PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / tcx.c
1 /*
2 * QEMU TCX Frame buffer
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "console.h"
26 #include "pixel_ops.h"
27 #include "sysbus.h"
28 #include "qdev-addr.h"
29
30 #define MAXX 1024
31 #define MAXY 768
32 #define TCX_DAC_NREGS 16
33 #define TCX_THC_NREGS_8 0x081c
34 #define TCX_THC_NREGS_24 0x1000
35 #define TCX_TEC_NREGS 0x1000
36
37 typedef struct TCXState {
38 SysBusDevice busdev;
39 target_phys_addr_t addr;
40 DisplayState *ds;
41 uint8_t *vram;
42 uint32_t *vram24, *cplane;
43 MemoryRegion vram_mem;
44 MemoryRegion vram_8bit;
45 MemoryRegion vram_24bit;
46 MemoryRegion vram_cplane;
47 MemoryRegion dac;
48 MemoryRegion tec;
49 MemoryRegion thc24;
50 MemoryRegion thc8;
51 ram_addr_t vram24_offset, cplane_offset;
52 uint32_t vram_size;
53 uint32_t palette[256];
54 uint8_t r[256], g[256], b[256];
55 uint16_t width, height, depth;
56 uint8_t dac_index, dac_state;
57 } TCXState;
58
59 static void tcx_screen_dump(void *opaque, const char *filename);
60 static void tcx24_screen_dump(void *opaque, const char *filename);
61
62 static void tcx_set_dirty(TCXState *s)
63 {
64 memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
65 }
66
67 static void tcx24_set_dirty(TCXState *s)
68 {
69 memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
70 memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
71 }
72
73 static void update_palette_entries(TCXState *s, int start, int end)
74 {
75 int i;
76 for(i = start; i < end; i++) {
77 switch(ds_get_bits_per_pixel(s->ds)) {
78 default:
79 case 8:
80 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
81 break;
82 case 15:
83 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
84 break;
85 case 16:
86 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
87 break;
88 case 32:
89 if (is_surface_bgr(s->ds->surface))
90 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
91 else
92 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
93 break;
94 }
95 }
96 if (s->depth == 24) {
97 tcx24_set_dirty(s);
98 } else {
99 tcx_set_dirty(s);
100 }
101 }
102
103 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
104 const uint8_t *s, int width)
105 {
106 int x;
107 uint8_t val;
108 uint32_t *p = (uint32_t *)d;
109
110 for(x = 0; x < width; x++) {
111 val = *s++;
112 *p++ = s1->palette[val];
113 }
114 }
115
116 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
117 const uint8_t *s, int width)
118 {
119 int x;
120 uint8_t val;
121 uint16_t *p = (uint16_t *)d;
122
123 for(x = 0; x < width; x++) {
124 val = *s++;
125 *p++ = s1->palette[val];
126 }
127 }
128
129 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
130 const uint8_t *s, int width)
131 {
132 int x;
133 uint8_t val;
134
135 for(x = 0; x < width; x++) {
136 val = *s++;
137 *d++ = s1->palette[val];
138 }
139 }
140
141 /*
142 XXX Could be much more optimal:
143 * detect if line/page/whole screen is in 24 bit mode
144 * if destination is also BGR, use memcpy
145 */
146 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
147 const uint8_t *s, int width,
148 const uint32_t *cplane,
149 const uint32_t *s24)
150 {
151 int x, bgr, r, g, b;
152 uint8_t val, *p8;
153 uint32_t *p = (uint32_t *)d;
154 uint32_t dval;
155
156 bgr = is_surface_bgr(s1->ds->surface);
157 for(x = 0; x < width; x++, s++, s24++) {
158 if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
159 // 24-bit direct, BGR order
160 p8 = (uint8_t *)s24;
161 p8++;
162 b = *p8++;
163 g = *p8++;
164 r = *p8;
165 if (bgr)
166 dval = rgb_to_pixel32bgr(r, g, b);
167 else
168 dval = rgb_to_pixel32(r, g, b);
169 } else {
170 val = *s;
171 dval = s1->palette[val];
172 }
173 *p++ = dval;
174 }
175 }
176
177 static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
178 ram_addr_t cpage)
179 {
180 int ret;
181 unsigned int off;
182
183 ret = memory_region_get_dirty(&s->vram_mem, page, DIRTY_MEMORY_VGA);
184 for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
185 ret |= memory_region_get_dirty(&s->vram_mem, page24 + off,
186 DIRTY_MEMORY_VGA);
187 ret |= memory_region_get_dirty(&s->vram_mem, cpage + off,
188 DIRTY_MEMORY_VGA);
189 }
190 return ret;
191 }
192
193 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
194 ram_addr_t page_max, ram_addr_t page24,
195 ram_addr_t cpage)
196 {
197 memory_region_reset_dirty(&ts->vram_mem,
198 page_min, page_max + TARGET_PAGE_SIZE,
199 DIRTY_MEMORY_VGA);
200 memory_region_reset_dirty(&ts->vram_mem,
201 page24 + page_min * 4,
202 page24 + page_max * 4 + TARGET_PAGE_SIZE,
203 DIRTY_MEMORY_VGA);
204 memory_region_reset_dirty(&ts->vram_mem,
205 cpage + page_min * 4,
206 cpage + page_max * 4 + TARGET_PAGE_SIZE,
207 DIRTY_MEMORY_VGA);
208 }
209
210 /* Fixed line length 1024 allows us to do nice tricks not possible on
211 VGA... */
212 static void tcx_update_display(void *opaque)
213 {
214 TCXState *ts = opaque;
215 ram_addr_t page, page_min, page_max;
216 int y, y_start, dd, ds;
217 uint8_t *d, *s;
218 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
219
220 if (ds_get_bits_per_pixel(ts->ds) == 0)
221 return;
222 page = 0;
223 y_start = -1;
224 page_min = -1;
225 page_max = 0;
226 d = ds_get_data(ts->ds);
227 s = ts->vram;
228 dd = ds_get_linesize(ts->ds);
229 ds = 1024;
230
231 switch (ds_get_bits_per_pixel(ts->ds)) {
232 case 32:
233 f = tcx_draw_line32;
234 break;
235 case 15:
236 case 16:
237 f = tcx_draw_line16;
238 break;
239 default:
240 case 8:
241 f = tcx_draw_line8;
242 break;
243 case 0:
244 return;
245 }
246
247 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
248 if (memory_region_get_dirty(&ts->vram_mem, page, DIRTY_MEMORY_VGA)) {
249 if (y_start < 0)
250 y_start = y;
251 if (page < page_min)
252 page_min = page;
253 if (page > page_max)
254 page_max = page;
255 f(ts, d, s, ts->width);
256 d += dd;
257 s += ds;
258 f(ts, d, s, ts->width);
259 d += dd;
260 s += ds;
261 f(ts, d, s, ts->width);
262 d += dd;
263 s += ds;
264 f(ts, d, s, ts->width);
265 d += dd;
266 s += ds;
267 } else {
268 if (y_start >= 0) {
269 /* flush to display */
270 dpy_update(ts->ds, 0, y_start,
271 ts->width, y - y_start);
272 y_start = -1;
273 }
274 d += dd * 4;
275 s += ds * 4;
276 }
277 }
278 if (y_start >= 0) {
279 /* flush to display */
280 dpy_update(ts->ds, 0, y_start,
281 ts->width, y - y_start);
282 }
283 /* reset modified pages */
284 if (page_max >= page_min) {
285 memory_region_reset_dirty(&ts->vram_mem,
286 page_min, page_max + TARGET_PAGE_SIZE,
287 DIRTY_MEMORY_VGA);
288 }
289 }
290
291 static void tcx24_update_display(void *opaque)
292 {
293 TCXState *ts = opaque;
294 ram_addr_t page, page_min, page_max, cpage, page24;
295 int y, y_start, dd, ds;
296 uint8_t *d, *s;
297 uint32_t *cptr, *s24;
298
299 if (ds_get_bits_per_pixel(ts->ds) != 32)
300 return;
301 page = 0;
302 page24 = ts->vram24_offset;
303 cpage = ts->cplane_offset;
304 y_start = -1;
305 page_min = -1;
306 page_max = 0;
307 d = ds_get_data(ts->ds);
308 s = ts->vram;
309 s24 = ts->vram24;
310 cptr = ts->cplane;
311 dd = ds_get_linesize(ts->ds);
312 ds = 1024;
313
314 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
315 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
316 if (check_dirty(ts, page, page24, cpage)) {
317 if (y_start < 0)
318 y_start = y;
319 if (page < page_min)
320 page_min = page;
321 if (page > page_max)
322 page_max = page;
323 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
324 d += dd;
325 s += ds;
326 cptr += ds;
327 s24 += ds;
328 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
329 d += dd;
330 s += ds;
331 cptr += ds;
332 s24 += ds;
333 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
334 d += dd;
335 s += ds;
336 cptr += ds;
337 s24 += ds;
338 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
339 d += dd;
340 s += ds;
341 cptr += ds;
342 s24 += ds;
343 } else {
344 if (y_start >= 0) {
345 /* flush to display */
346 dpy_update(ts->ds, 0, y_start,
347 ts->width, y - y_start);
348 y_start = -1;
349 }
350 d += dd * 4;
351 s += ds * 4;
352 cptr += ds * 4;
353 s24 += ds * 4;
354 }
355 }
356 if (y_start >= 0) {
357 /* flush to display */
358 dpy_update(ts->ds, 0, y_start,
359 ts->width, y - y_start);
360 }
361 /* reset modified pages */
362 if (page_max >= page_min) {
363 reset_dirty(ts, page_min, page_max, page24, cpage);
364 }
365 }
366
367 static void tcx_invalidate_display(void *opaque)
368 {
369 TCXState *s = opaque;
370
371 tcx_set_dirty(s);
372 qemu_console_resize(s->ds, s->width, s->height);
373 }
374
375 static void tcx24_invalidate_display(void *opaque)
376 {
377 TCXState *s = opaque;
378
379 tcx_set_dirty(s);
380 tcx24_set_dirty(s);
381 qemu_console_resize(s->ds, s->width, s->height);
382 }
383
384 static int vmstate_tcx_post_load(void *opaque, int version_id)
385 {
386 TCXState *s = opaque;
387
388 update_palette_entries(s, 0, 256);
389 if (s->depth == 24) {
390 tcx24_set_dirty(s);
391 } else {
392 tcx_set_dirty(s);
393 }
394
395 return 0;
396 }
397
398 static const VMStateDescription vmstate_tcx = {
399 .name ="tcx",
400 .version_id = 4,
401 .minimum_version_id = 4,
402 .minimum_version_id_old = 4,
403 .post_load = vmstate_tcx_post_load,
404 .fields = (VMStateField []) {
405 VMSTATE_UINT16(height, TCXState),
406 VMSTATE_UINT16(width, TCXState),
407 VMSTATE_UINT16(depth, TCXState),
408 VMSTATE_BUFFER(r, TCXState),
409 VMSTATE_BUFFER(g, TCXState),
410 VMSTATE_BUFFER(b, TCXState),
411 VMSTATE_UINT8(dac_index, TCXState),
412 VMSTATE_UINT8(dac_state, TCXState),
413 VMSTATE_END_OF_LIST()
414 }
415 };
416
417 static void tcx_reset(DeviceState *d)
418 {
419 TCXState *s = container_of(d, TCXState, busdev.qdev);
420
421 /* Initialize palette */
422 memset(s->r, 0, 256);
423 memset(s->g, 0, 256);
424 memset(s->b, 0, 256);
425 s->r[255] = s->g[255] = s->b[255] = 255;
426 update_palette_entries(s, 0, 256);
427 memset(s->vram, 0, MAXX*MAXY);
428 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
429 DIRTY_MEMORY_VGA);
430 s->dac_index = 0;
431 s->dac_state = 0;
432 }
433
434 static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
435 unsigned size)
436 {
437 return 0;
438 }
439
440 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
441 unsigned size)
442 {
443 TCXState *s = opaque;
444
445 switch (addr) {
446 case 0:
447 s->dac_index = val >> 24;
448 s->dac_state = 0;
449 break;
450 case 4:
451 switch (s->dac_state) {
452 case 0:
453 s->r[s->dac_index] = val >> 24;
454 update_palette_entries(s, s->dac_index, s->dac_index + 1);
455 s->dac_state++;
456 break;
457 case 1:
458 s->g[s->dac_index] = val >> 24;
459 update_palette_entries(s, s->dac_index, s->dac_index + 1);
460 s->dac_state++;
461 break;
462 case 2:
463 s->b[s->dac_index] = val >> 24;
464 update_palette_entries(s, s->dac_index, s->dac_index + 1);
465 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
466 default:
467 s->dac_state = 0;
468 break;
469 }
470 break;
471 default:
472 break;
473 }
474 return;
475 }
476
477 static const MemoryRegionOps tcx_dac_ops = {
478 .read = tcx_dac_readl,
479 .write = tcx_dac_writel,
480 .endianness = DEVICE_NATIVE_ENDIAN,
481 .valid = {
482 .min_access_size = 4,
483 .max_access_size = 4,
484 },
485 };
486
487 static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
488 unsigned size)
489 {
490 return 0;
491 }
492
493 static void dummy_writel(void *opaque, target_phys_addr_t addr,
494 uint64_t val, unsigned size)
495 {
496 }
497
498 static const MemoryRegionOps dummy_ops = {
499 .read = dummy_readl,
500 .write = dummy_writel,
501 .endianness = DEVICE_NATIVE_ENDIAN,
502 .valid = {
503 .min_access_size = 4,
504 .max_access_size = 4,
505 },
506 };
507
508 static int tcx_init1(SysBusDevice *dev)
509 {
510 TCXState *s = FROM_SYSBUS(TCXState, dev);
511 ram_addr_t vram_offset = 0;
512 int size;
513 uint8_t *vram_base;
514
515 memory_region_init_ram(&s->vram_mem, "tcx.vram",
516 s->vram_size * (1 + 4 + 4));
517 vmstate_register_ram_global(&s->vram_mem);
518 vram_base = memory_region_get_ram_ptr(&s->vram_mem);
519
520 /* 8-bit plane */
521 s->vram = vram_base;
522 size = s->vram_size;
523 memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
524 &s->vram_mem, vram_offset, size);
525 sysbus_init_mmio(dev, &s->vram_8bit);
526 vram_offset += size;
527 vram_base += size;
528
529 /* DAC */
530 memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
531 sysbus_init_mmio(dev, &s->dac);
532
533 /* TEC (dummy) */
534 memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
535 sysbus_init_mmio(dev, &s->tec);
536 /* THC: NetBSD writes here even with 8-bit display: dummy */
537 memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
538 TCX_THC_NREGS_24);
539 sysbus_init_mmio(dev, &s->thc24);
540
541 if (s->depth == 24) {
542 /* 24-bit plane */
543 size = s->vram_size * 4;
544 s->vram24 = (uint32_t *)vram_base;
545 s->vram24_offset = vram_offset;
546 memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
547 &s->vram_mem, vram_offset, size);
548 sysbus_init_mmio(dev, &s->vram_24bit);
549 vram_offset += size;
550 vram_base += size;
551
552 /* Control plane */
553 size = s->vram_size * 4;
554 s->cplane = (uint32_t *)vram_base;
555 s->cplane_offset = vram_offset;
556 memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
557 &s->vram_mem, vram_offset, size);
558 sysbus_init_mmio(dev, &s->vram_cplane);
559
560 s->ds = graphic_console_init(tcx24_update_display,
561 tcx24_invalidate_display,
562 tcx24_screen_dump, NULL, s);
563 } else {
564 /* THC 8 bit (dummy) */
565 memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
566 TCX_THC_NREGS_8);
567 sysbus_init_mmio(dev, &s->thc8);
568
569 s->ds = graphic_console_init(tcx_update_display,
570 tcx_invalidate_display,
571 tcx_screen_dump, NULL, s);
572 }
573
574 qemu_console_resize(s->ds, s->width, s->height);
575 return 0;
576 }
577
578 static void tcx_screen_dump(void *opaque, const char *filename)
579 {
580 TCXState *s = opaque;
581 FILE *f;
582 uint8_t *d, *d1, v;
583 int y, x;
584
585 f = fopen(filename, "wb");
586 if (!f)
587 return;
588 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
589 d1 = s->vram;
590 for(y = 0; y < s->height; y++) {
591 d = d1;
592 for(x = 0; x < s->width; x++) {
593 v = *d;
594 fputc(s->r[v], f);
595 fputc(s->g[v], f);
596 fputc(s->b[v], f);
597 d++;
598 }
599 d1 += MAXX;
600 }
601 fclose(f);
602 return;
603 }
604
605 static void tcx24_screen_dump(void *opaque, const char *filename)
606 {
607 TCXState *s = opaque;
608 FILE *f;
609 uint8_t *d, *d1, v;
610 uint32_t *s24, *cptr, dval;
611 int y, x;
612
613 f = fopen(filename, "wb");
614 if (!f)
615 return;
616 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
617 d1 = s->vram;
618 s24 = s->vram24;
619 cptr = s->cplane;
620 for(y = 0; y < s->height; y++) {
621 d = d1;
622 for(x = 0; x < s->width; x++, d++, s24++) {
623 if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
624 dval = *s24 & 0x00ffffff;
625 fputc((dval >> 16) & 0xff, f);
626 fputc((dval >> 8) & 0xff, f);
627 fputc(dval & 0xff, f);
628 } else {
629 v = *d;
630 fputc(s->r[v], f);
631 fputc(s->g[v], f);
632 fputc(s->b[v], f);
633 }
634 }
635 d1 += MAXX;
636 }
637 fclose(f);
638 return;
639 }
640
641 static Property tcx_properties[] = {
642 DEFINE_PROP_TADDR("addr", TCXState, addr, -1),
643 DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
644 DEFINE_PROP_UINT16("width", TCXState, width, -1),
645 DEFINE_PROP_UINT16("height", TCXState, height, -1),
646 DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
647 DEFINE_PROP_END_OF_LIST(),
648 };
649
650 static void tcx_class_init(ObjectClass *klass, void *data)
651 {
652 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
653
654 k->init = tcx_init1;
655 }
656
657 static DeviceInfo tcx_info = {
658 .name = "SUNW,tcx",
659 .size = sizeof(TCXState),
660 .reset = tcx_reset,
661 .vmsd = &vmstate_tcx,
662 .props = tcx_properties,
663 .class_init = tcx_class_init,
664 };
665
666 static void tcx_register_devices(void)
667 {
668 sysbus_register_withprop(&tcx_info);
669 }
670
671 device_init(tcx_register_devices)