meson: convert hw/vfio
[qemu.git] / hw / timer / i8254.c
1 /*
2 * QEMU 8253/8254 interval timer emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/irq.h"
27 #include "qemu/module.h"
28 #include "qemu/timer.h"
29 #include "hw/timer/i8254.h"
30 #include "hw/timer/i8254_internal.h"
31
32 //#define DEBUG_PIT
33
34 #define RW_STATE_LSB 1
35 #define RW_STATE_MSB 2
36 #define RW_STATE_WORD0 3
37 #define RW_STATE_WORD1 4
38
39 #define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254)
40 #define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254)
41
42 typedef struct PITClass {
43 PITCommonClass parent_class;
44
45 DeviceRealize parent_realize;
46 } PITClass;
47
48 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
49
50 static int pit_get_count(PITChannelState *s)
51 {
52 uint64_t d;
53 int counter;
54
55 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ,
56 NANOSECONDS_PER_SECOND);
57 switch(s->mode) {
58 case 0:
59 case 1:
60 case 4:
61 case 5:
62 counter = (s->count - d) & 0xffff;
63 break;
64 case 3:
65 /* XXX: may be incorrect for odd counts */
66 counter = s->count - ((2 * d) % s->count);
67 break;
68 default:
69 counter = s->count - (d % s->count);
70 break;
71 }
72 return counter;
73 }
74
75 /* val must be 0 or 1 */
76 static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
77 int val)
78 {
79 switch (sc->mode) {
80 default:
81 case 0:
82 case 4:
83 /* XXX: just disable/enable counting */
84 break;
85 case 1:
86 case 5:
87 if (sc->gate < val) {
88 /* restart counting on rising edge */
89 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
90 pit_irq_timer_update(sc, sc->count_load_time);
91 }
92 break;
93 case 2:
94 case 3:
95 if (sc->gate < val) {
96 /* restart counting on rising edge */
97 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
98 pit_irq_timer_update(sc, sc->count_load_time);
99 }
100 /* XXX: disable/enable counting */
101 break;
102 }
103 sc->gate = val;
104 }
105
106 static inline void pit_load_count(PITChannelState *s, int val)
107 {
108 if (val == 0)
109 val = 0x10000;
110 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
111 s->count = val;
112 pit_irq_timer_update(s, s->count_load_time);
113 }
114
115 /* if already latched, do not latch again */
116 static void pit_latch_count(PITChannelState *s)
117 {
118 if (!s->count_latched) {
119 s->latched_count = pit_get_count(s);
120 s->count_latched = s->rw_mode;
121 }
122 }
123
124 static void pit_ioport_write(void *opaque, hwaddr addr,
125 uint64_t val, unsigned size)
126 {
127 PITCommonState *pit = opaque;
128 int channel, access;
129 PITChannelState *s;
130
131 addr &= 3;
132 if (addr == 3) {
133 channel = val >> 6;
134 if (channel == 3) {
135 /* read back command */
136 for(channel = 0; channel < 3; channel++) {
137 s = &pit->channels[channel];
138 if (val & (2 << channel)) {
139 if (!(val & 0x20)) {
140 pit_latch_count(s);
141 }
142 if (!(val & 0x10) && !s->status_latched) {
143 /* status latch */
144 /* XXX: add BCD and null count */
145 s->status =
146 (pit_get_out(s,
147 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) |
148 (s->rw_mode << 4) |
149 (s->mode << 1) |
150 s->bcd;
151 s->status_latched = 1;
152 }
153 }
154 }
155 } else {
156 s = &pit->channels[channel];
157 access = (val >> 4) & 3;
158 if (access == 0) {
159 pit_latch_count(s);
160 } else {
161 s->rw_mode = access;
162 s->read_state = access;
163 s->write_state = access;
164
165 s->mode = (val >> 1) & 7;
166 s->bcd = val & 1;
167 /* XXX: update irq timer ? */
168 }
169 }
170 } else {
171 s = &pit->channels[addr];
172 switch(s->write_state) {
173 default:
174 case RW_STATE_LSB:
175 pit_load_count(s, val);
176 break;
177 case RW_STATE_MSB:
178 pit_load_count(s, val << 8);
179 break;
180 case RW_STATE_WORD0:
181 s->write_latch = val;
182 s->write_state = RW_STATE_WORD1;
183 break;
184 case RW_STATE_WORD1:
185 pit_load_count(s, s->write_latch | (val << 8));
186 s->write_state = RW_STATE_WORD0;
187 break;
188 }
189 }
190 }
191
192 static uint64_t pit_ioport_read(void *opaque, hwaddr addr,
193 unsigned size)
194 {
195 PITCommonState *pit = opaque;
196 int ret, count;
197 PITChannelState *s;
198
199 addr &= 3;
200
201 if (addr == 3) {
202 /* Mode/Command register is write only, read is ignored */
203 return 0;
204 }
205
206 s = &pit->channels[addr];
207 if (s->status_latched) {
208 s->status_latched = 0;
209 ret = s->status;
210 } else if (s->count_latched) {
211 switch(s->count_latched) {
212 default:
213 case RW_STATE_LSB:
214 ret = s->latched_count & 0xff;
215 s->count_latched = 0;
216 break;
217 case RW_STATE_MSB:
218 ret = s->latched_count >> 8;
219 s->count_latched = 0;
220 break;
221 case RW_STATE_WORD0:
222 ret = s->latched_count & 0xff;
223 s->count_latched = RW_STATE_MSB;
224 break;
225 }
226 } else {
227 switch(s->read_state) {
228 default:
229 case RW_STATE_LSB:
230 count = pit_get_count(s);
231 ret = count & 0xff;
232 break;
233 case RW_STATE_MSB:
234 count = pit_get_count(s);
235 ret = (count >> 8) & 0xff;
236 break;
237 case RW_STATE_WORD0:
238 count = pit_get_count(s);
239 ret = count & 0xff;
240 s->read_state = RW_STATE_WORD1;
241 break;
242 case RW_STATE_WORD1:
243 count = pit_get_count(s);
244 ret = (count >> 8) & 0xff;
245 s->read_state = RW_STATE_WORD0;
246 break;
247 }
248 }
249 return ret;
250 }
251
252 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
253 {
254 int64_t expire_time;
255 int irq_level;
256
257 if (!s->irq_timer || s->irq_disabled) {
258 return;
259 }
260 expire_time = pit_get_next_transition_time(s, current_time);
261 irq_level = pit_get_out(s, current_time);
262 qemu_set_irq(s->irq, irq_level);
263 #ifdef DEBUG_PIT
264 printf("irq_level=%d next_delay=%f\n",
265 irq_level,
266 (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND);
267 #endif
268 s->next_transition_time = expire_time;
269 if (expire_time != -1)
270 timer_mod(s->irq_timer, expire_time);
271 else
272 timer_del(s->irq_timer);
273 }
274
275 static void pit_irq_timer(void *opaque)
276 {
277 PITChannelState *s = opaque;
278
279 pit_irq_timer_update(s, s->next_transition_time);
280 }
281
282 static void pit_reset(DeviceState *dev)
283 {
284 PITCommonState *pit = PIT_COMMON(dev);
285 PITChannelState *s;
286
287 pit_reset_common(pit);
288
289 s = &pit->channels[0];
290 if (!s->irq_disabled) {
291 timer_mod(s->irq_timer, s->next_transition_time);
292 }
293 }
294
295 /* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
296 * reenable it when legacy mode is left again. */
297 static void pit_irq_control(void *opaque, int n, int enable)
298 {
299 PITCommonState *pit = opaque;
300 PITChannelState *s = &pit->channels[0];
301
302 if (enable) {
303 s->irq_disabled = 0;
304 pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
305 } else {
306 s->irq_disabled = 1;
307 timer_del(s->irq_timer);
308 }
309 }
310
311 static const MemoryRegionOps pit_ioport_ops = {
312 .read = pit_ioport_read,
313 .write = pit_ioport_write,
314 .impl = {
315 .min_access_size = 1,
316 .max_access_size = 1,
317 },
318 .endianness = DEVICE_LITTLE_ENDIAN,
319 };
320
321 static void pit_post_load(PITCommonState *s)
322 {
323 PITChannelState *sc = &s->channels[0];
324
325 if (sc->next_transition_time != -1) {
326 timer_mod(sc->irq_timer, sc->next_transition_time);
327 } else {
328 timer_del(sc->irq_timer);
329 }
330 }
331
332 static void pit_realizefn(DeviceState *dev, Error **errp)
333 {
334 PITCommonState *pit = PIT_COMMON(dev);
335 PITClass *pc = PIT_GET_CLASS(dev);
336 PITChannelState *s;
337
338 s = &pit->channels[0];
339 /* the timer 0 is connected to an IRQ */
340 s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s);
341 qdev_init_gpio_out(dev, &s->irq, 1);
342
343 memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops,
344 pit, "pit", 4);
345
346 qdev_init_gpio_in(dev, pit_irq_control, 1);
347
348 pc->parent_realize(dev, errp);
349 }
350
351 static Property pit_properties[] = {
352 DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
353 DEFINE_PROP_END_OF_LIST(),
354 };
355
356 static void pit_class_initfn(ObjectClass *klass, void *data)
357 {
358 PITClass *pc = PIT_CLASS(klass);
359 PITCommonClass *k = PIT_COMMON_CLASS(klass);
360 DeviceClass *dc = DEVICE_CLASS(klass);
361
362 device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize);
363 k->set_channel_gate = pit_set_channel_gate;
364 k->get_channel_info = pit_get_channel_info_common;
365 k->post_load = pit_post_load;
366 dc->reset = pit_reset;
367 device_class_set_props(dc, pit_properties);
368 }
369
370 static const TypeInfo pit_info = {
371 .name = TYPE_I8254,
372 .parent = TYPE_PIT_COMMON,
373 .instance_size = sizeof(PITCommonState),
374 .class_init = pit_class_initfn,
375 .class_size = sizeof(PITClass),
376 };
377
378 static void pit_register_types(void)
379 {
380 type_register_static(&pit_info);
381 }
382
383 type_init(pit_register_types)