Update version for v6.2.0-rc4 release
[qemu.git] / hw / timer / i8254_common.c
1 /*
2 * QEMU 8253/8254 - common bits of emulated and KVM kernel model
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2012 Jan Kiszka, Siemens AG
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/isa/isa.h"
28 #include "qemu/module.h"
29 #include "qemu/timer.h"
30 #include "hw/timer/i8254.h"
31 #include "hw/timer/i8254_internal.h"
32 #include "migration/vmstate.h"
33
34 /* val must be 0 or 1 */
35 void pit_set_gate(ISADevice *dev, int channel, int val)
36 {
37 PITCommonState *pit = PIT_COMMON(dev);
38 PITChannelState *s = &pit->channels[channel];
39 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
40
41 c->set_channel_gate(pit, s, val);
42 }
43
44 /* get pit output bit */
45 int pit_get_out(PITChannelState *s, int64_t current_time)
46 {
47 uint64_t d;
48 int out;
49
50 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
51 NANOSECONDS_PER_SECOND);
52 switch (s->mode) {
53 default:
54 case 0:
55 out = (d >= s->count);
56 break;
57 case 1:
58 out = (d < s->count);
59 break;
60 case 2:
61 if ((d % s->count) == 0 && d != 0) {
62 out = 1;
63 } else {
64 out = 0;
65 }
66 break;
67 case 3:
68 out = (d % s->count) < ((s->count + 1) >> 1);
69 break;
70 case 4:
71 case 5:
72 out = (d == s->count);
73 break;
74 }
75 return out;
76 }
77
78 /* return -1 if no transition will occur. */
79 int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
80 {
81 uint64_t d, next_time, base;
82 int period2;
83
84 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
85 NANOSECONDS_PER_SECOND);
86 switch (s->mode) {
87 default:
88 case 0:
89 case 1:
90 if (d < s->count) {
91 next_time = s->count;
92 } else {
93 return -1;
94 }
95 break;
96 case 2:
97 base = QEMU_ALIGN_DOWN(d, s->count);
98 if ((d - base) == 0 && d != 0) {
99 next_time = base + s->count;
100 } else {
101 next_time = base + s->count + 1;
102 }
103 break;
104 case 3:
105 base = QEMU_ALIGN_DOWN(d, s->count);
106 period2 = ((s->count + 1) >> 1);
107 if ((d - base) < period2) {
108 next_time = base + period2;
109 } else {
110 next_time = base + s->count;
111 }
112 break;
113 case 4:
114 case 5:
115 if (d < s->count) {
116 next_time = s->count;
117 } else if (d == s->count) {
118 next_time = s->count + 1;
119 } else {
120 return -1;
121 }
122 break;
123 }
124 /* convert to timer units */
125 next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND,
126 PIT_FREQ);
127 /* fix potential rounding problems */
128 /* XXX: better solution: use a clock at PIT_FREQ Hz */
129 if (next_time <= current_time) {
130 next_time = current_time + 1;
131 }
132 return next_time;
133 }
134
135 void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
136 PITChannelInfo *info)
137 {
138 info->gate = sc->gate;
139 info->mode = sc->mode;
140 info->initial_count = sc->count;
141 info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
142 }
143
144 void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
145 {
146 PITCommonState *pit = PIT_COMMON(dev);
147 PITChannelState *s = &pit->channels[channel];
148 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
149
150 c->get_channel_info(pit, s, info);
151 }
152
153 void pit_reset_common(PITCommonState *pit)
154 {
155 PITChannelState *s;
156 int i;
157
158 for (i = 0; i < 3; i++) {
159 s = &pit->channels[i];
160 s->mode = 3;
161 s->gate = (i != 2);
162 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
163 s->count = 0x10000;
164 if (i == 0 && !s->irq_disabled) {
165 s->next_transition_time =
166 pit_get_next_transition_time(s, s->count_load_time);
167 }
168 }
169 }
170
171 static void pit_common_realize(DeviceState *dev, Error **errp)
172 {
173 ISADevice *isadev = ISA_DEVICE(dev);
174 PITCommonState *pit = PIT_COMMON(dev);
175
176 isa_register_ioport(isadev, &pit->ioports, pit->iobase);
177
178 qdev_set_legacy_instance_id(dev, pit->iobase, 2);
179 }
180
181 static const VMStateDescription vmstate_pit_channel = {
182 .name = "pit channel",
183 .version_id = 2,
184 .minimum_version_id = 2,
185 .fields = (VMStateField[]) {
186 VMSTATE_INT32(count, PITChannelState),
187 VMSTATE_UINT16(latched_count, PITChannelState),
188 VMSTATE_UINT8(count_latched, PITChannelState),
189 VMSTATE_UINT8(status_latched, PITChannelState),
190 VMSTATE_UINT8(status, PITChannelState),
191 VMSTATE_UINT8(read_state, PITChannelState),
192 VMSTATE_UINT8(write_state, PITChannelState),
193 VMSTATE_UINT8(write_latch, PITChannelState),
194 VMSTATE_UINT8(rw_mode, PITChannelState),
195 VMSTATE_UINT8(mode, PITChannelState),
196 VMSTATE_UINT8(bcd, PITChannelState),
197 VMSTATE_UINT8(gate, PITChannelState),
198 VMSTATE_INT64(count_load_time, PITChannelState),
199 VMSTATE_INT64(next_transition_time, PITChannelState),
200 VMSTATE_END_OF_LIST()
201 }
202 };
203
204 static int pit_dispatch_pre_save(void *opaque)
205 {
206 PITCommonState *s = opaque;
207 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
208
209 if (c->pre_save) {
210 c->pre_save(s);
211 }
212
213 return 0;
214 }
215
216 static int pit_dispatch_post_load(void *opaque, int version_id)
217 {
218 PITCommonState *s = opaque;
219 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
220
221 if (c->post_load) {
222 c->post_load(s);
223 }
224 return 0;
225 }
226
227 static const VMStateDescription vmstate_pit_common = {
228 .name = "i8254",
229 .version_id = 3,
230 .minimum_version_id = 2,
231 .pre_save = pit_dispatch_pre_save,
232 .post_load = pit_dispatch_post_load,
233 .fields = (VMStateField[]) {
234 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
235 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
236 vmstate_pit_channel, PITChannelState),
237 VMSTATE_INT64(channels[0].next_transition_time,
238 PITCommonState), /* formerly irq_timer */
239 VMSTATE_END_OF_LIST()
240 }
241 };
242
243 static void pit_common_class_init(ObjectClass *klass, void *data)
244 {
245 DeviceClass *dc = DEVICE_CLASS(klass);
246
247 dc->realize = pit_common_realize;
248 dc->vmsd = &vmstate_pit_common;
249 /*
250 * Reason: unlike ordinary ISA devices, the PIT may need to be
251 * wired to the HPET, and because of that, some wiring is always
252 * done by board code.
253 */
254 dc->user_creatable = false;
255 }
256
257 static const TypeInfo pit_common_type = {
258 .name = TYPE_PIT_COMMON,
259 .parent = TYPE_ISA_DEVICE,
260 .instance_size = sizeof(PITCommonState),
261 .class_size = sizeof(PITCommonClass),
262 .class_init = pit_common_class_init,
263 .abstract = true,
264 };
265
266 static void register_devices(void)
267 {
268 type_register_static(&pit_common_type);
269 }
270
271 type_init(register_devices);