xen/pt: allow QEMU to request MSI unmasking at bind time
[qemu.git] / hw / timer / i8254_common.c
1 /*
2 * QEMU 8253/8254 - common bits of emulated and KVM kernel model
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2012 Jan Kiszka, Siemens AG
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/i386/pc.h"
28 #include "hw/isa/isa.h"
29 #include "qemu/timer.h"
30 #include "hw/timer/i8254.h"
31 #include "hw/timer/i8254_internal.h"
32
33 /* val must be 0 or 1 */
34 void pit_set_gate(ISADevice *dev, int channel, int val)
35 {
36 PITCommonState *pit = PIT_COMMON(dev);
37 PITChannelState *s = &pit->channels[channel];
38 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
39
40 c->set_channel_gate(pit, s, val);
41 }
42
43 /* get pit output bit */
44 int pit_get_out(PITChannelState *s, int64_t current_time)
45 {
46 uint64_t d;
47 int out;
48
49 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
50 NANOSECONDS_PER_SECOND);
51 switch (s->mode) {
52 default:
53 case 0:
54 out = (d >= s->count);
55 break;
56 case 1:
57 out = (d < s->count);
58 break;
59 case 2:
60 if ((d % s->count) == 0 && d != 0) {
61 out = 1;
62 } else {
63 out = 0;
64 }
65 break;
66 case 3:
67 out = (d % s->count) < ((s->count + 1) >> 1);
68 break;
69 case 4:
70 case 5:
71 out = (d == s->count);
72 break;
73 }
74 return out;
75 }
76
77 /* return -1 if no transition will occur. */
78 int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
79 {
80 uint64_t d, next_time, base;
81 int period2;
82
83 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
84 NANOSECONDS_PER_SECOND);
85 switch (s->mode) {
86 default:
87 case 0:
88 case 1:
89 if (d < s->count) {
90 next_time = s->count;
91 } else {
92 return -1;
93 }
94 break;
95 case 2:
96 base = QEMU_ALIGN_DOWN(d, s->count);
97 if ((d - base) == 0 && d != 0) {
98 next_time = base + s->count;
99 } else {
100 next_time = base + s->count + 1;
101 }
102 break;
103 case 3:
104 base = QEMU_ALIGN_DOWN(d, s->count);
105 period2 = ((s->count + 1) >> 1);
106 if ((d - base) < period2) {
107 next_time = base + period2;
108 } else {
109 next_time = base + s->count;
110 }
111 break;
112 case 4:
113 case 5:
114 if (d < s->count) {
115 next_time = s->count;
116 } else if (d == s->count) {
117 next_time = s->count + 1;
118 } else {
119 return -1;
120 }
121 break;
122 }
123 /* convert to timer units */
124 next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND,
125 PIT_FREQ);
126 /* fix potential rounding problems */
127 /* XXX: better solution: use a clock at PIT_FREQ Hz */
128 if (next_time <= current_time) {
129 next_time = current_time + 1;
130 }
131 return next_time;
132 }
133
134 void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
135 PITChannelInfo *info)
136 {
137 info->gate = sc->gate;
138 info->mode = sc->mode;
139 info->initial_count = sc->count;
140 info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
141 }
142
143 void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
144 {
145 PITCommonState *pit = PIT_COMMON(dev);
146 PITChannelState *s = &pit->channels[channel];
147 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
148
149 c->get_channel_info(pit, s, info);
150 }
151
152 void pit_reset_common(PITCommonState *pit)
153 {
154 PITChannelState *s;
155 int i;
156
157 for (i = 0; i < 3; i++) {
158 s = &pit->channels[i];
159 s->mode = 3;
160 s->gate = (i != 2);
161 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
162 s->count = 0x10000;
163 if (i == 0 && !s->irq_disabled) {
164 s->next_transition_time =
165 pit_get_next_transition_time(s, s->count_load_time);
166 }
167 }
168 }
169
170 static void pit_common_realize(DeviceState *dev, Error **errp)
171 {
172 ISADevice *isadev = ISA_DEVICE(dev);
173 PITCommonState *pit = PIT_COMMON(dev);
174
175 isa_register_ioport(isadev, &pit->ioports, pit->iobase);
176
177 qdev_set_legacy_instance_id(dev, pit->iobase, 2);
178 }
179
180 static const VMStateDescription vmstate_pit_channel = {
181 .name = "pit channel",
182 .version_id = 2,
183 .minimum_version_id = 2,
184 .fields = (VMStateField[]) {
185 VMSTATE_INT32(count, PITChannelState),
186 VMSTATE_UINT16(latched_count, PITChannelState),
187 VMSTATE_UINT8(count_latched, PITChannelState),
188 VMSTATE_UINT8(status_latched, PITChannelState),
189 VMSTATE_UINT8(status, PITChannelState),
190 VMSTATE_UINT8(read_state, PITChannelState),
191 VMSTATE_UINT8(write_state, PITChannelState),
192 VMSTATE_UINT8(write_latch, PITChannelState),
193 VMSTATE_UINT8(rw_mode, PITChannelState),
194 VMSTATE_UINT8(mode, PITChannelState),
195 VMSTATE_UINT8(bcd, PITChannelState),
196 VMSTATE_UINT8(gate, PITChannelState),
197 VMSTATE_INT64(count_load_time, PITChannelState),
198 VMSTATE_INT64(next_transition_time, PITChannelState),
199 VMSTATE_END_OF_LIST()
200 }
201 };
202
203 static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
204 {
205 PITCommonState *pit = opaque;
206 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
207 PITChannelState *s;
208 int i;
209
210 if (version_id != 1) {
211 return -EINVAL;
212 }
213
214 for (i = 0; i < 3; i++) {
215 s = &pit->channels[i];
216 s->count = qemu_get_be32(f);
217 qemu_get_be16s(f, &s->latched_count);
218 qemu_get_8s(f, &s->count_latched);
219 qemu_get_8s(f, &s->status_latched);
220 qemu_get_8s(f, &s->status);
221 qemu_get_8s(f, &s->read_state);
222 qemu_get_8s(f, &s->write_state);
223 qemu_get_8s(f, &s->write_latch);
224 qemu_get_8s(f, &s->rw_mode);
225 qemu_get_8s(f, &s->mode);
226 qemu_get_8s(f, &s->bcd);
227 qemu_get_8s(f, &s->gate);
228 s->count_load_time = qemu_get_be64(f);
229 s->irq_disabled = 0;
230 if (i == 0) {
231 s->next_transition_time = qemu_get_be64(f);
232 }
233 }
234 if (c->post_load) {
235 c->post_load(pit);
236 }
237 return 0;
238 }
239
240 static void pit_dispatch_pre_save(void *opaque)
241 {
242 PITCommonState *s = opaque;
243 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
244
245 if (c->pre_save) {
246 c->pre_save(s);
247 }
248 }
249
250 static int pit_dispatch_post_load(void *opaque, int version_id)
251 {
252 PITCommonState *s = opaque;
253 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
254
255 if (c->post_load) {
256 c->post_load(s);
257 }
258 return 0;
259 }
260
261 static const VMStateDescription vmstate_pit_common = {
262 .name = "i8254",
263 .version_id = 3,
264 .minimum_version_id = 2,
265 .minimum_version_id_old = 1,
266 .load_state_old = pit_load_old,
267 .pre_save = pit_dispatch_pre_save,
268 .post_load = pit_dispatch_post_load,
269 .fields = (VMStateField[]) {
270 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
271 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
272 vmstate_pit_channel, PITChannelState),
273 VMSTATE_INT64(channels[0].next_transition_time,
274 PITCommonState), /* formerly irq_timer */
275 VMSTATE_END_OF_LIST()
276 }
277 };
278
279 static void pit_common_class_init(ObjectClass *klass, void *data)
280 {
281 DeviceClass *dc = DEVICE_CLASS(klass);
282
283 dc->realize = pit_common_realize;
284 dc->vmsd = &vmstate_pit_common;
285 /*
286 * Reason: unlike ordinary ISA devices, the PIT may need to be
287 * wired to the HPET, and because of that, some wiring is always
288 * done by board code.
289 */
290 dc->user_creatable = false;
291 }
292
293 static const TypeInfo pit_common_type = {
294 .name = TYPE_PIT_COMMON,
295 .parent = TYPE_ISA_DEVICE,
296 .instance_size = sizeof(PITCommonState),
297 .class_size = sizeof(PITCommonClass),
298 .class_init = pit_common_class_init,
299 .abstract = true,
300 };
301
302 static void register_devices(void)
303 {
304 type_register_static(&pit_common_type);
305 }
306
307 type_init(register_devices);