xen/pt: allow QEMU to request MSI unmasking at bind time
[qemu.git] / hw / timer / m48t59-isa.c
1 /*
2 * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface
3 *
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "hw/isa/isa.h"
27 #include "hw/timer/m48t59.h"
28 #include "m48t59-internal.h"
29
30 #define TYPE_M48TXX_ISA "isa-m48txx"
31 #define M48TXX_ISA_GET_CLASS(obj) \
32 OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
33 #define M48TXX_ISA_CLASS(klass) \
34 OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
35 #define M48TXX_ISA(obj) \
36 OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
37
38 typedef struct M48txxISAState {
39 ISADevice parent_obj;
40 M48t59State state;
41 uint32_t io_base;
42 MemoryRegion io;
43 } M48txxISAState;
44
45 typedef struct M48txxISADeviceClass {
46 ISADeviceClass parent_class;
47 M48txxInfo info;
48 } M48txxISADeviceClass;
49
50 static M48txxInfo m48txx_isa_info[] = {
51 {
52 .bus_name = "isa-m48t59",
53 .model = 59,
54 .size = 0x2000,
55 }
56 };
57
58 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
59 int base_year, int model)
60 {
61 DeviceState *dev;
62 int i;
63
64 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
65 if (m48txx_isa_info[i].size != size ||
66 m48txx_isa_info[i].model != model) {
67 continue;
68 }
69
70 dev = DEVICE(isa_create(bus, m48txx_isa_info[i].bus_name));
71 qdev_prop_set_uint32(dev, "iobase", io_base);
72 qdev_prop_set_int32(dev, "base-year", base_year);
73 qdev_init_nofail(dev);
74 return NVRAM(dev);
75 }
76
77 assert(false);
78 return NULL;
79 }
80
81 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
82 {
83 M48txxISAState *d = M48TXX_ISA(obj);
84 return m48t59_read(&d->state, addr);
85 }
86
87 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
88 {
89 M48txxISAState *d = M48TXX_ISA(obj);
90 m48t59_write(&d->state, addr, val);
91 }
92
93 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
94 {
95 M48txxISAState *d = M48TXX_ISA(obj);
96 m48t59_toggle_lock(&d->state, lock);
97 }
98
99 static Property m48t59_isa_properties[] = {
100 DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
101 DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
102 DEFINE_PROP_END_OF_LIST(),
103 };
104
105 static void m48t59_reset_isa(DeviceState *d)
106 {
107 M48txxISAState *isa = M48TXX_ISA(d);
108 M48t59State *NVRAM = &isa->state;
109
110 m48t59_reset_common(NVRAM);
111 }
112
113 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
114 {
115 M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
116 ISADevice *isadev = ISA_DEVICE(dev);
117 M48txxISAState *d = M48TXX_ISA(dev);
118 M48t59State *s = &d->state;
119
120 s->model = u->info.model;
121 s->size = u->info.size;
122 isa_init_irq(isadev, &s->IRQ, 8);
123 m48t59_realize_common(s, errp);
124 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
125 if (d->io_base != 0) {
126 isa_register_ioport(isadev, &d->io, d->io_base);
127 }
128 }
129
130 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
131 {
132 DeviceClass *dc = DEVICE_CLASS(klass);
133 NvramClass *nc = NVRAM_CLASS(klass);
134
135 dc->realize = m48t59_isa_realize;
136 dc->reset = m48t59_reset_isa;
137 dc->props = m48t59_isa_properties;
138 nc->read = m48txx_isa_read;
139 nc->write = m48txx_isa_write;
140 nc->toggle_lock = m48txx_isa_toggle_lock;
141 }
142
143 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
144 {
145 M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
146 M48txxInfo *info = data;
147
148 u->info = *info;
149 }
150
151 static const TypeInfo m48txx_isa_type_info = {
152 .name = TYPE_M48TXX_ISA,
153 .parent = TYPE_ISA_DEVICE,
154 .instance_size = sizeof(M48txxISAState),
155 .abstract = true,
156 .class_init = m48txx_isa_class_init,
157 .interfaces = (InterfaceInfo[]) {
158 { TYPE_NVRAM },
159 { }
160 }
161 };
162
163 static void m48t59_isa_register_types(void)
164 {
165 TypeInfo isa_type_info = {
166 .parent = TYPE_M48TXX_ISA,
167 .class_size = sizeof(M48txxISADeviceClass),
168 .class_init = m48txx_isa_concrete_class_init,
169 };
170 int i;
171
172 type_register_static(&m48txx_isa_type_info);
173
174 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
175 isa_type_info.name = m48txx_isa_info[i].bus_name;
176 isa_type_info.class_data = &m48txx_isa_info[i];
177 type_register(&isa_type_info);
178 }
179 }
180
181 type_init(m48t59_isa_register_types)