timer: Use a single definition of NSEC_PER_SEC for the whole codebase
[qemu.git] / hw / timer / mc146818rtc.c
1 /*
2 * QEMU MC146818 RTC emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "qemu/timer.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/timer/mc146818rtc.h"
28 #include "qapi/visitor.h"
29 #include "qapi-event.h"
30 #include "qmp-commands.h"
31
32 #ifdef TARGET_I386
33 #include "hw/i386/apic.h"
34 #endif
35
36 //#define DEBUG_CMOS
37 //#define DEBUG_COALESCED
38
39 #ifdef DEBUG_CMOS
40 # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
41 #else
42 # define CMOS_DPRINTF(format, ...) do { } while (0)
43 #endif
44
45 #ifdef DEBUG_COALESCED
46 # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__)
47 #else
48 # define DPRINTF_C(format, ...) do { } while (0)
49 #endif
50
51 #define SEC_PER_MIN 60
52 #define MIN_PER_HOUR 60
53 #define SEC_PER_HOUR 3600
54 #define HOUR_PER_DAY 24
55 #define SEC_PER_DAY 86400
56
57 #define RTC_REINJECT_ON_ACK_COUNT 20
58 #define RTC_CLOCK_RATE 32768
59 #define UIP_HOLD_LENGTH (8 * NSEC_PER_SEC / 32768)
60
61 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
62
63 typedef struct RTCState {
64 ISADevice parent_obj;
65
66 MemoryRegion io;
67 uint8_t cmos_data[128];
68 uint8_t cmos_index;
69 int32_t base_year;
70 uint64_t base_rtc;
71 uint64_t last_update;
72 int64_t offset;
73 qemu_irq irq;
74 int it_shift;
75 /* periodic timer */
76 QEMUTimer *periodic_timer;
77 int64_t next_periodic_time;
78 /* update-ended timer */
79 QEMUTimer *update_timer;
80 uint64_t next_alarm_time;
81 uint16_t irq_reinject_on_ack_count;
82 uint32_t irq_coalesced;
83 uint32_t period;
84 QEMUTimer *coalesced_timer;
85 Notifier clock_reset_notifier;
86 LostTickPolicy lost_tick_policy;
87 Notifier suspend_notifier;
88 QLIST_ENTRY(RTCState) link;
89 } RTCState;
90
91 static void rtc_set_time(RTCState *s);
92 static void rtc_update_time(RTCState *s);
93 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
94 static inline int rtc_from_bcd(RTCState *s, int a);
95 static uint64_t get_next_alarm(RTCState *s);
96
97 static inline bool rtc_running(RTCState *s)
98 {
99 return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
100 (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
101 }
102
103 static uint64_t get_guest_rtc_ns(RTCState *s)
104 {
105 uint64_t guest_rtc;
106 uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
107
108 guest_rtc = s->base_rtc * NSEC_PER_SEC
109 + guest_clock - s->last_update + s->offset;
110 return guest_rtc;
111 }
112
113 #ifdef TARGET_I386
114 static void rtc_coalesced_timer_update(RTCState *s)
115 {
116 if (s->irq_coalesced == 0) {
117 timer_del(s->coalesced_timer);
118 } else {
119 /* divide each RTC interval to 2 - 8 smaller intervals */
120 int c = MIN(s->irq_coalesced, 7) + 1;
121 int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
122 muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
123 timer_mod(s->coalesced_timer, next_clock);
124 }
125 }
126
127 static void rtc_coalesced_timer(void *opaque)
128 {
129 RTCState *s = opaque;
130
131 if (s->irq_coalesced != 0) {
132 apic_reset_irq_delivered();
133 s->cmos_data[RTC_REG_C] |= 0xc0;
134 DPRINTF_C("cmos: injecting from timer\n");
135 qemu_irq_raise(s->irq);
136 if (apic_get_irq_delivered()) {
137 s->irq_coalesced--;
138 DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
139 s->irq_coalesced);
140 }
141 }
142
143 rtc_coalesced_timer_update(s);
144 }
145 #endif
146
147 /* handle periodic timer */
148 static void periodic_timer_update(RTCState *s, int64_t current_time)
149 {
150 int period_code, period;
151 int64_t cur_clock, next_irq_clock;
152
153 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
154 if (period_code != 0
155 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
156 if (period_code <= 2)
157 period_code += 7;
158 /* period in 32 Khz cycles */
159 period = 1 << (period_code - 1);
160 #ifdef TARGET_I386
161 if (period != s->period) {
162 s->irq_coalesced = (s->irq_coalesced * s->period) / period;
163 DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
164 }
165 s->period = period;
166 #endif
167 /* compute 32 khz clock */
168 cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
169 next_irq_clock = (cur_clock & ~(period - 1)) + period;
170 s->next_periodic_time =
171 muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
172 timer_mod(s->periodic_timer, s->next_periodic_time);
173 } else {
174 #ifdef TARGET_I386
175 s->irq_coalesced = 0;
176 #endif
177 timer_del(s->periodic_timer);
178 }
179 }
180
181 static void rtc_periodic_timer(void *opaque)
182 {
183 RTCState *s = opaque;
184
185 periodic_timer_update(s, s->next_periodic_time);
186 s->cmos_data[RTC_REG_C] |= REG_C_PF;
187 if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
188 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
189 #ifdef TARGET_I386
190 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
191 if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
192 s->irq_reinject_on_ack_count = 0;
193 apic_reset_irq_delivered();
194 qemu_irq_raise(s->irq);
195 if (!apic_get_irq_delivered()) {
196 s->irq_coalesced++;
197 rtc_coalesced_timer_update(s);
198 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
199 s->irq_coalesced);
200 }
201 } else
202 #endif
203 qemu_irq_raise(s->irq);
204 }
205 }
206
207 /* handle update-ended timer */
208 static void check_update_timer(RTCState *s)
209 {
210 uint64_t next_update_time;
211 uint64_t guest_nsec;
212 int next_alarm_sec;
213
214 /* From the data sheet: "Holding the dividers in reset prevents
215 * interrupts from operating, while setting the SET bit allows"
216 * them to occur. However, it will prevent an alarm interrupt
217 * from occurring, because the time of day is not updated.
218 */
219 if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
220 timer_del(s->update_timer);
221 return;
222 }
223 if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
224 (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
225 timer_del(s->update_timer);
226 return;
227 }
228 if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
229 (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
230 timer_del(s->update_timer);
231 return;
232 }
233
234 guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
235 /* if UF is clear, reprogram to next second */
236 next_update_time = qemu_clock_get_ns(rtc_clock)
237 + NSEC_PER_SEC - guest_nsec;
238
239 /* Compute time of next alarm. One second is already accounted
240 * for in next_update_time.
241 */
242 next_alarm_sec = get_next_alarm(s);
243 s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
244
245 if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
246 /* UF is set, but AF is clear. Program the timer to target
247 * the alarm time. */
248 next_update_time = s->next_alarm_time;
249 }
250 if (next_update_time != timer_expire_time_ns(s->update_timer)) {
251 timer_mod(s->update_timer, next_update_time);
252 }
253 }
254
255 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
256 {
257 if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
258 hour %= 12;
259 if (s->cmos_data[RTC_HOURS] & 0x80) {
260 hour += 12;
261 }
262 }
263 return hour;
264 }
265
266 static uint64_t get_next_alarm(RTCState *s)
267 {
268 int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
269 int32_t hour, min, sec;
270
271 rtc_update_time(s);
272
273 alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
274 alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
275 alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
276 alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
277
278 cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
279 cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
280 cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
281 cur_hour = convert_hour(s, cur_hour);
282
283 if (alarm_hour == -1) {
284 alarm_hour = cur_hour;
285 if (alarm_min == -1) {
286 alarm_min = cur_min;
287 if (alarm_sec == -1) {
288 alarm_sec = cur_sec + 1;
289 } else if (cur_sec > alarm_sec) {
290 alarm_min++;
291 }
292 } else if (cur_min == alarm_min) {
293 if (alarm_sec == -1) {
294 alarm_sec = cur_sec + 1;
295 } else {
296 if (cur_sec > alarm_sec) {
297 alarm_hour++;
298 }
299 }
300 if (alarm_sec == SEC_PER_MIN) {
301 /* wrap to next hour, minutes is not in don't care mode */
302 alarm_sec = 0;
303 alarm_hour++;
304 }
305 } else if (cur_min > alarm_min) {
306 alarm_hour++;
307 }
308 } else if (cur_hour == alarm_hour) {
309 if (alarm_min == -1) {
310 alarm_min = cur_min;
311 if (alarm_sec == -1) {
312 alarm_sec = cur_sec + 1;
313 } else if (cur_sec > alarm_sec) {
314 alarm_min++;
315 }
316
317 if (alarm_sec == SEC_PER_MIN) {
318 alarm_sec = 0;
319 alarm_min++;
320 }
321 /* wrap to next day, hour is not in don't care mode */
322 alarm_min %= MIN_PER_HOUR;
323 } else if (cur_min == alarm_min) {
324 if (alarm_sec == -1) {
325 alarm_sec = cur_sec + 1;
326 }
327 /* wrap to next day, hours+minutes not in don't care mode */
328 alarm_sec %= SEC_PER_MIN;
329 }
330 }
331
332 /* values that are still don't care fire at the next min/sec */
333 if (alarm_min == -1) {
334 alarm_min = 0;
335 }
336 if (alarm_sec == -1) {
337 alarm_sec = 0;
338 }
339
340 /* keep values in range */
341 if (alarm_sec == SEC_PER_MIN) {
342 alarm_sec = 0;
343 alarm_min++;
344 }
345 if (alarm_min == MIN_PER_HOUR) {
346 alarm_min = 0;
347 alarm_hour++;
348 }
349 alarm_hour %= HOUR_PER_DAY;
350
351 hour = alarm_hour - cur_hour;
352 min = hour * MIN_PER_HOUR + alarm_min - cur_min;
353 sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
354 return sec <= 0 ? sec + SEC_PER_DAY : sec;
355 }
356
357 static void rtc_update_timer(void *opaque)
358 {
359 RTCState *s = opaque;
360 int32_t irqs = REG_C_UF;
361 int32_t new_irqs;
362
363 assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
364
365 /* UIP might have been latched, update time and clear it. */
366 rtc_update_time(s);
367 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
368
369 if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
370 irqs |= REG_C_AF;
371 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
372 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
373 }
374 }
375
376 new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
377 s->cmos_data[RTC_REG_C] |= irqs;
378 if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
379 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
380 qemu_irq_raise(s->irq);
381 }
382 check_update_timer(s);
383 }
384
385 static void cmos_ioport_write(void *opaque, hwaddr addr,
386 uint64_t data, unsigned size)
387 {
388 RTCState *s = opaque;
389
390 if ((addr & 1) == 0) {
391 s->cmos_index = data & 0x7f;
392 } else {
393 CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
394 s->cmos_index, data);
395 switch(s->cmos_index) {
396 case RTC_SECONDS_ALARM:
397 case RTC_MINUTES_ALARM:
398 case RTC_HOURS_ALARM:
399 s->cmos_data[s->cmos_index] = data;
400 check_update_timer(s);
401 break;
402 case RTC_IBM_PS2_CENTURY_BYTE:
403 s->cmos_index = RTC_CENTURY;
404 /* fall through */
405 case RTC_CENTURY:
406 case RTC_SECONDS:
407 case RTC_MINUTES:
408 case RTC_HOURS:
409 case RTC_DAY_OF_WEEK:
410 case RTC_DAY_OF_MONTH:
411 case RTC_MONTH:
412 case RTC_YEAR:
413 s->cmos_data[s->cmos_index] = data;
414 /* if in set mode, do not update the time */
415 if (rtc_running(s)) {
416 rtc_set_time(s);
417 check_update_timer(s);
418 }
419 break;
420 case RTC_REG_A:
421 if ((data & 0x60) == 0x60) {
422 if (rtc_running(s)) {
423 rtc_update_time(s);
424 }
425 /* What happens to UIP when divider reset is enabled is
426 * unclear from the datasheet. Shouldn't matter much
427 * though.
428 */
429 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
430 } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
431 (data & 0x70) <= 0x20) {
432 /* when the divider reset is removed, the first update cycle
433 * begins one-half second later*/
434 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
435 s->offset = 500000000;
436 rtc_set_time(s);
437 }
438 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
439 }
440 /* UIP bit is read only */
441 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
442 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
443 periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
444 check_update_timer(s);
445 break;
446 case RTC_REG_B:
447 if (data & REG_B_SET) {
448 /* update cmos to when the rtc was stopping */
449 if (rtc_running(s)) {
450 rtc_update_time(s);
451 }
452 /* set mode: reset UIP mode */
453 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
454 data &= ~REG_B_UIE;
455 } else {
456 /* if disabling set mode, update the time */
457 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
458 (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
459 s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC;
460 rtc_set_time(s);
461 }
462 }
463 /* if an interrupt flag is already set when the interrupt
464 * becomes enabled, raise an interrupt immediately. */
465 if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
466 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
467 qemu_irq_raise(s->irq);
468 } else {
469 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
470 qemu_irq_lower(s->irq);
471 }
472 s->cmos_data[RTC_REG_B] = data;
473 periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
474 check_update_timer(s);
475 break;
476 case RTC_REG_C:
477 case RTC_REG_D:
478 /* cannot write to them */
479 break;
480 default:
481 s->cmos_data[s->cmos_index] = data;
482 break;
483 }
484 }
485 }
486
487 static inline int rtc_to_bcd(RTCState *s, int a)
488 {
489 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
490 return a;
491 } else {
492 return ((a / 10) << 4) | (a % 10);
493 }
494 }
495
496 static inline int rtc_from_bcd(RTCState *s, int a)
497 {
498 if ((a & 0xc0) == 0xc0) {
499 return -1;
500 }
501 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
502 return a;
503 } else {
504 return ((a >> 4) * 10) + (a & 0x0f);
505 }
506 }
507
508 static void rtc_get_time(RTCState *s, struct tm *tm)
509 {
510 tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
511 tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
512 tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
513 if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
514 tm->tm_hour %= 12;
515 if (s->cmos_data[RTC_HOURS] & 0x80) {
516 tm->tm_hour += 12;
517 }
518 }
519 tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
520 tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
521 tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
522 tm->tm_year =
523 rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
524 rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
525 }
526
527 static QLIST_HEAD(, RTCState) rtc_devices =
528 QLIST_HEAD_INITIALIZER(rtc_devices);
529
530 #ifdef TARGET_I386
531 void qmp_rtc_reset_reinjection(Error **errp)
532 {
533 RTCState *s;
534
535 QLIST_FOREACH(s, &rtc_devices, link) {
536 s->irq_coalesced = 0;
537 }
538 }
539 #endif
540
541 static void rtc_set_time(RTCState *s)
542 {
543 struct tm tm;
544
545 rtc_get_time(s, &tm);
546 s->base_rtc = mktimegm(&tm);
547 s->last_update = qemu_clock_get_ns(rtc_clock);
548
549 qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort);
550 }
551
552 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
553 {
554 int year;
555
556 s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
557 s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
558 if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
559 /* 24 hour format */
560 s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
561 } else {
562 /* 12 hour format */
563 int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
564 s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
565 if (tm->tm_hour >= 12)
566 s->cmos_data[RTC_HOURS] |= 0x80;
567 }
568 s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
569 s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
570 s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
571 year = tm->tm_year + 1900 - s->base_year;
572 s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
573 s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
574 }
575
576 static void rtc_update_time(RTCState *s)
577 {
578 struct tm ret;
579 time_t guest_sec;
580 int64_t guest_nsec;
581
582 guest_nsec = get_guest_rtc_ns(s);
583 guest_sec = guest_nsec / NSEC_PER_SEC;
584 gmtime_r(&guest_sec, &ret);
585
586 /* Is SET flag of Register B disabled? */
587 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
588 rtc_set_cmos(s, &ret);
589 }
590 }
591
592 static int update_in_progress(RTCState *s)
593 {
594 int64_t guest_nsec;
595
596 if (!rtc_running(s)) {
597 return 0;
598 }
599 if (timer_pending(s->update_timer)) {
600 int64_t next_update_time = timer_expire_time_ns(s->update_timer);
601 /* Latch UIP until the timer expires. */
602 if (qemu_clock_get_ns(rtc_clock) >=
603 (next_update_time - UIP_HOLD_LENGTH)) {
604 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
605 return 1;
606 }
607 }
608
609 guest_nsec = get_guest_rtc_ns(s);
610 /* UIP bit will be set at last 244us of every second. */
611 if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
612 return 1;
613 }
614 return 0;
615 }
616
617 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
618 unsigned size)
619 {
620 RTCState *s = opaque;
621 int ret;
622 if ((addr & 1) == 0) {
623 return 0xff;
624 } else {
625 switch(s->cmos_index) {
626 case RTC_IBM_PS2_CENTURY_BYTE:
627 s->cmos_index = RTC_CENTURY;
628 /* fall through */
629 case RTC_CENTURY:
630 case RTC_SECONDS:
631 case RTC_MINUTES:
632 case RTC_HOURS:
633 case RTC_DAY_OF_WEEK:
634 case RTC_DAY_OF_MONTH:
635 case RTC_MONTH:
636 case RTC_YEAR:
637 /* if not in set mode, calibrate cmos before
638 * reading*/
639 if (rtc_running(s)) {
640 rtc_update_time(s);
641 }
642 ret = s->cmos_data[s->cmos_index];
643 break;
644 case RTC_REG_A:
645 if (update_in_progress(s)) {
646 s->cmos_data[s->cmos_index] |= REG_A_UIP;
647 } else {
648 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
649 }
650 ret = s->cmos_data[s->cmos_index];
651 break;
652 case RTC_REG_C:
653 ret = s->cmos_data[s->cmos_index];
654 qemu_irq_lower(s->irq);
655 s->cmos_data[RTC_REG_C] = 0x00;
656 if (ret & (REG_C_UF | REG_C_AF)) {
657 check_update_timer(s);
658 }
659 #ifdef TARGET_I386
660 if(s->irq_coalesced &&
661 (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
662 s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
663 s->irq_reinject_on_ack_count++;
664 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
665 apic_reset_irq_delivered();
666 DPRINTF_C("cmos: injecting on ack\n");
667 qemu_irq_raise(s->irq);
668 if (apic_get_irq_delivered()) {
669 s->irq_coalesced--;
670 DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
671 s->irq_coalesced);
672 }
673 }
674 #endif
675 break;
676 default:
677 ret = s->cmos_data[s->cmos_index];
678 break;
679 }
680 CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
681 s->cmos_index, ret);
682 return ret;
683 }
684 }
685
686 void rtc_set_memory(ISADevice *dev, int addr, int val)
687 {
688 RTCState *s = MC146818_RTC(dev);
689 if (addr >= 0 && addr <= 127)
690 s->cmos_data[addr] = val;
691 }
692
693 int rtc_get_memory(ISADevice *dev, int addr)
694 {
695 RTCState *s = MC146818_RTC(dev);
696 assert(addr >= 0 && addr <= 127);
697 return s->cmos_data[addr];
698 }
699
700 static void rtc_set_date_from_host(ISADevice *dev)
701 {
702 RTCState *s = MC146818_RTC(dev);
703 struct tm tm;
704
705 qemu_get_timedate(&tm, 0);
706
707 s->base_rtc = mktimegm(&tm);
708 s->last_update = qemu_clock_get_ns(rtc_clock);
709 s->offset = 0;
710
711 /* set the CMOS date */
712 rtc_set_cmos(s, &tm);
713 }
714
715 static int rtc_post_load(void *opaque, int version_id)
716 {
717 RTCState *s = opaque;
718
719 if (version_id <= 2) {
720 rtc_set_time(s);
721 s->offset = 0;
722 check_update_timer(s);
723 }
724
725 uint64_t now = qemu_clock_get_ns(rtc_clock);
726 if (now < s->next_periodic_time ||
727 now > (s->next_periodic_time + get_max_clock_jump())) {
728 periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
729 }
730
731 #ifdef TARGET_I386
732 if (version_id >= 2) {
733 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
734 rtc_coalesced_timer_update(s);
735 }
736 }
737 #endif
738 return 0;
739 }
740
741 static bool rtc_irq_reinject_on_ack_count_needed(void *opaque)
742 {
743 RTCState *s = (RTCState *)opaque;
744 return s->irq_reinject_on_ack_count != 0;
745 }
746
747 static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = {
748 .name = "mc146818rtc/irq_reinject_on_ack_count",
749 .version_id = 1,
750 .minimum_version_id = 1,
751 .needed = rtc_irq_reinject_on_ack_count_needed,
752 .fields = (VMStateField[]) {
753 VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState),
754 VMSTATE_END_OF_LIST()
755 }
756 };
757
758 static const VMStateDescription vmstate_rtc = {
759 .name = "mc146818rtc",
760 .version_id = 3,
761 .minimum_version_id = 1,
762 .post_load = rtc_post_load,
763 .fields = (VMStateField[]) {
764 VMSTATE_BUFFER(cmos_data, RTCState),
765 VMSTATE_UINT8(cmos_index, RTCState),
766 VMSTATE_UNUSED(7*4),
767 VMSTATE_TIMER_PTR(periodic_timer, RTCState),
768 VMSTATE_INT64(next_periodic_time, RTCState),
769 VMSTATE_UNUSED(3*8),
770 VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
771 VMSTATE_UINT32_V(period, RTCState, 2),
772 VMSTATE_UINT64_V(base_rtc, RTCState, 3),
773 VMSTATE_UINT64_V(last_update, RTCState, 3),
774 VMSTATE_INT64_V(offset, RTCState, 3),
775 VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3),
776 VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
777 VMSTATE_END_OF_LIST()
778 },
779 .subsections = (const VMStateDescription*[]) {
780 &vmstate_rtc_irq_reinject_on_ack_count,
781 NULL
782 }
783 };
784
785 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
786 {
787 RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
788 int64_t now = *(int64_t *)data;
789
790 rtc_set_date_from_host(ISA_DEVICE(s));
791 periodic_timer_update(s, now);
792 check_update_timer(s);
793 #ifdef TARGET_I386
794 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
795 rtc_coalesced_timer_update(s);
796 }
797 #endif
798 }
799
800 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
801 BIOS will read it and start S3 resume at POST Entry */
802 static void rtc_notify_suspend(Notifier *notifier, void *data)
803 {
804 RTCState *s = container_of(notifier, RTCState, suspend_notifier);
805 rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
806 }
807
808 static void rtc_reset(void *opaque)
809 {
810 RTCState *s = opaque;
811
812 s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
813 s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
814 check_update_timer(s);
815
816 qemu_irq_lower(s->irq);
817
818 #ifdef TARGET_I386
819 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
820 s->irq_coalesced = 0;
821 s->irq_reinject_on_ack_count = 0;
822 }
823 #endif
824 }
825
826 static const MemoryRegionOps cmos_ops = {
827 .read = cmos_ioport_read,
828 .write = cmos_ioport_write,
829 .impl = {
830 .min_access_size = 1,
831 .max_access_size = 1,
832 },
833 .endianness = DEVICE_LITTLE_ENDIAN,
834 };
835
836 static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
837 {
838 RTCState *s = MC146818_RTC(obj);
839
840 rtc_update_time(s);
841 rtc_get_time(s, current_tm);
842 }
843
844 static void rtc_realizefn(DeviceState *dev, Error **errp)
845 {
846 ISADevice *isadev = ISA_DEVICE(dev);
847 RTCState *s = MC146818_RTC(dev);
848 int base = 0x70;
849
850 s->cmos_data[RTC_REG_A] = 0x26;
851 s->cmos_data[RTC_REG_B] = 0x02;
852 s->cmos_data[RTC_REG_C] = 0x00;
853 s->cmos_data[RTC_REG_D] = 0x80;
854
855 /* This is for historical reasons. The default base year qdev property
856 * was set to 2000 for most machine types before the century byte was
857 * implemented.
858 *
859 * This if statement means that the century byte will be always 0
860 * (at least until 2079...) for base_year = 1980, but will be set
861 * correctly for base_year = 2000.
862 */
863 if (s->base_year == 2000) {
864 s->base_year = 0;
865 }
866
867 rtc_set_date_from_host(isadev);
868
869 #ifdef TARGET_I386
870 switch (s->lost_tick_policy) {
871 case LOST_TICK_POLICY_SLEW:
872 s->coalesced_timer =
873 timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
874 break;
875 case LOST_TICK_POLICY_DISCARD:
876 break;
877 default:
878 error_setg(errp, "Invalid lost tick policy.");
879 return;
880 }
881 #endif
882
883 s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
884 s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
885 check_update_timer(s);
886
887 s->clock_reset_notifier.notify = rtc_notify_clock_reset;
888 qemu_clock_register_reset_notifier(rtc_clock,
889 &s->clock_reset_notifier);
890
891 s->suspend_notifier.notify = rtc_notify_suspend;
892 qemu_register_suspend_notifier(&s->suspend_notifier);
893
894 memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
895 isa_register_ioport(isadev, &s->io, base);
896
897 qdev_set_legacy_instance_id(dev, base, 3);
898 qemu_register_reset(rtc_reset, s);
899
900 object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
901
902 object_property_add_alias(qdev_get_machine(), "rtc-time",
903 OBJECT(s), "date", NULL);
904 }
905
906 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
907 {
908 DeviceState *dev;
909 ISADevice *isadev;
910 RTCState *s;
911
912 isadev = isa_create(bus, TYPE_MC146818_RTC);
913 dev = DEVICE(isadev);
914 s = MC146818_RTC(isadev);
915 qdev_prop_set_int32(dev, "base_year", base_year);
916 qdev_init_nofail(dev);
917 if (intercept_irq) {
918 s->irq = intercept_irq;
919 } else {
920 isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
921 }
922 QLIST_INSERT_HEAD(&rtc_devices, s, link);
923
924 return isadev;
925 }
926
927 static Property mc146818rtc_properties[] = {
928 DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
929 DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
930 lost_tick_policy, LOST_TICK_POLICY_DISCARD),
931 DEFINE_PROP_END_OF_LIST(),
932 };
933
934 static void rtc_class_initfn(ObjectClass *klass, void *data)
935 {
936 DeviceClass *dc = DEVICE_CLASS(klass);
937
938 dc->realize = rtc_realizefn;
939 dc->vmsd = &vmstate_rtc;
940 dc->props = mc146818rtc_properties;
941 /* Reason: needs to be wired up by rtc_init() */
942 dc->cannot_instantiate_with_device_add_yet = true;
943 }
944
945 static void rtc_finalize(Object *obj)
946 {
947 object_property_del(qdev_get_machine(), "rtc", NULL);
948 }
949
950 static const TypeInfo mc146818rtc_info = {
951 .name = TYPE_MC146818_RTC,
952 .parent = TYPE_ISA_DEVICE,
953 .instance_size = sizeof(RTCState),
954 .class_init = rtc_class_initfn,
955 .instance_finalize = rtc_finalize,
956 };
957
958 static void mc146818rtc_register_types(void)
959 {
960 type_register_static(&mc146818rtc_info);
961 }
962
963 type_init(mc146818rtc_register_types)