timer: rename NSEC_PER_SEC due to Mac OS X header clash
[qemu.git] / hw / timer / mc146818rtc.c
1 /*
2 * QEMU MC146818 RTC emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "qemu/timer.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/timer/mc146818rtc.h"
28 #include "qapi/visitor.h"
29 #include "qapi-event.h"
30 #include "qmp-commands.h"
31
32 #ifdef TARGET_I386
33 #include "hw/i386/apic.h"
34 #endif
35
36 //#define DEBUG_CMOS
37 //#define DEBUG_COALESCED
38
39 #ifdef DEBUG_CMOS
40 # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
41 #else
42 # define CMOS_DPRINTF(format, ...) do { } while (0)
43 #endif
44
45 #ifdef DEBUG_COALESCED
46 # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__)
47 #else
48 # define DPRINTF_C(format, ...) do { } while (0)
49 #endif
50
51 #define SEC_PER_MIN 60
52 #define MIN_PER_HOUR 60
53 #define SEC_PER_HOUR 3600
54 #define HOUR_PER_DAY 24
55 #define SEC_PER_DAY 86400
56
57 #define RTC_REINJECT_ON_ACK_COUNT 20
58 #define RTC_CLOCK_RATE 32768
59 #define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768)
60
61 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
62
63 typedef struct RTCState {
64 ISADevice parent_obj;
65
66 MemoryRegion io;
67 uint8_t cmos_data[128];
68 uint8_t cmos_index;
69 int32_t base_year;
70 uint64_t base_rtc;
71 uint64_t last_update;
72 int64_t offset;
73 qemu_irq irq;
74 int it_shift;
75 /* periodic timer */
76 QEMUTimer *periodic_timer;
77 int64_t next_periodic_time;
78 /* update-ended timer */
79 QEMUTimer *update_timer;
80 uint64_t next_alarm_time;
81 uint16_t irq_reinject_on_ack_count;
82 uint32_t irq_coalesced;
83 uint32_t period;
84 QEMUTimer *coalesced_timer;
85 Notifier clock_reset_notifier;
86 LostTickPolicy lost_tick_policy;
87 Notifier suspend_notifier;
88 QLIST_ENTRY(RTCState) link;
89 } RTCState;
90
91 static void rtc_set_time(RTCState *s);
92 static void rtc_update_time(RTCState *s);
93 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
94 static inline int rtc_from_bcd(RTCState *s, int a);
95 static uint64_t get_next_alarm(RTCState *s);
96
97 static inline bool rtc_running(RTCState *s)
98 {
99 return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
100 (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
101 }
102
103 static uint64_t get_guest_rtc_ns(RTCState *s)
104 {
105 uint64_t guest_rtc;
106 uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
107
108 guest_rtc = s->base_rtc * NANOSECONDS_PER_SECOND
109 + guest_clock - s->last_update + s->offset;
110 return guest_rtc;
111 }
112
113 #ifdef TARGET_I386
114 static void rtc_coalesced_timer_update(RTCState *s)
115 {
116 if (s->irq_coalesced == 0) {
117 timer_del(s->coalesced_timer);
118 } else {
119 /* divide each RTC interval to 2 - 8 smaller intervals */
120 int c = MIN(s->irq_coalesced, 7) + 1;
121 int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
122 muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
123 timer_mod(s->coalesced_timer, next_clock);
124 }
125 }
126
127 static void rtc_coalesced_timer(void *opaque)
128 {
129 RTCState *s = opaque;
130
131 if (s->irq_coalesced != 0) {
132 apic_reset_irq_delivered();
133 s->cmos_data[RTC_REG_C] |= 0xc0;
134 DPRINTF_C("cmos: injecting from timer\n");
135 qemu_irq_raise(s->irq);
136 if (apic_get_irq_delivered()) {
137 s->irq_coalesced--;
138 DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
139 s->irq_coalesced);
140 }
141 }
142
143 rtc_coalesced_timer_update(s);
144 }
145 #endif
146
147 /* handle periodic timer */
148 static void periodic_timer_update(RTCState *s, int64_t current_time)
149 {
150 int period_code, period;
151 int64_t cur_clock, next_irq_clock;
152
153 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
154 if (period_code != 0
155 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
156 if (period_code <= 2)
157 period_code += 7;
158 /* period in 32 Khz cycles */
159 period = 1 << (period_code - 1);
160 #ifdef TARGET_I386
161 if (period != s->period) {
162 s->irq_coalesced = (s->irq_coalesced * s->period) / period;
163 DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
164 }
165 s->period = period;
166 #endif
167 /* compute 32 khz clock */
168 cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
169 next_irq_clock = (cur_clock & ~(period - 1)) + period;
170 s->next_periodic_time =
171 muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
172 timer_mod(s->periodic_timer, s->next_periodic_time);
173 } else {
174 #ifdef TARGET_I386
175 s->irq_coalesced = 0;
176 #endif
177 timer_del(s->periodic_timer);
178 }
179 }
180
181 static void rtc_periodic_timer(void *opaque)
182 {
183 RTCState *s = opaque;
184
185 periodic_timer_update(s, s->next_periodic_time);
186 s->cmos_data[RTC_REG_C] |= REG_C_PF;
187 if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
188 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
189 #ifdef TARGET_I386
190 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
191 if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
192 s->irq_reinject_on_ack_count = 0;
193 apic_reset_irq_delivered();
194 qemu_irq_raise(s->irq);
195 if (!apic_get_irq_delivered()) {
196 s->irq_coalesced++;
197 rtc_coalesced_timer_update(s);
198 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
199 s->irq_coalesced);
200 }
201 } else
202 #endif
203 qemu_irq_raise(s->irq);
204 }
205 }
206
207 /* handle update-ended timer */
208 static void check_update_timer(RTCState *s)
209 {
210 uint64_t next_update_time;
211 uint64_t guest_nsec;
212 int next_alarm_sec;
213
214 /* From the data sheet: "Holding the dividers in reset prevents
215 * interrupts from operating, while setting the SET bit allows"
216 * them to occur. However, it will prevent an alarm interrupt
217 * from occurring, because the time of day is not updated.
218 */
219 if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
220 timer_del(s->update_timer);
221 return;
222 }
223 if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
224 (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
225 timer_del(s->update_timer);
226 return;
227 }
228 if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
229 (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
230 timer_del(s->update_timer);
231 return;
232 }
233
234 guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
235 /* if UF is clear, reprogram to next second */
236 next_update_time = qemu_clock_get_ns(rtc_clock)
237 + NANOSECONDS_PER_SECOND - guest_nsec;
238
239 /* Compute time of next alarm. One second is already accounted
240 * for in next_update_time.
241 */
242 next_alarm_sec = get_next_alarm(s);
243 s->next_alarm_time = next_update_time +
244 (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND;
245
246 if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
247 /* UF is set, but AF is clear. Program the timer to target
248 * the alarm time. */
249 next_update_time = s->next_alarm_time;
250 }
251 if (next_update_time != timer_expire_time_ns(s->update_timer)) {
252 timer_mod(s->update_timer, next_update_time);
253 }
254 }
255
256 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
257 {
258 if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
259 hour %= 12;
260 if (s->cmos_data[RTC_HOURS] & 0x80) {
261 hour += 12;
262 }
263 }
264 return hour;
265 }
266
267 static uint64_t get_next_alarm(RTCState *s)
268 {
269 int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
270 int32_t hour, min, sec;
271
272 rtc_update_time(s);
273
274 alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
275 alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
276 alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
277 alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
278
279 cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
280 cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
281 cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
282 cur_hour = convert_hour(s, cur_hour);
283
284 if (alarm_hour == -1) {
285 alarm_hour = cur_hour;
286 if (alarm_min == -1) {
287 alarm_min = cur_min;
288 if (alarm_sec == -1) {
289 alarm_sec = cur_sec + 1;
290 } else if (cur_sec > alarm_sec) {
291 alarm_min++;
292 }
293 } else if (cur_min == alarm_min) {
294 if (alarm_sec == -1) {
295 alarm_sec = cur_sec + 1;
296 } else {
297 if (cur_sec > alarm_sec) {
298 alarm_hour++;
299 }
300 }
301 if (alarm_sec == SEC_PER_MIN) {
302 /* wrap to next hour, minutes is not in don't care mode */
303 alarm_sec = 0;
304 alarm_hour++;
305 }
306 } else if (cur_min > alarm_min) {
307 alarm_hour++;
308 }
309 } else if (cur_hour == alarm_hour) {
310 if (alarm_min == -1) {
311 alarm_min = cur_min;
312 if (alarm_sec == -1) {
313 alarm_sec = cur_sec + 1;
314 } else if (cur_sec > alarm_sec) {
315 alarm_min++;
316 }
317
318 if (alarm_sec == SEC_PER_MIN) {
319 alarm_sec = 0;
320 alarm_min++;
321 }
322 /* wrap to next day, hour is not in don't care mode */
323 alarm_min %= MIN_PER_HOUR;
324 } else if (cur_min == alarm_min) {
325 if (alarm_sec == -1) {
326 alarm_sec = cur_sec + 1;
327 }
328 /* wrap to next day, hours+minutes not in don't care mode */
329 alarm_sec %= SEC_PER_MIN;
330 }
331 }
332
333 /* values that are still don't care fire at the next min/sec */
334 if (alarm_min == -1) {
335 alarm_min = 0;
336 }
337 if (alarm_sec == -1) {
338 alarm_sec = 0;
339 }
340
341 /* keep values in range */
342 if (alarm_sec == SEC_PER_MIN) {
343 alarm_sec = 0;
344 alarm_min++;
345 }
346 if (alarm_min == MIN_PER_HOUR) {
347 alarm_min = 0;
348 alarm_hour++;
349 }
350 alarm_hour %= HOUR_PER_DAY;
351
352 hour = alarm_hour - cur_hour;
353 min = hour * MIN_PER_HOUR + alarm_min - cur_min;
354 sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
355 return sec <= 0 ? sec + SEC_PER_DAY : sec;
356 }
357
358 static void rtc_update_timer(void *opaque)
359 {
360 RTCState *s = opaque;
361 int32_t irqs = REG_C_UF;
362 int32_t new_irqs;
363
364 assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
365
366 /* UIP might have been latched, update time and clear it. */
367 rtc_update_time(s);
368 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
369
370 if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
371 irqs |= REG_C_AF;
372 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
373 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
374 }
375 }
376
377 new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
378 s->cmos_data[RTC_REG_C] |= irqs;
379 if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
380 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
381 qemu_irq_raise(s->irq);
382 }
383 check_update_timer(s);
384 }
385
386 static void cmos_ioport_write(void *opaque, hwaddr addr,
387 uint64_t data, unsigned size)
388 {
389 RTCState *s = opaque;
390
391 if ((addr & 1) == 0) {
392 s->cmos_index = data & 0x7f;
393 } else {
394 CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
395 s->cmos_index, data);
396 switch(s->cmos_index) {
397 case RTC_SECONDS_ALARM:
398 case RTC_MINUTES_ALARM:
399 case RTC_HOURS_ALARM:
400 s->cmos_data[s->cmos_index] = data;
401 check_update_timer(s);
402 break;
403 case RTC_IBM_PS2_CENTURY_BYTE:
404 s->cmos_index = RTC_CENTURY;
405 /* fall through */
406 case RTC_CENTURY:
407 case RTC_SECONDS:
408 case RTC_MINUTES:
409 case RTC_HOURS:
410 case RTC_DAY_OF_WEEK:
411 case RTC_DAY_OF_MONTH:
412 case RTC_MONTH:
413 case RTC_YEAR:
414 s->cmos_data[s->cmos_index] = data;
415 /* if in set mode, do not update the time */
416 if (rtc_running(s)) {
417 rtc_set_time(s);
418 check_update_timer(s);
419 }
420 break;
421 case RTC_REG_A:
422 if ((data & 0x60) == 0x60) {
423 if (rtc_running(s)) {
424 rtc_update_time(s);
425 }
426 /* What happens to UIP when divider reset is enabled is
427 * unclear from the datasheet. Shouldn't matter much
428 * though.
429 */
430 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
431 } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
432 (data & 0x70) <= 0x20) {
433 /* when the divider reset is removed, the first update cycle
434 * begins one-half second later*/
435 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
436 s->offset = 500000000;
437 rtc_set_time(s);
438 }
439 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
440 }
441 /* UIP bit is read only */
442 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
443 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
444 periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
445 check_update_timer(s);
446 break;
447 case RTC_REG_B:
448 if (data & REG_B_SET) {
449 /* update cmos to when the rtc was stopping */
450 if (rtc_running(s)) {
451 rtc_update_time(s);
452 }
453 /* set mode: reset UIP mode */
454 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
455 data &= ~REG_B_UIE;
456 } else {
457 /* if disabling set mode, update the time */
458 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
459 (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
460 s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
461 rtc_set_time(s);
462 }
463 }
464 /* if an interrupt flag is already set when the interrupt
465 * becomes enabled, raise an interrupt immediately. */
466 if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
467 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
468 qemu_irq_raise(s->irq);
469 } else {
470 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
471 qemu_irq_lower(s->irq);
472 }
473 s->cmos_data[RTC_REG_B] = data;
474 periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
475 check_update_timer(s);
476 break;
477 case RTC_REG_C:
478 case RTC_REG_D:
479 /* cannot write to them */
480 break;
481 default:
482 s->cmos_data[s->cmos_index] = data;
483 break;
484 }
485 }
486 }
487
488 static inline int rtc_to_bcd(RTCState *s, int a)
489 {
490 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
491 return a;
492 } else {
493 return ((a / 10) << 4) | (a % 10);
494 }
495 }
496
497 static inline int rtc_from_bcd(RTCState *s, int a)
498 {
499 if ((a & 0xc0) == 0xc0) {
500 return -1;
501 }
502 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
503 return a;
504 } else {
505 return ((a >> 4) * 10) + (a & 0x0f);
506 }
507 }
508
509 static void rtc_get_time(RTCState *s, struct tm *tm)
510 {
511 tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
512 tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
513 tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
514 if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
515 tm->tm_hour %= 12;
516 if (s->cmos_data[RTC_HOURS] & 0x80) {
517 tm->tm_hour += 12;
518 }
519 }
520 tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
521 tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
522 tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
523 tm->tm_year =
524 rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
525 rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
526 }
527
528 static QLIST_HEAD(, RTCState) rtc_devices =
529 QLIST_HEAD_INITIALIZER(rtc_devices);
530
531 #ifdef TARGET_I386
532 void qmp_rtc_reset_reinjection(Error **errp)
533 {
534 RTCState *s;
535
536 QLIST_FOREACH(s, &rtc_devices, link) {
537 s->irq_coalesced = 0;
538 }
539 }
540 #endif
541
542 static void rtc_set_time(RTCState *s)
543 {
544 struct tm tm;
545
546 rtc_get_time(s, &tm);
547 s->base_rtc = mktimegm(&tm);
548 s->last_update = qemu_clock_get_ns(rtc_clock);
549
550 qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort);
551 }
552
553 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
554 {
555 int year;
556
557 s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
558 s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
559 if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
560 /* 24 hour format */
561 s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
562 } else {
563 /* 12 hour format */
564 int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
565 s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
566 if (tm->tm_hour >= 12)
567 s->cmos_data[RTC_HOURS] |= 0x80;
568 }
569 s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
570 s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
571 s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
572 year = tm->tm_year + 1900 - s->base_year;
573 s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
574 s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
575 }
576
577 static void rtc_update_time(RTCState *s)
578 {
579 struct tm ret;
580 time_t guest_sec;
581 int64_t guest_nsec;
582
583 guest_nsec = get_guest_rtc_ns(s);
584 guest_sec = guest_nsec / NANOSECONDS_PER_SECOND;
585 gmtime_r(&guest_sec, &ret);
586
587 /* Is SET flag of Register B disabled? */
588 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
589 rtc_set_cmos(s, &ret);
590 }
591 }
592
593 static int update_in_progress(RTCState *s)
594 {
595 int64_t guest_nsec;
596
597 if (!rtc_running(s)) {
598 return 0;
599 }
600 if (timer_pending(s->update_timer)) {
601 int64_t next_update_time = timer_expire_time_ns(s->update_timer);
602 /* Latch UIP until the timer expires. */
603 if (qemu_clock_get_ns(rtc_clock) >=
604 (next_update_time - UIP_HOLD_LENGTH)) {
605 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
606 return 1;
607 }
608 }
609
610 guest_nsec = get_guest_rtc_ns(s);
611 /* UIP bit will be set at last 244us of every second. */
612 if ((guest_nsec % NANOSECONDS_PER_SECOND) >=
613 (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) {
614 return 1;
615 }
616 return 0;
617 }
618
619 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
620 unsigned size)
621 {
622 RTCState *s = opaque;
623 int ret;
624 if ((addr & 1) == 0) {
625 return 0xff;
626 } else {
627 switch(s->cmos_index) {
628 case RTC_IBM_PS2_CENTURY_BYTE:
629 s->cmos_index = RTC_CENTURY;
630 /* fall through */
631 case RTC_CENTURY:
632 case RTC_SECONDS:
633 case RTC_MINUTES:
634 case RTC_HOURS:
635 case RTC_DAY_OF_WEEK:
636 case RTC_DAY_OF_MONTH:
637 case RTC_MONTH:
638 case RTC_YEAR:
639 /* if not in set mode, calibrate cmos before
640 * reading*/
641 if (rtc_running(s)) {
642 rtc_update_time(s);
643 }
644 ret = s->cmos_data[s->cmos_index];
645 break;
646 case RTC_REG_A:
647 if (update_in_progress(s)) {
648 s->cmos_data[s->cmos_index] |= REG_A_UIP;
649 } else {
650 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
651 }
652 ret = s->cmos_data[s->cmos_index];
653 break;
654 case RTC_REG_C:
655 ret = s->cmos_data[s->cmos_index];
656 qemu_irq_lower(s->irq);
657 s->cmos_data[RTC_REG_C] = 0x00;
658 if (ret & (REG_C_UF | REG_C_AF)) {
659 check_update_timer(s);
660 }
661 #ifdef TARGET_I386
662 if(s->irq_coalesced &&
663 (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
664 s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
665 s->irq_reinject_on_ack_count++;
666 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
667 apic_reset_irq_delivered();
668 DPRINTF_C("cmos: injecting on ack\n");
669 qemu_irq_raise(s->irq);
670 if (apic_get_irq_delivered()) {
671 s->irq_coalesced--;
672 DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
673 s->irq_coalesced);
674 }
675 }
676 #endif
677 break;
678 default:
679 ret = s->cmos_data[s->cmos_index];
680 break;
681 }
682 CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
683 s->cmos_index, ret);
684 return ret;
685 }
686 }
687
688 void rtc_set_memory(ISADevice *dev, int addr, int val)
689 {
690 RTCState *s = MC146818_RTC(dev);
691 if (addr >= 0 && addr <= 127)
692 s->cmos_data[addr] = val;
693 }
694
695 int rtc_get_memory(ISADevice *dev, int addr)
696 {
697 RTCState *s = MC146818_RTC(dev);
698 assert(addr >= 0 && addr <= 127);
699 return s->cmos_data[addr];
700 }
701
702 static void rtc_set_date_from_host(ISADevice *dev)
703 {
704 RTCState *s = MC146818_RTC(dev);
705 struct tm tm;
706
707 qemu_get_timedate(&tm, 0);
708
709 s->base_rtc = mktimegm(&tm);
710 s->last_update = qemu_clock_get_ns(rtc_clock);
711 s->offset = 0;
712
713 /* set the CMOS date */
714 rtc_set_cmos(s, &tm);
715 }
716
717 static int rtc_post_load(void *opaque, int version_id)
718 {
719 RTCState *s = opaque;
720
721 if (version_id <= 2) {
722 rtc_set_time(s);
723 s->offset = 0;
724 check_update_timer(s);
725 }
726
727 uint64_t now = qemu_clock_get_ns(rtc_clock);
728 if (now < s->next_periodic_time ||
729 now > (s->next_periodic_time + get_max_clock_jump())) {
730 periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
731 }
732
733 #ifdef TARGET_I386
734 if (version_id >= 2) {
735 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
736 rtc_coalesced_timer_update(s);
737 }
738 }
739 #endif
740 return 0;
741 }
742
743 static bool rtc_irq_reinject_on_ack_count_needed(void *opaque)
744 {
745 RTCState *s = (RTCState *)opaque;
746 return s->irq_reinject_on_ack_count != 0;
747 }
748
749 static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = {
750 .name = "mc146818rtc/irq_reinject_on_ack_count",
751 .version_id = 1,
752 .minimum_version_id = 1,
753 .needed = rtc_irq_reinject_on_ack_count_needed,
754 .fields = (VMStateField[]) {
755 VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState),
756 VMSTATE_END_OF_LIST()
757 }
758 };
759
760 static const VMStateDescription vmstate_rtc = {
761 .name = "mc146818rtc",
762 .version_id = 3,
763 .minimum_version_id = 1,
764 .post_load = rtc_post_load,
765 .fields = (VMStateField[]) {
766 VMSTATE_BUFFER(cmos_data, RTCState),
767 VMSTATE_UINT8(cmos_index, RTCState),
768 VMSTATE_UNUSED(7*4),
769 VMSTATE_TIMER_PTR(periodic_timer, RTCState),
770 VMSTATE_INT64(next_periodic_time, RTCState),
771 VMSTATE_UNUSED(3*8),
772 VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
773 VMSTATE_UINT32_V(period, RTCState, 2),
774 VMSTATE_UINT64_V(base_rtc, RTCState, 3),
775 VMSTATE_UINT64_V(last_update, RTCState, 3),
776 VMSTATE_INT64_V(offset, RTCState, 3),
777 VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3),
778 VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
779 VMSTATE_END_OF_LIST()
780 },
781 .subsections = (const VMStateDescription*[]) {
782 &vmstate_rtc_irq_reinject_on_ack_count,
783 NULL
784 }
785 };
786
787 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
788 {
789 RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
790 int64_t now = *(int64_t *)data;
791
792 rtc_set_date_from_host(ISA_DEVICE(s));
793 periodic_timer_update(s, now);
794 check_update_timer(s);
795 #ifdef TARGET_I386
796 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
797 rtc_coalesced_timer_update(s);
798 }
799 #endif
800 }
801
802 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
803 BIOS will read it and start S3 resume at POST Entry */
804 static void rtc_notify_suspend(Notifier *notifier, void *data)
805 {
806 RTCState *s = container_of(notifier, RTCState, suspend_notifier);
807 rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
808 }
809
810 static void rtc_reset(void *opaque)
811 {
812 RTCState *s = opaque;
813
814 s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
815 s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
816 check_update_timer(s);
817
818 qemu_irq_lower(s->irq);
819
820 #ifdef TARGET_I386
821 if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
822 s->irq_coalesced = 0;
823 s->irq_reinject_on_ack_count = 0;
824 }
825 #endif
826 }
827
828 static const MemoryRegionOps cmos_ops = {
829 .read = cmos_ioport_read,
830 .write = cmos_ioport_write,
831 .impl = {
832 .min_access_size = 1,
833 .max_access_size = 1,
834 },
835 .endianness = DEVICE_LITTLE_ENDIAN,
836 };
837
838 static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
839 {
840 RTCState *s = MC146818_RTC(obj);
841
842 rtc_update_time(s);
843 rtc_get_time(s, current_tm);
844 }
845
846 static void rtc_realizefn(DeviceState *dev, Error **errp)
847 {
848 ISADevice *isadev = ISA_DEVICE(dev);
849 RTCState *s = MC146818_RTC(dev);
850 int base = 0x70;
851
852 s->cmos_data[RTC_REG_A] = 0x26;
853 s->cmos_data[RTC_REG_B] = 0x02;
854 s->cmos_data[RTC_REG_C] = 0x00;
855 s->cmos_data[RTC_REG_D] = 0x80;
856
857 /* This is for historical reasons. The default base year qdev property
858 * was set to 2000 for most machine types before the century byte was
859 * implemented.
860 *
861 * This if statement means that the century byte will be always 0
862 * (at least until 2079...) for base_year = 1980, but will be set
863 * correctly for base_year = 2000.
864 */
865 if (s->base_year == 2000) {
866 s->base_year = 0;
867 }
868
869 rtc_set_date_from_host(isadev);
870
871 #ifdef TARGET_I386
872 switch (s->lost_tick_policy) {
873 case LOST_TICK_POLICY_SLEW:
874 s->coalesced_timer =
875 timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
876 break;
877 case LOST_TICK_POLICY_DISCARD:
878 break;
879 default:
880 error_setg(errp, "Invalid lost tick policy.");
881 return;
882 }
883 #endif
884
885 s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
886 s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
887 check_update_timer(s);
888
889 s->clock_reset_notifier.notify = rtc_notify_clock_reset;
890 qemu_clock_register_reset_notifier(rtc_clock,
891 &s->clock_reset_notifier);
892
893 s->suspend_notifier.notify = rtc_notify_suspend;
894 qemu_register_suspend_notifier(&s->suspend_notifier);
895
896 memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
897 isa_register_ioport(isadev, &s->io, base);
898
899 qdev_set_legacy_instance_id(dev, base, 3);
900 qemu_register_reset(rtc_reset, s);
901
902 object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
903
904 object_property_add_alias(qdev_get_machine(), "rtc-time",
905 OBJECT(s), "date", NULL);
906 }
907
908 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
909 {
910 DeviceState *dev;
911 ISADevice *isadev;
912 RTCState *s;
913
914 isadev = isa_create(bus, TYPE_MC146818_RTC);
915 dev = DEVICE(isadev);
916 s = MC146818_RTC(isadev);
917 qdev_prop_set_int32(dev, "base_year", base_year);
918 qdev_init_nofail(dev);
919 if (intercept_irq) {
920 s->irq = intercept_irq;
921 } else {
922 isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
923 }
924 QLIST_INSERT_HEAD(&rtc_devices, s, link);
925
926 return isadev;
927 }
928
929 static Property mc146818rtc_properties[] = {
930 DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
931 DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
932 lost_tick_policy, LOST_TICK_POLICY_DISCARD),
933 DEFINE_PROP_END_OF_LIST(),
934 };
935
936 static void rtc_class_initfn(ObjectClass *klass, void *data)
937 {
938 DeviceClass *dc = DEVICE_CLASS(klass);
939
940 dc->realize = rtc_realizefn;
941 dc->vmsd = &vmstate_rtc;
942 dc->props = mc146818rtc_properties;
943 /* Reason: needs to be wired up by rtc_init() */
944 dc->cannot_instantiate_with_device_add_yet = true;
945 }
946
947 static void rtc_finalize(Object *obj)
948 {
949 object_property_del(qdev_get_machine(), "rtc", NULL);
950 }
951
952 static const TypeInfo mc146818rtc_info = {
953 .name = TYPE_MC146818_RTC,
954 .parent = TYPE_ISA_DEVICE,
955 .instance_size = sizeof(RTCState),
956 .class_init = rtc_class_initfn,
957 .instance_finalize = rtc_finalize,
958 };
959
960 static void mc146818rtc_register_types(void)
961 {
962 type_register_static(&mc146818rtc_info);
963 }
964
965 type_init(mc146818rtc_register_types)