hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / timer / milkymist-sysctl.c
1 /*
2 * QEMU model of the Milkymist System Controller.
3 *
4 * Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Specification available at:
21 * http://milkymist.walle.cc/socdoc/sysctl.pdf
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/irq.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
28 #include "trace.h"
29 #include "qemu/timer.h"
30 #include "sysemu/runstate.h"
31 #include "hw/ptimer.h"
32 #include "hw/qdev-properties.h"
33 #include "qemu/error-report.h"
34 #include "qemu/module.h"
35 #include "qom/object.h"
36
37 enum {
38 CTRL_ENABLE = (1<<0),
39 CTRL_AUTORESTART = (1<<1),
40 };
41
42 enum {
43 ICAP_READY = (1<<0),
44 };
45
46 enum {
47 R_GPIO_IN = 0,
48 R_GPIO_OUT,
49 R_GPIO_INTEN,
50 R_TIMER0_CONTROL = 4,
51 R_TIMER0_COMPARE,
52 R_TIMER0_COUNTER,
53 R_TIMER1_CONTROL = 8,
54 R_TIMER1_COMPARE,
55 R_TIMER1_COUNTER,
56 R_ICAP = 16,
57 R_DBG_SCRATCHPAD = 20,
58 R_DBG_WRITE_LOCK,
59 R_CLK_FREQUENCY = 29,
60 R_CAPABILITIES,
61 R_SYSTEM_ID,
62 R_MAX
63 };
64
65 #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
66 OBJECT_DECLARE_SIMPLE_TYPE(MilkymistSysctlState, MILKYMIST_SYSCTL)
67
68 struct MilkymistSysctlState {
69 SysBusDevice parent_obj;
70
71 MemoryRegion regs_region;
72
73 ptimer_state *ptimer0;
74 ptimer_state *ptimer1;
75
76 uint32_t freq_hz;
77 uint32_t capabilities;
78 uint32_t systemid;
79 uint32_t strappings;
80
81 uint32_t regs[R_MAX];
82
83 qemu_irq gpio_irq;
84 qemu_irq timer0_irq;
85 qemu_irq timer1_irq;
86 };
87
88 static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
89 {
90 trace_milkymist_sysctl_icap_write(value);
91 switch (value & 0xffff) {
92 case 0x000e:
93 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
94 break;
95 }
96 }
97
98 static uint64_t sysctl_read(void *opaque, hwaddr addr,
99 unsigned size)
100 {
101 MilkymistSysctlState *s = opaque;
102 uint32_t r = 0;
103
104 addr >>= 2;
105 switch (addr) {
106 case R_TIMER0_COUNTER:
107 r = (uint32_t)ptimer_get_count(s->ptimer0);
108 /* milkymist timer counts up */
109 r = s->regs[R_TIMER0_COMPARE] - r;
110 break;
111 case R_TIMER1_COUNTER:
112 r = (uint32_t)ptimer_get_count(s->ptimer1);
113 /* milkymist timer counts up */
114 r = s->regs[R_TIMER1_COMPARE] - r;
115 break;
116 case R_GPIO_IN:
117 case R_GPIO_OUT:
118 case R_GPIO_INTEN:
119 case R_TIMER0_CONTROL:
120 case R_TIMER0_COMPARE:
121 case R_TIMER1_CONTROL:
122 case R_TIMER1_COMPARE:
123 case R_ICAP:
124 case R_DBG_SCRATCHPAD:
125 case R_DBG_WRITE_LOCK:
126 case R_CLK_FREQUENCY:
127 case R_CAPABILITIES:
128 case R_SYSTEM_ID:
129 r = s->regs[addr];
130 break;
131
132 default:
133 error_report("milkymist_sysctl: read access to unknown register 0x"
134 TARGET_FMT_plx, addr << 2);
135 break;
136 }
137
138 trace_milkymist_sysctl_memory_read(addr << 2, r);
139
140 return r;
141 }
142
143 static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
144 unsigned size)
145 {
146 MilkymistSysctlState *s = opaque;
147
148 trace_milkymist_sysctl_memory_write(addr, value);
149
150 addr >>= 2;
151 switch (addr) {
152 case R_GPIO_OUT:
153 case R_GPIO_INTEN:
154 case R_TIMER0_COUNTER:
155 case R_TIMER1_COUNTER:
156 case R_DBG_SCRATCHPAD:
157 s->regs[addr] = value;
158 break;
159 case R_TIMER0_COMPARE:
160 ptimer_transaction_begin(s->ptimer0);
161 ptimer_set_limit(s->ptimer0, value, 0);
162 s->regs[addr] = value;
163 ptimer_transaction_commit(s->ptimer0);
164 break;
165 case R_TIMER1_COMPARE:
166 ptimer_transaction_begin(s->ptimer1);
167 ptimer_set_limit(s->ptimer1, value, 0);
168 s->regs[addr] = value;
169 ptimer_transaction_commit(s->ptimer1);
170 break;
171 case R_TIMER0_CONTROL:
172 ptimer_transaction_begin(s->ptimer0);
173 s->regs[addr] = value;
174 if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
175 trace_milkymist_sysctl_start_timer0();
176 ptimer_set_count(s->ptimer0,
177 s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
178 ptimer_run(s->ptimer0, 0);
179 } else {
180 trace_milkymist_sysctl_stop_timer0();
181 ptimer_stop(s->ptimer0);
182 }
183 ptimer_transaction_commit(s->ptimer0);
184 break;
185 case R_TIMER1_CONTROL:
186 ptimer_transaction_begin(s->ptimer1);
187 s->regs[addr] = value;
188 if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
189 trace_milkymist_sysctl_start_timer1();
190 ptimer_set_count(s->ptimer1,
191 s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
192 ptimer_run(s->ptimer1, 0);
193 } else {
194 trace_milkymist_sysctl_stop_timer1();
195 ptimer_stop(s->ptimer1);
196 }
197 ptimer_transaction_commit(s->ptimer1);
198 break;
199 case R_ICAP:
200 sysctl_icap_write(s, value);
201 break;
202 case R_DBG_WRITE_LOCK:
203 s->regs[addr] = 1;
204 break;
205 case R_SYSTEM_ID:
206 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
207 break;
208
209 case R_GPIO_IN:
210 case R_CLK_FREQUENCY:
211 case R_CAPABILITIES:
212 error_report("milkymist_sysctl: write to read-only register 0x"
213 TARGET_FMT_plx, addr << 2);
214 break;
215
216 default:
217 error_report("milkymist_sysctl: write access to unknown register 0x"
218 TARGET_FMT_plx, addr << 2);
219 break;
220 }
221 }
222
223 static const MemoryRegionOps sysctl_mmio_ops = {
224 .read = sysctl_read,
225 .write = sysctl_write,
226 .valid = {
227 .min_access_size = 4,
228 .max_access_size = 4,
229 },
230 .endianness = DEVICE_NATIVE_ENDIAN,
231 };
232
233 static void timer0_hit(void *opaque)
234 {
235 MilkymistSysctlState *s = opaque;
236
237 if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
238 s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
239 trace_milkymist_sysctl_stop_timer0();
240 ptimer_stop(s->ptimer0);
241 }
242
243 trace_milkymist_sysctl_pulse_irq_timer0();
244 qemu_irq_pulse(s->timer0_irq);
245 }
246
247 static void timer1_hit(void *opaque)
248 {
249 MilkymistSysctlState *s = opaque;
250
251 if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
252 s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
253 trace_milkymist_sysctl_stop_timer1();
254 ptimer_stop(s->ptimer1);
255 }
256
257 trace_milkymist_sysctl_pulse_irq_timer1();
258 qemu_irq_pulse(s->timer1_irq);
259 }
260
261 static void milkymist_sysctl_reset(DeviceState *d)
262 {
263 MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
264 int i;
265
266 for (i = 0; i < R_MAX; i++) {
267 s->regs[i] = 0;
268 }
269
270 ptimer_transaction_begin(s->ptimer0);
271 ptimer_stop(s->ptimer0);
272 ptimer_transaction_commit(s->ptimer0);
273 ptimer_transaction_begin(s->ptimer1);
274 ptimer_stop(s->ptimer1);
275 ptimer_transaction_commit(s->ptimer1);
276
277 /* defaults */
278 s->regs[R_ICAP] = ICAP_READY;
279 s->regs[R_SYSTEM_ID] = s->systemid;
280 s->regs[R_CLK_FREQUENCY] = s->freq_hz;
281 s->regs[R_CAPABILITIES] = s->capabilities;
282 s->regs[R_GPIO_IN] = s->strappings;
283 }
284
285 static void milkymist_sysctl_init(Object *obj)
286 {
287 MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
288 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
289
290 sysbus_init_irq(dev, &s->gpio_irq);
291 sysbus_init_irq(dev, &s->timer0_irq);
292 sysbus_init_irq(dev, &s->timer1_irq);
293
294 memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
295 "milkymist-sysctl", R_MAX * 4);
296 sysbus_init_mmio(dev, &s->regs_region);
297 }
298
299 static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
300 {
301 MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
302
303 s->ptimer0 = ptimer_init(timer0_hit, s, PTIMER_POLICY_DEFAULT);
304 s->ptimer1 = ptimer_init(timer1_hit, s, PTIMER_POLICY_DEFAULT);
305
306 ptimer_transaction_begin(s->ptimer0);
307 ptimer_set_freq(s->ptimer0, s->freq_hz);
308 ptimer_transaction_commit(s->ptimer0);
309 ptimer_transaction_begin(s->ptimer1);
310 ptimer_set_freq(s->ptimer1, s->freq_hz);
311 ptimer_transaction_commit(s->ptimer1);
312 }
313
314 static const VMStateDescription vmstate_milkymist_sysctl = {
315 .name = "milkymist-sysctl",
316 .version_id = 1,
317 .minimum_version_id = 1,
318 .fields = (VMStateField[]) {
319 VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
320 VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
321 VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
322 VMSTATE_END_OF_LIST()
323 }
324 };
325
326 static Property milkymist_sysctl_properties[] = {
327 DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
328 freq_hz, 80000000),
329 DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
330 capabilities, 0x00000000),
331 DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
332 systemid, 0x10014d31),
333 DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
334 strappings, 0x00000001),
335 DEFINE_PROP_END_OF_LIST(),
336 };
337
338 static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
339 {
340 DeviceClass *dc = DEVICE_CLASS(klass);
341
342 dc->realize = milkymist_sysctl_realize;
343 dc->reset = milkymist_sysctl_reset;
344 dc->vmsd = &vmstate_milkymist_sysctl;
345 device_class_set_props(dc, milkymist_sysctl_properties);
346 }
347
348 static const TypeInfo milkymist_sysctl_info = {
349 .name = TYPE_MILKYMIST_SYSCTL,
350 .parent = TYPE_SYS_BUS_DEVICE,
351 .instance_size = sizeof(MilkymistSysctlState),
352 .instance_init = milkymist_sysctl_init,
353 .class_init = milkymist_sysctl_class_init,
354 };
355
356 static void milkymist_sysctl_register_types(void)
357 {
358 type_register_static(&milkymist_sysctl_info);
359 }
360
361 type_init(milkymist_sysctl_register_types)