Add access control support to qemu bridge helper
[qemu.git] / hw / tusb6010.c
1 /*
2 * Texas Instruments TUSB6010 emulation.
3 * Based on reverse-engineering of a linux driver.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "usb.h"
24 #include "omap.h"
25 #include "irq.h"
26 #include "devices.h"
27 #include "sysbus.h"
28
29 typedef struct TUSBState {
30 SysBusDevice busdev;
31 MemoryRegion iomem[2];
32 qemu_irq irq;
33 MUSBState *musb;
34 QEMUTimer *otg_timer;
35 QEMUTimer *pwr_timer;
36
37 int power;
38 uint32_t scratch;
39 uint16_t test_reset;
40 uint32_t prcm_config;
41 uint32_t prcm_mngmt;
42 uint16_t otg_status;
43 uint32_t dev_config;
44 int host_mode;
45 uint32_t intr;
46 uint32_t intr_ok;
47 uint32_t mask;
48 uint32_t usbip_intr;
49 uint32_t usbip_mask;
50 uint32_t gpio_intr;
51 uint32_t gpio_mask;
52 uint32_t gpio_config;
53 uint32_t dma_intr;
54 uint32_t dma_mask;
55 uint32_t dma_map;
56 uint32_t dma_config;
57 uint32_t ep0_config;
58 uint32_t rx_config[15];
59 uint32_t tx_config[15];
60 uint32_t wkup_mask;
61 uint32_t pullup[2];
62 uint32_t control_config;
63 uint32_t otg_timer_val;
64 } TUSBState;
65
66 #define TUSB_DEVCLOCK 60000000 /* 60 MHz */
67
68 #define TUSB_VLYNQ_CTRL 0x004
69
70 /* Mentor Graphics OTG core registers. */
71 #define TUSB_BASE_OFFSET 0x400
72
73 /* FIFO registers, 32-bit. */
74 #define TUSB_FIFO_BASE 0x600
75
76 /* Device System & Control registers, 32-bit. */
77 #define TUSB_SYS_REG_BASE 0x800
78
79 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
80 #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16)
81 #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15)
82 #define TUSB_DEV_CONF_SOFT_ID (1 << 1)
83 #define TUSB_DEV_CONF_ID_SEL (1 << 0)
84
85 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
86 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
87 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
88 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23)
89 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19)
90 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18)
91 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
92 #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16)
93 #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15)
94 #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14)
95 #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13)
96 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12)
97 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11)
98 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10)
99 #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9)
100 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7)
101 #define TUSB_PHY_OTG_CTRL_PD (1 << 6)
102 #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5)
103 #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4)
104 #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3)
105 #define TUSB_PHY_OTG_CTRL_RESET (1 << 2)
106 #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1)
107 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
108
109 /* OTG status register */
110 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
111 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8)
112 #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7)
113 #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6)
114 #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5)
115 #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4)
116 #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3)
117 #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2)
118 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
119 #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1)
120 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
121
122 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
123 #define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31)
124 #define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
125 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
126
127 /* PRCM configuration register */
128 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
129 #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24)
130 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
131
132 /* PRCM management register */
133 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
134 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25)
135 #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24)
136 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20)
137 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19)
138 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18)
139 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
140 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
141 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
142 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8)
143 #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4)
144 #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3)
145 #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2)
146 #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1)
147 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
148
149 /* Wake-up source clear and mask registers */
150 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
151 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
152 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
153 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
154 #define TUSB_PRCM_WGPIO_7 (1 << 12)
155 #define TUSB_PRCM_WGPIO_6 (1 << 11)
156 #define TUSB_PRCM_WGPIO_5 (1 << 10)
157 #define TUSB_PRCM_WGPIO_4 (1 << 9)
158 #define TUSB_PRCM_WGPIO_3 (1 << 8)
159 #define TUSB_PRCM_WGPIO_2 (1 << 7)
160 #define TUSB_PRCM_WGPIO_1 (1 << 6)
161 #define TUSB_PRCM_WGPIO_0 (1 << 5)
162 #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */
163 #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */
164 #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */
165 #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */
166 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */
167
168 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
169 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
170 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
171 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
172 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
173 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
174 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
175 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
176 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
177 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
178 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
179 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
180 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
181 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
182 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
183 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
184
185 /* NOR flash interrupt source registers */
186 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
187 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
188 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
189 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
190 #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24)
191 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
192 #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16)
193 #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15)
194 #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14)
195 #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13)
196 #define TUSB_INT_SRC_DEV_READY (1 << 12)
197 #define TUSB_INT_SRC_USB_IP_TX (1 << 9)
198 #define TUSB_INT_SRC_USB_IP_RX (1 << 8)
199 #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7)
200 #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6)
201 #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5)
202 #define TUSB_INT_SRC_USB_IP_CONN (1 << 4)
203 #define TUSB_INT_SRC_USB_IP_SOF (1 << 3)
204 #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2)
205 #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1)
206 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
207
208 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
209 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
210 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
211 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
212 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
213 #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c)
214 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
215 #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c)
216 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188)
217 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
218 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
219 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
220
221 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
222 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
223
224 /* Device System & Control register bitfields */
225 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18)
226 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
227 #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16)
228 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
229 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
230 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20)
231 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16)
232 #define TUSB_EP0_CONFIG_SW_EN (1 << 8)
233 #define TUSB_EP0_CONFIG_DIR_TX (1 << 7)
234 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
235 #define TUSB_EP_CONFIG_SW_EN (1 << 31)
236 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
237 #define TUSB_PROD_TEST_RESET_VAL 0xa596
238
239 static void tusb_intr_update(TUSBState *s)
240 {
241 if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
242 qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
243 else
244 qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
245 }
246
247 static void tusb_usbip_intr_update(TUSBState *s)
248 {
249 /* TX interrupt in the MUSB */
250 if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
251 s->intr |= TUSB_INT_SRC_USB_IP_TX;
252 else
253 s->intr &= ~TUSB_INT_SRC_USB_IP_TX;
254
255 /* RX interrupt in the MUSB */
256 if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask)
257 s->intr |= TUSB_INT_SRC_USB_IP_RX;
258 else
259 s->intr &= ~TUSB_INT_SRC_USB_IP_RX;
260
261 /* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */
262
263 tusb_intr_update(s);
264 }
265
266 static void tusb_dma_intr_update(TUSBState *s)
267 {
268 if (s->dma_intr & ~s->dma_mask)
269 s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
270 else
271 s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE;
272
273 tusb_intr_update(s);
274 }
275
276 static void tusb_gpio_intr_update(TUSBState *s)
277 {
278 /* TODO: How is this signalled? */
279 }
280
281 extern CPUReadMemoryFunc * const musb_read[];
282 extern CPUWriteMemoryFunc * const musb_write[];
283
284 static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
285 {
286 TUSBState *s = (TUSBState *) opaque;
287
288 switch (addr & 0xfff) {
289 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
290 return musb_read[0](s->musb, addr & 0x1ff);
291
292 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
293 return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c));
294 }
295
296 printf("%s: unknown register at %03x\n",
297 __FUNCTION__, (int) (addr & 0xfff));
298 return 0;
299 }
300
301 static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
302 {
303 TUSBState *s = (TUSBState *) opaque;
304
305 switch (addr & 0xfff) {
306 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
307 return musb_read[1](s->musb, addr & 0x1ff);
308
309 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
310 return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c));
311 }
312
313 printf("%s: unknown register at %03x\n",
314 __FUNCTION__, (int) (addr & 0xfff));
315 return 0;
316 }
317
318 static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
319 {
320 TUSBState *s = (TUSBState *) opaque;
321 int offset = addr & 0xfff;
322 int epnum;
323 uint32_t ret;
324
325 switch (offset) {
326 case TUSB_DEV_CONF:
327 return s->dev_config;
328
329 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
330 return musb_read[2](s->musb, offset & 0x1ff);
331
332 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
333 return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c));
334
335 case TUSB_PHY_OTG_CTRL_ENABLE:
336 case TUSB_PHY_OTG_CTRL:
337 return 0x00; /* TODO */
338
339 case TUSB_DEV_OTG_STAT:
340 ret = s->otg_status;
341 #if 0
342 if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
343 ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
344 #endif
345 return ret;
346 case TUSB_DEV_OTG_TIMER:
347 return s->otg_timer_val;
348
349 case TUSB_PRCM_REV:
350 return 0x20;
351 case TUSB_PRCM_CONF:
352 return s->prcm_config;
353 case TUSB_PRCM_MNGMT:
354 return s->prcm_mngmt;
355 case TUSB_PRCM_WAKEUP_SOURCE:
356 case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */
357 return 0x00000000;
358 case TUSB_PRCM_WAKEUP_MASK:
359 return s->wkup_mask;
360
361 case TUSB_PULLUP_1_CTRL:
362 return s->pullup[0];
363 case TUSB_PULLUP_2_CTRL:
364 return s->pullup[1];
365
366 case TUSB_INT_CTRL_REV:
367 return 0x20;
368 case TUSB_INT_CTRL_CONF:
369 return s->control_config;
370
371 case TUSB_USBIP_INT_SRC:
372 case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */
373 case TUSB_USBIP_INT_CLEAR:
374 return s->usbip_intr;
375 case TUSB_USBIP_INT_MASK:
376 return s->usbip_mask;
377
378 case TUSB_DMA_INT_SRC:
379 case TUSB_DMA_INT_SET: /* TODO: What do these two return? */
380 case TUSB_DMA_INT_CLEAR:
381 return s->dma_intr;
382 case TUSB_DMA_INT_MASK:
383 return s->dma_mask;
384
385 case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */
386 case TUSB_GPIO_INT_SET:
387 case TUSB_GPIO_INT_CLEAR:
388 return s->gpio_intr;
389 case TUSB_GPIO_INT_MASK:
390 return s->gpio_mask;
391
392 case TUSB_INT_SRC:
393 case TUSB_INT_SRC_SET: /* TODO: What do these two return? */
394 case TUSB_INT_SRC_CLEAR:
395 return s->intr;
396 case TUSB_INT_MASK:
397 return s->mask;
398
399 case TUSB_GPIO_REV:
400 return 0x30;
401 case TUSB_GPIO_CONF:
402 return s->gpio_config;
403
404 case TUSB_DMA_CTRL_REV:
405 return 0x30;
406 case TUSB_DMA_REQ_CONF:
407 return s->dma_config;
408 case TUSB_EP0_CONF:
409 return s->ep0_config;
410 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
411 epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
412 return s->tx_config[epnum];
413 case TUSB_DMA_EP_MAP:
414 return s->dma_map;
415 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
416 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
417 return s->rx_config[epnum];
418 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
419 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
420 return 0x00000000; /* TODO */
421 case TUSB_WAIT_COUNT:
422 return 0x00; /* TODO */
423
424 case TUSB_SCRATCH_PAD:
425 return s->scratch;
426
427 case TUSB_PROD_TEST_RESET:
428 return s->test_reset;
429
430 /* DIE IDs */
431 case TUSB_DIDR1_LO:
432 return 0xa9453c59;
433 case TUSB_DIDR1_HI:
434 return 0x54059adf;
435 }
436
437 printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
438 return 0;
439 }
440
441 static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
442 uint32_t value)
443 {
444 TUSBState *s = (TUSBState *) opaque;
445
446 switch (addr & 0xfff) {
447 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
448 musb_write[0](s->musb, addr & 0x1ff, value);
449 break;
450
451 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
452 musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
453 break;
454
455 default:
456 printf("%s: unknown register at %03x\n",
457 __FUNCTION__, (int) (addr & 0xfff));
458 return;
459 }
460 }
461
462 static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
463 uint32_t value)
464 {
465 TUSBState *s = (TUSBState *) opaque;
466
467 switch (addr & 0xfff) {
468 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
469 musb_write[1](s->musb, addr & 0x1ff, value);
470 break;
471
472 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
473 musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
474 break;
475
476 default:
477 printf("%s: unknown register at %03x\n",
478 __FUNCTION__, (int) (addr & 0xfff));
479 return;
480 }
481 }
482
483 static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
484 uint32_t value)
485 {
486 TUSBState *s = (TUSBState *) opaque;
487 int offset = addr & 0xfff;
488 int epnum;
489
490 switch (offset) {
491 case TUSB_VLYNQ_CTRL:
492 break;
493
494 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
495 musb_write[2](s->musb, offset & 0x1ff, value);
496 break;
497
498 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
499 musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
500 break;
501
502 case TUSB_DEV_CONF:
503 s->dev_config = value;
504 s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
505 if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
506 hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
507 break;
508
509 case TUSB_PHY_OTG_CTRL_ENABLE:
510 case TUSB_PHY_OTG_CTRL:
511 return; /* TODO */
512 case TUSB_DEV_OTG_TIMER:
513 s->otg_timer_val = value;
514 if (value & TUSB_DEV_OTG_TIMER_ENABLE)
515 qemu_mod_timer(s->otg_timer, qemu_get_clock_ns(vm_clock) +
516 muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
517 get_ticks_per_sec(), TUSB_DEVCLOCK));
518 else
519 qemu_del_timer(s->otg_timer);
520 break;
521
522 case TUSB_PRCM_CONF:
523 s->prcm_config = value;
524 break;
525 case TUSB_PRCM_MNGMT:
526 s->prcm_mngmt = value;
527 break;
528 case TUSB_PRCM_WAKEUP_CLEAR:
529 break;
530 case TUSB_PRCM_WAKEUP_MASK:
531 s->wkup_mask = value;
532 break;
533
534 case TUSB_PULLUP_1_CTRL:
535 s->pullup[0] = value;
536 break;
537 case TUSB_PULLUP_2_CTRL:
538 s->pullup[1] = value;
539 break;
540 case TUSB_INT_CTRL_CONF:
541 s->control_config = value;
542 tusb_intr_update(s);
543 break;
544
545 case TUSB_USBIP_INT_SET:
546 s->usbip_intr |= value;
547 tusb_usbip_intr_update(s);
548 break;
549 case TUSB_USBIP_INT_CLEAR:
550 s->usbip_intr &= ~value;
551 tusb_usbip_intr_update(s);
552 musb_core_intr_clear(s->musb, ~value);
553 break;
554 case TUSB_USBIP_INT_MASK:
555 s->usbip_mask = value;
556 tusb_usbip_intr_update(s);
557 break;
558
559 case TUSB_DMA_INT_SET:
560 s->dma_intr |= value;
561 tusb_dma_intr_update(s);
562 break;
563 case TUSB_DMA_INT_CLEAR:
564 s->dma_intr &= ~value;
565 tusb_dma_intr_update(s);
566 break;
567 case TUSB_DMA_INT_MASK:
568 s->dma_mask = value;
569 tusb_dma_intr_update(s);
570 break;
571
572 case TUSB_GPIO_INT_SET:
573 s->gpio_intr |= value;
574 tusb_gpio_intr_update(s);
575 break;
576 case TUSB_GPIO_INT_CLEAR:
577 s->gpio_intr &= ~value;
578 tusb_gpio_intr_update(s);
579 break;
580 case TUSB_GPIO_INT_MASK:
581 s->gpio_mask = value;
582 tusb_gpio_intr_update(s);
583 break;
584
585 case TUSB_INT_SRC_SET:
586 s->intr |= value;
587 tusb_intr_update(s);
588 break;
589 case TUSB_INT_SRC_CLEAR:
590 s->intr &= ~value;
591 tusb_intr_update(s);
592 break;
593 case TUSB_INT_MASK:
594 s->mask = value;
595 tusb_intr_update(s);
596 break;
597
598 case TUSB_GPIO_CONF:
599 s->gpio_config = value;
600 break;
601 case TUSB_DMA_REQ_CONF:
602 s->dma_config = value;
603 break;
604 case TUSB_EP0_CONF:
605 s->ep0_config = value & 0x1ff;
606 musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
607 value & TUSB_EP0_CONFIG_DIR_TX);
608 break;
609 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
610 epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
611 s->tx_config[epnum] = value;
612 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1);
613 break;
614 case TUSB_DMA_EP_MAP:
615 s->dma_map = value;
616 break;
617 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
618 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
619 s->rx_config[epnum] = value;
620 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0);
621 break;
622 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
623 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
624 return; /* TODO */
625 case TUSB_WAIT_COUNT:
626 return; /* TODO */
627
628 case TUSB_SCRATCH_PAD:
629 s->scratch = value;
630 break;
631
632 case TUSB_PROD_TEST_RESET:
633 s->test_reset = value;
634 break;
635
636 default:
637 printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
638 return;
639 }
640 }
641
642 static const MemoryRegionOps tusb_async_ops = {
643 .old_mmio = {
644 .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
645 .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
646 },
647 .endianness = DEVICE_NATIVE_ENDIAN,
648 };
649
650 static void tusb_otg_tick(void *opaque)
651 {
652 TUSBState *s = (TUSBState *) opaque;
653
654 s->otg_timer_val = 0;
655 s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
656 tusb_intr_update(s);
657 }
658
659 static void tusb_power_tick(void *opaque)
660 {
661 TUSBState *s = (TUSBState *) opaque;
662
663 if (s->power) {
664 s->intr_ok = ~0;
665 tusb_intr_update(s);
666 }
667 }
668
669 static void tusb_musb_core_intr(void *opaque, int source, int level)
670 {
671 TUSBState *s = (TUSBState *) opaque;
672 uint16_t otg_status = s->otg_status;
673
674 switch (source) {
675 case musb_set_vbus:
676 if (level)
677 otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID;
678 else
679 otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
680
681 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
682 /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
683 if (s->otg_status != otg_status) {
684 s->otg_status = otg_status;
685 s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG;
686 tusb_intr_update(s);
687 }
688 break;
689
690 case musb_set_session:
691 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
692 /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
693 if (level) {
694 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID;
695 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END;
696 } else {
697 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID;
698 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END;
699 }
700
701 /* XXX: some IRQ or anything? */
702 break;
703
704 case musb_irq_tx:
705 case musb_irq_rx:
706 s->usbip_intr = musb_core_intr_get(s->musb);
707 /* Fall through. */
708 default:
709 if (level)
710 s->intr |= 1 << source;
711 else
712 s->intr &= ~(1 << source);
713 tusb_intr_update(s);
714 break;
715 }
716 }
717
718 static void tusb6010_power(TUSBState *s, int on)
719 {
720 if (!on) {
721 s->power = 0;
722 } else if (!s->power && on) {
723 s->power = 1;
724 /* Pull the interrupt down after TUSB6010 comes up. */
725 s->intr_ok = 0;
726 tusb_intr_update(s);
727 qemu_mod_timer(s->pwr_timer,
728 qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 2);
729 }
730 }
731
732 static void tusb6010_irq(void *opaque, int source, int level)
733 {
734 if (source) {
735 tusb_musb_core_intr(opaque, source - 1, level);
736 } else {
737 tusb6010_power(opaque, level);
738 }
739 }
740
741 static void tusb6010_reset(DeviceState *dev)
742 {
743 TUSBState *s = FROM_SYSBUS(TUSBState, sysbus_from_qdev(dev));
744 int i;
745
746 s->test_reset = TUSB_PROD_TEST_RESET_VAL;
747 s->host_mode = 0;
748 s->dev_config = 0;
749 s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
750 s->power = 0;
751 s->mask = 0xffffffff;
752 s->intr = 0x00000000;
753 s->otg_timer_val = 0;
754 s->scratch = 0;
755 s->prcm_config = 0;
756 s->prcm_mngmt = 0;
757 s->intr_ok = 0;
758 s->usbip_intr = 0;
759 s->usbip_mask = 0;
760 s->gpio_intr = 0;
761 s->gpio_mask = 0;
762 s->gpio_config = 0;
763 s->dma_intr = 0;
764 s->dma_mask = 0;
765 s->dma_map = 0;
766 s->dma_config = 0;
767 s->ep0_config = 0;
768 s->wkup_mask = 0;
769 s->pullup[0] = s->pullup[1] = 0;
770 s->control_config = 0;
771 for (i = 0; i < 15; i++) {
772 s->rx_config[i] = s->tx_config[i] = 0;
773 }
774 musb_reset(s->musb);
775 }
776
777 static int tusb6010_init(SysBusDevice *dev)
778 {
779 TUSBState *s = FROM_SYSBUS(TUSBState, dev);
780 s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
781 s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
782 memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
783 UINT32_MAX);
784 sysbus_init_mmio(dev, &s->iomem[0]);
785 sysbus_init_mmio(dev, &s->iomem[1]);
786 sysbus_init_irq(dev, &s->irq);
787 qdev_init_gpio_in(&dev->qdev, tusb6010_irq, musb_irq_max + 1);
788 s->musb = musb_init(&dev->qdev, 1);
789 return 0;
790 }
791
792 static void tusb6010_class_init(ObjectClass *klass, void *data)
793 {
794 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
795
796 k->init = tusb6010_init;
797 }
798
799 static DeviceInfo tusb6010_info = {
800 .name = "tusb6010",
801 .size = sizeof(TUSBState),
802 .reset = tusb6010_reset,
803 .class_init = tusb6010_class_init,
804 };
805
806 static void tusb6010_register_device(void)
807 {
808 sysbus_register_withprop(&tusb6010_info);
809 }
810
811 device_init(tusb6010_register_device)