PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / usb-ohci.c
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
27 */
28
29 #include "hw.h"
30 #include "qemu-timer.h"
31 #include "usb.h"
32 #include "pci.h"
33 #include "usb-ohci.h"
34 #include "sysbus.h"
35 #include "qdev-addr.h"
36
37 //#define DEBUG_OHCI
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
40 //#define DEBUG_ISOCH
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #ifdef DEBUG_OHCI
45 #define DPRINTF printf
46 #else
47 #define DPRINTF(...)
48 #endif
49
50 /* Number of Downstream Ports on the root hub. */
51
52 #define OHCI_MAX_PORTS 15
53
54 static int64_t usb_frame_time;
55 static int64_t usb_bit_time;
56
57 typedef struct OHCIPort {
58 USBPort port;
59 uint32_t ctrl;
60 } OHCIPort;
61
62 typedef struct {
63 USBBus bus;
64 qemu_irq irq;
65 MemoryRegion mem;
66 int num_ports;
67 const char *name;
68
69 QEMUTimer *eof_timer;
70 int64_t sof_time;
71
72 /* OHCI state */
73 /* Control partition */
74 uint32_t ctl, status;
75 uint32_t intr_status;
76 uint32_t intr;
77
78 /* memory pointer partition */
79 uint32_t hcca;
80 uint32_t ctrl_head, ctrl_cur;
81 uint32_t bulk_head, bulk_cur;
82 uint32_t per_cur;
83 uint32_t done;
84 int done_count;
85
86 /* Frame counter partition */
87 uint32_t fsmps:15;
88 uint32_t fit:1;
89 uint32_t fi:14;
90 uint32_t frt:1;
91 uint16_t frame_number;
92 uint16_t padding;
93 uint32_t pstart;
94 uint32_t lst;
95
96 /* Root Hub partition */
97 uint32_t rhdesc_a, rhdesc_b;
98 uint32_t rhstatus;
99 OHCIPort rhport[OHCI_MAX_PORTS];
100
101 /* PXA27x Non-OHCI events */
102 uint32_t hstatus;
103 uint32_t hmask;
104 uint32_t hreset;
105 uint32_t htest;
106
107 /* SM501 local memory offset */
108 target_phys_addr_t localmem_base;
109
110 /* Active packets. */
111 uint32_t old_ctl;
112 USBPacket usb_packet;
113 uint8_t usb_buf[8192];
114 uint32_t async_td;
115 int async_complete;
116
117 } OHCIState;
118
119 /* Host Controller Communications Area */
120 struct ohci_hcca {
121 uint32_t intr[32];
122 uint16_t frame, pad;
123 uint32_t done;
124 };
125
126 static void ohci_bus_stop(OHCIState *ohci);
127 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev);
128
129 /* Bitfields for the first word of an Endpoint Desciptor. */
130 #define OHCI_ED_FA_SHIFT 0
131 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
132 #define OHCI_ED_EN_SHIFT 7
133 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
134 #define OHCI_ED_D_SHIFT 11
135 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
136 #define OHCI_ED_S (1<<13)
137 #define OHCI_ED_K (1<<14)
138 #define OHCI_ED_F (1<<15)
139 #define OHCI_ED_MPS_SHIFT 16
140 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
141
142 /* Flags in the head field of an Endpoint Desciptor. */
143 #define OHCI_ED_H 1
144 #define OHCI_ED_C 2
145
146 /* Bitfields for the first word of a Transfer Desciptor. */
147 #define OHCI_TD_R (1<<18)
148 #define OHCI_TD_DP_SHIFT 19
149 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
150 #define OHCI_TD_DI_SHIFT 21
151 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
152 #define OHCI_TD_T0 (1<<24)
153 #define OHCI_TD_T1 (1<<25)
154 #define OHCI_TD_EC_SHIFT 26
155 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
156 #define OHCI_TD_CC_SHIFT 28
157 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
158
159 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
160 /* CC & DI - same as in the General Transfer Desciptor */
161 #define OHCI_TD_SF_SHIFT 0
162 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
163 #define OHCI_TD_FC_SHIFT 24
164 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
165
166 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
167 #define OHCI_TD_PSW_CC_SHIFT 12
168 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
169 #define OHCI_TD_PSW_SIZE_SHIFT 0
170 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
171
172 #define OHCI_PAGE_MASK 0xfffff000
173 #define OHCI_OFFSET_MASK 0xfff
174
175 #define OHCI_DPTR_MASK 0xfffffff0
176
177 #define OHCI_BM(val, field) \
178 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
179
180 #define OHCI_SET_BM(val, field, newval) do { \
181 val &= ~OHCI_##field##_MASK; \
182 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
183 } while(0)
184
185 /* endpoint descriptor */
186 struct ohci_ed {
187 uint32_t flags;
188 uint32_t tail;
189 uint32_t head;
190 uint32_t next;
191 };
192
193 /* General transfer descriptor */
194 struct ohci_td {
195 uint32_t flags;
196 uint32_t cbp;
197 uint32_t next;
198 uint32_t be;
199 };
200
201 /* Isochronous transfer descriptor */
202 struct ohci_iso_td {
203 uint32_t flags;
204 uint32_t bp;
205 uint32_t next;
206 uint32_t be;
207 uint16_t offset[8];
208 };
209
210 #define USB_HZ 12000000
211
212 /* OHCI Local stuff */
213 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
214 #define OHCI_CTL_PLE (1<<2)
215 #define OHCI_CTL_IE (1<<3)
216 #define OHCI_CTL_CLE (1<<4)
217 #define OHCI_CTL_BLE (1<<5)
218 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
219 #define OHCI_USB_RESET 0x00
220 #define OHCI_USB_RESUME 0x40
221 #define OHCI_USB_OPERATIONAL 0x80
222 #define OHCI_USB_SUSPEND 0xc0
223 #define OHCI_CTL_IR (1<<8)
224 #define OHCI_CTL_RWC (1<<9)
225 #define OHCI_CTL_RWE (1<<10)
226
227 #define OHCI_STATUS_HCR (1<<0)
228 #define OHCI_STATUS_CLF (1<<1)
229 #define OHCI_STATUS_BLF (1<<2)
230 #define OHCI_STATUS_OCR (1<<3)
231 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
232
233 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
234 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
235 #define OHCI_INTR_SF (1<<2) /* Start of frame */
236 #define OHCI_INTR_RD (1<<3) /* Resume detect */
237 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
238 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
239 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
240 #define OHCI_INTR_OC (1<<30) /* Ownership change */
241 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
242
243 #define OHCI_HCCA_SIZE 0x100
244 #define OHCI_HCCA_MASK 0xffffff00
245
246 #define OHCI_EDPTR_MASK 0xfffffff0
247
248 #define OHCI_FMI_FI 0x00003fff
249 #define OHCI_FMI_FSMPS 0xffff0000
250 #define OHCI_FMI_FIT 0x80000000
251
252 #define OHCI_FR_RT (1<<31)
253
254 #define OHCI_LS_THRESH 0x628
255
256 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
257 #define OHCI_RHA_PSM (1<<8)
258 #define OHCI_RHA_NPS (1<<9)
259 #define OHCI_RHA_DT (1<<10)
260 #define OHCI_RHA_OCPM (1<<11)
261 #define OHCI_RHA_NOCP (1<<12)
262 #define OHCI_RHA_POTPGT_MASK 0xff000000
263
264 #define OHCI_RHS_LPS (1<<0)
265 #define OHCI_RHS_OCI (1<<1)
266 #define OHCI_RHS_DRWE (1<<15)
267 #define OHCI_RHS_LPSC (1<<16)
268 #define OHCI_RHS_OCIC (1<<17)
269 #define OHCI_RHS_CRWE (1<<31)
270
271 #define OHCI_PORT_CCS (1<<0)
272 #define OHCI_PORT_PES (1<<1)
273 #define OHCI_PORT_PSS (1<<2)
274 #define OHCI_PORT_POCI (1<<3)
275 #define OHCI_PORT_PRS (1<<4)
276 #define OHCI_PORT_PPS (1<<8)
277 #define OHCI_PORT_LSDA (1<<9)
278 #define OHCI_PORT_CSC (1<<16)
279 #define OHCI_PORT_PESC (1<<17)
280 #define OHCI_PORT_PSSC (1<<18)
281 #define OHCI_PORT_OCIC (1<<19)
282 #define OHCI_PORT_PRSC (1<<20)
283 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
284 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
285
286 #define OHCI_TD_DIR_SETUP 0x0
287 #define OHCI_TD_DIR_OUT 0x1
288 #define OHCI_TD_DIR_IN 0x2
289 #define OHCI_TD_DIR_RESERVED 0x3
290
291 #define OHCI_CC_NOERROR 0x0
292 #define OHCI_CC_CRC 0x1
293 #define OHCI_CC_BITSTUFFING 0x2
294 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
295 #define OHCI_CC_STALL 0x4
296 #define OHCI_CC_DEVICENOTRESPONDING 0x5
297 #define OHCI_CC_PIDCHECKFAILURE 0x6
298 #define OHCI_CC_UNDEXPETEDPID 0x7
299 #define OHCI_CC_DATAOVERRUN 0x8
300 #define OHCI_CC_DATAUNDERRUN 0x9
301 #define OHCI_CC_BUFFEROVERRUN 0xc
302 #define OHCI_CC_BUFFERUNDERRUN 0xd
303
304 #define OHCI_HRESET_FSBIR (1 << 0)
305
306 /* Update IRQ levels */
307 static inline void ohci_intr_update(OHCIState *ohci)
308 {
309 int level = 0;
310
311 if ((ohci->intr & OHCI_INTR_MIE) &&
312 (ohci->intr_status & ohci->intr))
313 level = 1;
314
315 qemu_set_irq(ohci->irq, level);
316 }
317
318 /* Set an interrupt */
319 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
320 {
321 ohci->intr_status |= intr;
322 ohci_intr_update(ohci);
323 }
324
325 /* Attach or detach a device on a root hub port. */
326 static void ohci_attach(USBPort *port1)
327 {
328 OHCIState *s = port1->opaque;
329 OHCIPort *port = &s->rhport[port1->index];
330 uint32_t old_state = port->ctrl;
331
332 /* set connect status */
333 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
334
335 /* update speed */
336 if (port->port.dev->speed == USB_SPEED_LOW) {
337 port->ctrl |= OHCI_PORT_LSDA;
338 } else {
339 port->ctrl &= ~OHCI_PORT_LSDA;
340 }
341
342 /* notify of remote-wakeup */
343 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
344 ohci_set_interrupt(s, OHCI_INTR_RD);
345 }
346
347 DPRINTF("usb-ohci: Attached port %d\n", port1->index);
348
349 if (old_state != port->ctrl) {
350 ohci_set_interrupt(s, OHCI_INTR_RHSC);
351 }
352 }
353
354 static void ohci_detach(USBPort *port1)
355 {
356 OHCIState *s = port1->opaque;
357 OHCIPort *port = &s->rhport[port1->index];
358 uint32_t old_state = port->ctrl;
359
360 ohci_async_cancel_device(s, port1->dev);
361
362 /* set connect status */
363 if (port->ctrl & OHCI_PORT_CCS) {
364 port->ctrl &= ~OHCI_PORT_CCS;
365 port->ctrl |= OHCI_PORT_CSC;
366 }
367 /* disable port */
368 if (port->ctrl & OHCI_PORT_PES) {
369 port->ctrl &= ~OHCI_PORT_PES;
370 port->ctrl |= OHCI_PORT_PESC;
371 }
372 DPRINTF("usb-ohci: Detached port %d\n", port1->index);
373
374 if (old_state != port->ctrl) {
375 ohci_set_interrupt(s, OHCI_INTR_RHSC);
376 }
377 }
378
379 static void ohci_wakeup(USBPort *port1)
380 {
381 OHCIState *s = port1->opaque;
382 OHCIPort *port = &s->rhport[port1->index];
383 uint32_t intr = 0;
384 if (port->ctrl & OHCI_PORT_PSS) {
385 DPRINTF("usb-ohci: port %d: wakeup\n", port1->index);
386 port->ctrl |= OHCI_PORT_PSSC;
387 port->ctrl &= ~OHCI_PORT_PSS;
388 intr = OHCI_INTR_RHSC;
389 }
390 /* Note that the controller can be suspended even if this port is not */
391 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
392 DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
393 /* This is the one state transition the controller can do by itself */
394 s->ctl &= ~OHCI_CTL_HCFS;
395 s->ctl |= OHCI_USB_RESUME;
396 /* In suspend mode only ResumeDetected is possible, not RHSC:
397 * see the OHCI spec 5.1.2.3.
398 */
399 intr = OHCI_INTR_RD;
400 }
401 ohci_set_interrupt(s, intr);
402 }
403
404 static void ohci_child_detach(USBPort *port1, USBDevice *child)
405 {
406 OHCIState *s = port1->opaque;
407
408 ohci_async_cancel_device(s, child);
409 }
410
411 /* Reset the controller */
412 static void ohci_reset(void *opaque)
413 {
414 OHCIState *ohci = opaque;
415 OHCIPort *port;
416 int i;
417
418 ohci_bus_stop(ohci);
419 ohci->ctl = 0;
420 ohci->old_ctl = 0;
421 ohci->status = 0;
422 ohci->intr_status = 0;
423 ohci->intr = OHCI_INTR_MIE;
424
425 ohci->hcca = 0;
426 ohci->ctrl_head = ohci->ctrl_cur = 0;
427 ohci->bulk_head = ohci->bulk_cur = 0;
428 ohci->per_cur = 0;
429 ohci->done = 0;
430 ohci->done_count = 7;
431
432 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
433 * I took the value linux sets ...
434 */
435 ohci->fsmps = 0x2778;
436 ohci->fi = 0x2edf;
437 ohci->fit = 0;
438 ohci->frt = 0;
439 ohci->frame_number = 0;
440 ohci->pstart = 0;
441 ohci->lst = OHCI_LS_THRESH;
442
443 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
444 ohci->rhdesc_b = 0x0; /* Impl. specific */
445 ohci->rhstatus = 0;
446
447 for (i = 0; i < ohci->num_ports; i++)
448 {
449 port = &ohci->rhport[i];
450 port->ctrl = 0;
451 if (port->port.dev && port->port.dev->attached) {
452 usb_reset(&port->port);
453 }
454 }
455 if (ohci->async_td) {
456 usb_cancel_packet(&ohci->usb_packet);
457 ohci->async_td = 0;
458 }
459 DPRINTF("usb-ohci: Reset %s\n", ohci->name);
460 }
461
462 /* Get an array of dwords from main memory */
463 static inline int get_dwords(OHCIState *ohci,
464 uint32_t addr, uint32_t *buf, int num)
465 {
466 int i;
467
468 addr += ohci->localmem_base;
469
470 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
471 cpu_physical_memory_read(addr, buf, sizeof(*buf));
472 *buf = le32_to_cpu(*buf);
473 }
474
475 return 1;
476 }
477
478 /* Put an array of dwords in to main memory */
479 static inline int put_dwords(OHCIState *ohci,
480 uint32_t addr, uint32_t *buf, int num)
481 {
482 int i;
483
484 addr += ohci->localmem_base;
485
486 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
487 uint32_t tmp = cpu_to_le32(*buf);
488 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
489 }
490
491 return 1;
492 }
493
494 /* Get an array of words from main memory */
495 static inline int get_words(OHCIState *ohci,
496 uint32_t addr, uint16_t *buf, int num)
497 {
498 int i;
499
500 addr += ohci->localmem_base;
501
502 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
503 cpu_physical_memory_read(addr, buf, sizeof(*buf));
504 *buf = le16_to_cpu(*buf);
505 }
506
507 return 1;
508 }
509
510 /* Put an array of words in to main memory */
511 static inline int put_words(OHCIState *ohci,
512 uint32_t addr, uint16_t *buf, int num)
513 {
514 int i;
515
516 addr += ohci->localmem_base;
517
518 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
519 uint16_t tmp = cpu_to_le16(*buf);
520 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
521 }
522
523 return 1;
524 }
525
526 static inline int ohci_read_ed(OHCIState *ohci,
527 uint32_t addr, struct ohci_ed *ed)
528 {
529 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
530 }
531
532 static inline int ohci_read_td(OHCIState *ohci,
533 uint32_t addr, struct ohci_td *td)
534 {
535 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
536 }
537
538 static inline int ohci_read_iso_td(OHCIState *ohci,
539 uint32_t addr, struct ohci_iso_td *td)
540 {
541 return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
542 get_words(ohci, addr + 16, td->offset, 8));
543 }
544
545 static inline int ohci_read_hcca(OHCIState *ohci,
546 uint32_t addr, struct ohci_hcca *hcca)
547 {
548 cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
549 return 1;
550 }
551
552 static inline int ohci_put_ed(OHCIState *ohci,
553 uint32_t addr, struct ohci_ed *ed)
554 {
555 return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
556 }
557
558 static inline int ohci_put_td(OHCIState *ohci,
559 uint32_t addr, struct ohci_td *td)
560 {
561 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
562 }
563
564 static inline int ohci_put_iso_td(OHCIState *ohci,
565 uint32_t addr, struct ohci_iso_td *td)
566 {
567 return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
568 put_words(ohci, addr + 16, td->offset, 8));
569 }
570
571 static inline int ohci_put_hcca(OHCIState *ohci,
572 uint32_t addr, struct ohci_hcca *hcca)
573 {
574 cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
575 return 1;
576 }
577
578 /* Read/Write the contents of a TD from/to main memory. */
579 static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
580 uint8_t *buf, int len, int write)
581 {
582 uint32_t ptr;
583 uint32_t n;
584
585 ptr = td->cbp;
586 n = 0x1000 - (ptr & 0xfff);
587 if (n > len)
588 n = len;
589 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
590 if (n == len)
591 return;
592 ptr = td->be & ~0xfffu;
593 buf += n;
594 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
595 }
596
597 /* Read/Write the contents of an ISO TD from/to main memory. */
598 static void ohci_copy_iso_td(OHCIState *ohci,
599 uint32_t start_addr, uint32_t end_addr,
600 uint8_t *buf, int len, int write)
601 {
602 uint32_t ptr;
603 uint32_t n;
604
605 ptr = start_addr;
606 n = 0x1000 - (ptr & 0xfff);
607 if (n > len)
608 n = len;
609 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
610 if (n == len)
611 return;
612 ptr = end_addr & ~0xfffu;
613 buf += n;
614 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
615 }
616
617 static void ohci_process_lists(OHCIState *ohci, int completion);
618
619 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
620 {
621 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
622 #ifdef DEBUG_PACKET
623 DPRINTF("Async packet complete\n");
624 #endif
625 ohci->async_complete = 1;
626 ohci_process_lists(ohci, 1);
627 }
628
629 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
630
631 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
632 int completion)
633 {
634 int dir;
635 size_t len = 0;
636 #ifdef DEBUG_ISOCH
637 const char *str = NULL;
638 #endif
639 int pid;
640 int ret;
641 int i;
642 USBDevice *dev;
643 struct ohci_iso_td iso_td;
644 uint32_t addr;
645 uint16_t starting_frame;
646 int16_t relative_frame_number;
647 int frame_count;
648 uint32_t start_offset, next_offset, end_offset = 0;
649 uint32_t start_addr, end_addr;
650
651 addr = ed->head & OHCI_DPTR_MASK;
652
653 if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
654 printf("usb-ohci: ISO_TD read error at %x\n", addr);
655 return 0;
656 }
657
658 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
659 frame_count = OHCI_BM(iso_td.flags, TD_FC);
660 relative_frame_number = USUB(ohci->frame_number, starting_frame);
661
662 #ifdef DEBUG_ISOCH
663 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
664 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
665 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
666 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
667 "frame_number 0x%.8x starting_frame 0x%.8x\n"
668 "frame_count 0x%.8x relative %d\n"
669 "di 0x%.8x cc 0x%.8x\n",
670 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
671 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
672 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
673 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
674 ohci->frame_number, starting_frame,
675 frame_count, relative_frame_number,
676 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
677 #endif
678
679 if (relative_frame_number < 0) {
680 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
681 return 1;
682 } else if (relative_frame_number > frame_count) {
683 /* ISO TD expired - retire the TD to the Done Queue and continue with
684 the next ISO TD of the same ED */
685 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
686 frame_count);
687 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
688 ed->head &= ~OHCI_DPTR_MASK;
689 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
690 iso_td.next = ohci->done;
691 ohci->done = addr;
692 i = OHCI_BM(iso_td.flags, TD_DI);
693 if (i < ohci->done_count)
694 ohci->done_count = i;
695 ohci_put_iso_td(ohci, addr, &iso_td);
696 return 0;
697 }
698
699 dir = OHCI_BM(ed->flags, ED_D);
700 switch (dir) {
701 case OHCI_TD_DIR_IN:
702 #ifdef DEBUG_ISOCH
703 str = "in";
704 #endif
705 pid = USB_TOKEN_IN;
706 break;
707 case OHCI_TD_DIR_OUT:
708 #ifdef DEBUG_ISOCH
709 str = "out";
710 #endif
711 pid = USB_TOKEN_OUT;
712 break;
713 case OHCI_TD_DIR_SETUP:
714 #ifdef DEBUG_ISOCH
715 str = "setup";
716 #endif
717 pid = USB_TOKEN_SETUP;
718 break;
719 default:
720 printf("usb-ohci: Bad direction %d\n", dir);
721 return 1;
722 }
723
724 if (!iso_td.bp || !iso_td.be) {
725 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
726 return 1;
727 }
728
729 start_offset = iso_td.offset[relative_frame_number];
730 next_offset = iso_td.offset[relative_frame_number + 1];
731
732 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
733 ((relative_frame_number < frame_count) &&
734 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
735 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
736 start_offset, next_offset);
737 return 1;
738 }
739
740 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
741 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
742 start_offset, next_offset);
743 return 1;
744 }
745
746 if ((start_offset & 0x1000) == 0) {
747 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
748 (start_offset & OHCI_OFFSET_MASK);
749 } else {
750 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
751 (start_offset & OHCI_OFFSET_MASK);
752 }
753
754 if (relative_frame_number < frame_count) {
755 end_offset = next_offset - 1;
756 if ((end_offset & 0x1000) == 0) {
757 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
758 (end_offset & OHCI_OFFSET_MASK);
759 } else {
760 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
761 (end_offset & OHCI_OFFSET_MASK);
762 }
763 } else {
764 /* Last packet in the ISO TD */
765 end_addr = iso_td.be;
766 }
767
768 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
769 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
770 - (start_addr & OHCI_OFFSET_MASK);
771 } else {
772 len = end_addr - start_addr + 1;
773 }
774
775 if (len && dir != OHCI_TD_DIR_IN) {
776 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
777 }
778
779 if (completion) {
780 ret = ohci->usb_packet.result;
781 } else {
782 ret = USB_RET_NODEV;
783 for (i = 0; i < ohci->num_ports; i++) {
784 dev = ohci->rhport[i].port.dev;
785 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
786 continue;
787 usb_packet_setup(&ohci->usb_packet, pid,
788 OHCI_BM(ed->flags, ED_FA),
789 OHCI_BM(ed->flags, ED_EN));
790 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len);
791 ret = usb_handle_packet(dev, &ohci->usb_packet);
792 if (ret != USB_RET_NODEV)
793 break;
794 }
795
796 if (ret == USB_RET_ASYNC) {
797 return 1;
798 }
799 }
800
801 #ifdef DEBUG_ISOCH
802 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
803 start_offset, end_offset, start_addr, end_addr, str, len, ret);
804 #endif
805
806 /* Writeback */
807 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
808 /* IN transfer succeeded */
809 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
810 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
811 OHCI_CC_NOERROR);
812 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
813 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
814 /* OUT transfer succeeded */
815 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
816 OHCI_CC_NOERROR);
817 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
818 } else {
819 if (ret > (ssize_t) len) {
820 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
821 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
822 OHCI_CC_DATAOVERRUN);
823 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
824 len);
825 } else if (ret >= 0) {
826 printf("usb-ohci: DataUnderrun %d\n", ret);
827 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
828 OHCI_CC_DATAUNDERRUN);
829 } else {
830 switch (ret) {
831 case USB_RET_NODEV:
832 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
833 OHCI_CC_DEVICENOTRESPONDING);
834 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
835 0);
836 break;
837 case USB_RET_NAK:
838 case USB_RET_STALL:
839 printf("usb-ohci: got NAK/STALL %d\n", ret);
840 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
841 OHCI_CC_STALL);
842 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
843 0);
844 break;
845 default:
846 printf("usb-ohci: Bad device response %d\n", ret);
847 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
848 OHCI_CC_UNDEXPETEDPID);
849 break;
850 }
851 }
852 }
853
854 if (relative_frame_number == frame_count) {
855 /* Last data packet of ISO TD - retire the TD to the Done Queue */
856 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
857 ed->head &= ~OHCI_DPTR_MASK;
858 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
859 iso_td.next = ohci->done;
860 ohci->done = addr;
861 i = OHCI_BM(iso_td.flags, TD_DI);
862 if (i < ohci->done_count)
863 ohci->done_count = i;
864 }
865 ohci_put_iso_td(ohci, addr, &iso_td);
866 return 1;
867 }
868
869 /* Service a transport descriptor.
870 Returns nonzero to terminate processing of this endpoint. */
871
872 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
873 {
874 int dir;
875 size_t len = 0, pktlen = 0;
876 #ifdef DEBUG_PACKET
877 const char *str = NULL;
878 #endif
879 int pid;
880 int ret;
881 int i;
882 USBDevice *dev;
883 struct ohci_td td;
884 uint32_t addr;
885 int flag_r;
886 int completion;
887
888 addr = ed->head & OHCI_DPTR_MASK;
889 /* See if this TD has already been submitted to the device. */
890 completion = (addr == ohci->async_td);
891 if (completion && !ohci->async_complete) {
892 #ifdef DEBUG_PACKET
893 DPRINTF("Skipping async TD\n");
894 #endif
895 return 1;
896 }
897 if (!ohci_read_td(ohci, addr, &td)) {
898 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
899 return 0;
900 }
901
902 dir = OHCI_BM(ed->flags, ED_D);
903 switch (dir) {
904 case OHCI_TD_DIR_OUT:
905 case OHCI_TD_DIR_IN:
906 /* Same value. */
907 break;
908 default:
909 dir = OHCI_BM(td.flags, TD_DP);
910 break;
911 }
912
913 switch (dir) {
914 case OHCI_TD_DIR_IN:
915 #ifdef DEBUG_PACKET
916 str = "in";
917 #endif
918 pid = USB_TOKEN_IN;
919 break;
920 case OHCI_TD_DIR_OUT:
921 #ifdef DEBUG_PACKET
922 str = "out";
923 #endif
924 pid = USB_TOKEN_OUT;
925 break;
926 case OHCI_TD_DIR_SETUP:
927 #ifdef DEBUG_PACKET
928 str = "setup";
929 #endif
930 pid = USB_TOKEN_SETUP;
931 break;
932 default:
933 fprintf(stderr, "usb-ohci: Bad direction\n");
934 return 1;
935 }
936 if (td.cbp && td.be) {
937 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
938 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
939 } else {
940 len = (td.be - td.cbp) + 1;
941 }
942
943 pktlen = len;
944 if (len && dir != OHCI_TD_DIR_IN) {
945 /* The endpoint may not allow us to transfer it all now */
946 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT;
947 if (pktlen > len) {
948 pktlen = len;
949 }
950 if (!completion) {
951 ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 0);
952 }
953 }
954 }
955
956 flag_r = (td.flags & OHCI_TD_R) != 0;
957 #ifdef DEBUG_PACKET
958 DPRINTF(" TD @ 0x%.8x %" PRId64 " of %" PRId64
959 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
960 addr, (int64_t)pktlen, (int64_t)len, str, flag_r, td.cbp, td.be);
961
962 if (pktlen > 0 && dir != OHCI_TD_DIR_IN) {
963 DPRINTF(" data:");
964 for (i = 0; i < pktlen; i++) {
965 printf(" %.2x", ohci->usb_buf[i]);
966 }
967 DPRINTF("\n");
968 }
969 #endif
970 if (completion) {
971 ret = ohci->usb_packet.result;
972 ohci->async_td = 0;
973 ohci->async_complete = 0;
974 } else {
975 ret = USB_RET_NODEV;
976 for (i = 0; i < ohci->num_ports; i++) {
977 dev = ohci->rhport[i].port.dev;
978 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
979 continue;
980
981 if (ohci->async_td) {
982 /* ??? The hardware should allow one active packet per
983 endpoint. We only allow one active packet per controller.
984 This should be sufficient as long as devices respond in a
985 timely manner.
986 */
987 #ifdef DEBUG_PACKET
988 DPRINTF("Too many pending packets\n");
989 #endif
990 return 1;
991 }
992 usb_packet_setup(&ohci->usb_packet, pid,
993 OHCI_BM(ed->flags, ED_FA),
994 OHCI_BM(ed->flags, ED_EN));
995 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen);
996 ret = usb_handle_packet(dev, &ohci->usb_packet);
997 if (ret != USB_RET_NODEV)
998 break;
999 }
1000 #ifdef DEBUG_PACKET
1001 DPRINTF("ret=%d\n", ret);
1002 #endif
1003 if (ret == USB_RET_ASYNC) {
1004 ohci->async_td = addr;
1005 return 1;
1006 }
1007 }
1008 if (ret >= 0) {
1009 if (dir == OHCI_TD_DIR_IN) {
1010 ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
1011 #ifdef DEBUG_PACKET
1012 DPRINTF(" data:");
1013 for (i = 0; i < ret; i++)
1014 printf(" %.2x", ohci->usb_buf[i]);
1015 DPRINTF("\n");
1016 #endif
1017 } else {
1018 ret = pktlen;
1019 }
1020 }
1021
1022 /* Writeback */
1023 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
1024 /* Transmission succeeded. */
1025 if (ret == len) {
1026 td.cbp = 0;
1027 } else {
1028 if ((td.cbp & 0xfff) + ret > 0xfff) {
1029 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff);
1030 } else {
1031 td.cbp += ret;
1032 }
1033 }
1034 td.flags |= OHCI_TD_T1;
1035 td.flags ^= OHCI_TD_T0;
1036 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1037 OHCI_SET_BM(td.flags, TD_EC, 0);
1038
1039 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) {
1040 /* Partial packet transfer: TD not ready to retire yet */
1041 goto exit_no_retire;
1042 }
1043
1044 /* Setting ED_C is part of the TD retirement process */
1045 ed->head &= ~OHCI_ED_C;
1046 if (td.flags & OHCI_TD_T0)
1047 ed->head |= OHCI_ED_C;
1048 } else {
1049 if (ret >= 0) {
1050 DPRINTF("usb-ohci: Underrun\n");
1051 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1052 } else {
1053 switch (ret) {
1054 case USB_RET_NODEV:
1055 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1056 case USB_RET_NAK:
1057 DPRINTF("usb-ohci: got NAK\n");
1058 return 1;
1059 case USB_RET_STALL:
1060 DPRINTF("usb-ohci: got STALL\n");
1061 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1062 break;
1063 case USB_RET_BABBLE:
1064 DPRINTF("usb-ohci: got BABBLE\n");
1065 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1066 break;
1067 default:
1068 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1069 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1070 OHCI_SET_BM(td.flags, TD_EC, 3);
1071 break;
1072 }
1073 }
1074 ed->head |= OHCI_ED_H;
1075 }
1076
1077 /* Retire this TD */
1078 ed->head &= ~OHCI_DPTR_MASK;
1079 ed->head |= td.next & OHCI_DPTR_MASK;
1080 td.next = ohci->done;
1081 ohci->done = addr;
1082 i = OHCI_BM(td.flags, TD_DI);
1083 if (i < ohci->done_count)
1084 ohci->done_count = i;
1085 exit_no_retire:
1086 ohci_put_td(ohci, addr, &td);
1087 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1088 }
1089
1090 /* Service an endpoint list. Returns nonzero if active TD were found. */
1091 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1092 {
1093 struct ohci_ed ed;
1094 uint32_t next_ed;
1095 uint32_t cur;
1096 int active;
1097
1098 active = 0;
1099
1100 if (head == 0)
1101 return 0;
1102
1103 for (cur = head; cur; cur = next_ed) {
1104 if (!ohci_read_ed(ohci, cur, &ed)) {
1105 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1106 return 0;
1107 }
1108
1109 next_ed = ed.next & OHCI_DPTR_MASK;
1110
1111 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1112 uint32_t addr;
1113 /* Cancel pending packets for ED that have been paused. */
1114 addr = ed.head & OHCI_DPTR_MASK;
1115 if (ohci->async_td && addr == ohci->async_td) {
1116 usb_cancel_packet(&ohci->usb_packet);
1117 ohci->async_td = 0;
1118 }
1119 continue;
1120 }
1121
1122 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1123 #ifdef DEBUG_PACKET
1124 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1125 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1126 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1127 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1128 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1129 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1130 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1131 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1132 #endif
1133 active = 1;
1134
1135 if ((ed.flags & OHCI_ED_F) == 0) {
1136 if (ohci_service_td(ohci, &ed))
1137 break;
1138 } else {
1139 /* Handle isochronous endpoints */
1140 if (ohci_service_iso_td(ohci, &ed, completion))
1141 break;
1142 }
1143 }
1144
1145 ohci_put_ed(ohci, cur, &ed);
1146 }
1147
1148 return active;
1149 }
1150
1151 /* Generate a SOF event, and set a timer for EOF */
1152 static void ohci_sof(OHCIState *ohci)
1153 {
1154 ohci->sof_time = qemu_get_clock_ns(vm_clock);
1155 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1156 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1157 }
1158
1159 /* Process Control and Bulk lists. */
1160 static void ohci_process_lists(OHCIState *ohci, int completion)
1161 {
1162 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1163 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1164 DPRINTF("usb-ohci: head %x, cur %x\n",
1165 ohci->ctrl_head, ohci->ctrl_cur);
1166 }
1167 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1168 ohci->ctrl_cur = 0;
1169 ohci->status &= ~OHCI_STATUS_CLF;
1170 }
1171 }
1172
1173 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1174 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1175 ohci->bulk_cur = 0;
1176 ohci->status &= ~OHCI_STATUS_BLF;
1177 }
1178 }
1179 }
1180
1181 /* Do frame processing on frame boundary */
1182 static void ohci_frame_boundary(void *opaque)
1183 {
1184 OHCIState *ohci = opaque;
1185 struct ohci_hcca hcca;
1186
1187 ohci_read_hcca(ohci, ohci->hcca, &hcca);
1188
1189 /* Process all the lists at the end of the frame */
1190 if (ohci->ctl & OHCI_CTL_PLE) {
1191 int n;
1192
1193 n = ohci->frame_number & 0x1f;
1194 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1195 }
1196
1197 /* Cancel all pending packets if either of the lists has been disabled. */
1198 if (ohci->async_td &&
1199 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1200 usb_cancel_packet(&ohci->usb_packet);
1201 ohci->async_td = 0;
1202 }
1203 ohci->old_ctl = ohci->ctl;
1204 ohci_process_lists(ohci, 0);
1205
1206 /* Frame boundary, so do EOF stuf here */
1207 ohci->frt = ohci->fit;
1208
1209 /* Increment frame number and take care of endianness. */
1210 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1211 hcca.frame = cpu_to_le16(ohci->frame_number);
1212
1213 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1214 if (!ohci->done)
1215 abort();
1216 if (ohci->intr & ohci->intr_status)
1217 ohci->done |= 1;
1218 hcca.done = cpu_to_le32(ohci->done);
1219 ohci->done = 0;
1220 ohci->done_count = 7;
1221 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1222 }
1223
1224 if (ohci->done_count != 7 && ohci->done_count != 0)
1225 ohci->done_count--;
1226
1227 /* Do SOF stuff here */
1228 ohci_sof(ohci);
1229
1230 /* Writeback HCCA */
1231 ohci_put_hcca(ohci, ohci->hcca, &hcca);
1232 }
1233
1234 /* Start sending SOF tokens across the USB bus, lists are processed in
1235 * next frame
1236 */
1237 static int ohci_bus_start(OHCIState *ohci)
1238 {
1239 ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1240 ohci_frame_boundary,
1241 ohci);
1242
1243 if (ohci->eof_timer == NULL) {
1244 fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1245 /* TODO: Signal unrecoverable error */
1246 return 0;
1247 }
1248
1249 DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1250
1251 ohci_sof(ohci);
1252
1253 return 1;
1254 }
1255
1256 /* Stop sending SOF tokens on the bus */
1257 static void ohci_bus_stop(OHCIState *ohci)
1258 {
1259 if (ohci->eof_timer)
1260 qemu_del_timer(ohci->eof_timer);
1261 ohci->eof_timer = NULL;
1262 }
1263
1264 /* Sets a flag in a port status register but only set it if the port is
1265 * connected, if not set ConnectStatusChange flag. If flag is enabled
1266 * return 1.
1267 */
1268 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1269 {
1270 int ret = 1;
1271
1272 /* writing a 0 has no effect */
1273 if (val == 0)
1274 return 0;
1275
1276 /* If CurrentConnectStatus is cleared we set
1277 * ConnectStatusChange
1278 */
1279 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1280 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1281 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1282 /* TODO: CSC is a wakeup event */
1283 }
1284 return 0;
1285 }
1286
1287 if (ohci->rhport[i].ctrl & val)
1288 ret = 0;
1289
1290 /* set the bit */
1291 ohci->rhport[i].ctrl |= val;
1292
1293 return ret;
1294 }
1295
1296 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1297 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1298 {
1299 val &= OHCI_FMI_FI;
1300
1301 if (val != ohci->fi) {
1302 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1303 ohci->name, ohci->fi, ohci->fi);
1304 }
1305
1306 ohci->fi = val;
1307 }
1308
1309 static void ohci_port_power(OHCIState *ohci, int i, int p)
1310 {
1311 if (p) {
1312 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1313 } else {
1314 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1315 OHCI_PORT_CCS|
1316 OHCI_PORT_PSS|
1317 OHCI_PORT_PRS);
1318 }
1319 }
1320
1321 /* Set HcControlRegister */
1322 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1323 {
1324 uint32_t old_state;
1325 uint32_t new_state;
1326
1327 old_state = ohci->ctl & OHCI_CTL_HCFS;
1328 ohci->ctl = val;
1329 new_state = ohci->ctl & OHCI_CTL_HCFS;
1330
1331 /* no state change */
1332 if (old_state == new_state)
1333 return;
1334
1335 switch (new_state) {
1336 case OHCI_USB_OPERATIONAL:
1337 ohci_bus_start(ohci);
1338 break;
1339 case OHCI_USB_SUSPEND:
1340 ohci_bus_stop(ohci);
1341 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1342 break;
1343 case OHCI_USB_RESUME:
1344 DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1345 break;
1346 case OHCI_USB_RESET:
1347 ohci_reset(ohci);
1348 DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1349 break;
1350 }
1351 }
1352
1353 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1354 {
1355 uint16_t fr;
1356 int64_t tks;
1357
1358 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1359 return (ohci->frt << 31);
1360
1361 /* Being in USB operational state guarnatees sof_time was
1362 * set already.
1363 */
1364 tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1365
1366 /* avoid muldiv if possible */
1367 if (tks >= usb_frame_time)
1368 return (ohci->frt << 31);
1369
1370 tks = muldiv64(1, tks, usb_bit_time);
1371 fr = (uint16_t)(ohci->fi - tks);
1372
1373 return (ohci->frt << 31) | fr;
1374 }
1375
1376
1377 /* Set root hub status */
1378 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1379 {
1380 uint32_t old_state;
1381
1382 old_state = ohci->rhstatus;
1383
1384 /* write 1 to clear OCIC */
1385 if (val & OHCI_RHS_OCIC)
1386 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1387
1388 if (val & OHCI_RHS_LPS) {
1389 int i;
1390
1391 for (i = 0; i < ohci->num_ports; i++)
1392 ohci_port_power(ohci, i, 0);
1393 DPRINTF("usb-ohci: powered down all ports\n");
1394 }
1395
1396 if (val & OHCI_RHS_LPSC) {
1397 int i;
1398
1399 for (i = 0; i < ohci->num_ports; i++)
1400 ohci_port_power(ohci, i, 1);
1401 DPRINTF("usb-ohci: powered up all ports\n");
1402 }
1403
1404 if (val & OHCI_RHS_DRWE)
1405 ohci->rhstatus |= OHCI_RHS_DRWE;
1406
1407 if (val & OHCI_RHS_CRWE)
1408 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1409
1410 if (old_state != ohci->rhstatus)
1411 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1412 }
1413
1414 /* Set root hub port status */
1415 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1416 {
1417 uint32_t old_state;
1418 OHCIPort *port;
1419
1420 port = &ohci->rhport[portnum];
1421 old_state = port->ctrl;
1422
1423 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1424 if (val & OHCI_PORT_WTC)
1425 port->ctrl &= ~(val & OHCI_PORT_WTC);
1426
1427 if (val & OHCI_PORT_CCS)
1428 port->ctrl &= ~OHCI_PORT_PES;
1429
1430 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1431
1432 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1433 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1434 }
1435
1436 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1437 DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1438 usb_send_msg(port->port.dev, USB_MSG_RESET);
1439 port->ctrl &= ~OHCI_PORT_PRS;
1440 /* ??? Should this also set OHCI_PORT_PESC. */
1441 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1442 }
1443
1444 /* Invert order here to ensure in ambiguous case, device is
1445 * powered up...
1446 */
1447 if (val & OHCI_PORT_LSDA)
1448 ohci_port_power(ohci, portnum, 0);
1449 if (val & OHCI_PORT_PPS)
1450 ohci_port_power(ohci, portnum, 1);
1451
1452 if (old_state != port->ctrl)
1453 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1454
1455 return;
1456 }
1457
1458 static uint64_t ohci_mem_read(void *opaque,
1459 target_phys_addr_t addr,
1460 unsigned size)
1461 {
1462 OHCIState *ohci = opaque;
1463 uint32_t retval;
1464
1465 /* Only aligned reads are allowed on OHCI */
1466 if (addr & 3) {
1467 fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1468 return 0xffffffff;
1469 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1470 /* HcRhPortStatus */
1471 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1472 } else {
1473 switch (addr >> 2) {
1474 case 0: /* HcRevision */
1475 retval = 0x10;
1476 break;
1477
1478 case 1: /* HcControl */
1479 retval = ohci->ctl;
1480 break;
1481
1482 case 2: /* HcCommandStatus */
1483 retval = ohci->status;
1484 break;
1485
1486 case 3: /* HcInterruptStatus */
1487 retval = ohci->intr_status;
1488 break;
1489
1490 case 4: /* HcInterruptEnable */
1491 case 5: /* HcInterruptDisable */
1492 retval = ohci->intr;
1493 break;
1494
1495 case 6: /* HcHCCA */
1496 retval = ohci->hcca;
1497 break;
1498
1499 case 7: /* HcPeriodCurrentED */
1500 retval = ohci->per_cur;
1501 break;
1502
1503 case 8: /* HcControlHeadED */
1504 retval = ohci->ctrl_head;
1505 break;
1506
1507 case 9: /* HcControlCurrentED */
1508 retval = ohci->ctrl_cur;
1509 break;
1510
1511 case 10: /* HcBulkHeadED */
1512 retval = ohci->bulk_head;
1513 break;
1514
1515 case 11: /* HcBulkCurrentED */
1516 retval = ohci->bulk_cur;
1517 break;
1518
1519 case 12: /* HcDoneHead */
1520 retval = ohci->done;
1521 break;
1522
1523 case 13: /* HcFmInterretval */
1524 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1525 break;
1526
1527 case 14: /* HcFmRemaining */
1528 retval = ohci_get_frame_remaining(ohci);
1529 break;
1530
1531 case 15: /* HcFmNumber */
1532 retval = ohci->frame_number;
1533 break;
1534
1535 case 16: /* HcPeriodicStart */
1536 retval = ohci->pstart;
1537 break;
1538
1539 case 17: /* HcLSThreshold */
1540 retval = ohci->lst;
1541 break;
1542
1543 case 18: /* HcRhDescriptorA */
1544 retval = ohci->rhdesc_a;
1545 break;
1546
1547 case 19: /* HcRhDescriptorB */
1548 retval = ohci->rhdesc_b;
1549 break;
1550
1551 case 20: /* HcRhStatus */
1552 retval = ohci->rhstatus;
1553 break;
1554
1555 /* PXA27x specific registers */
1556 case 24: /* HcStatus */
1557 retval = ohci->hstatus & ohci->hmask;
1558 break;
1559
1560 case 25: /* HcHReset */
1561 retval = ohci->hreset;
1562 break;
1563
1564 case 26: /* HcHInterruptEnable */
1565 retval = ohci->hmask;
1566 break;
1567
1568 case 27: /* HcHInterruptTest */
1569 retval = ohci->htest;
1570 break;
1571
1572 default:
1573 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1574 retval = 0xffffffff;
1575 }
1576 }
1577
1578 return retval;
1579 }
1580
1581 static void ohci_mem_write(void *opaque,
1582 target_phys_addr_t addr,
1583 uint64_t val,
1584 unsigned size)
1585 {
1586 OHCIState *ohci = opaque;
1587
1588 /* Only aligned reads are allowed on OHCI */
1589 if (addr & 3) {
1590 fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1591 return;
1592 }
1593
1594 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1595 /* HcRhPortStatus */
1596 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1597 return;
1598 }
1599
1600 switch (addr >> 2) {
1601 case 1: /* HcControl */
1602 ohci_set_ctl(ohci, val);
1603 break;
1604
1605 case 2: /* HcCommandStatus */
1606 /* SOC is read-only */
1607 val = (val & ~OHCI_STATUS_SOC);
1608
1609 /* Bits written as '0' remain unchanged in the register */
1610 ohci->status |= val;
1611
1612 if (ohci->status & OHCI_STATUS_HCR)
1613 ohci_reset(ohci);
1614 break;
1615
1616 case 3: /* HcInterruptStatus */
1617 ohci->intr_status &= ~val;
1618 ohci_intr_update(ohci);
1619 break;
1620
1621 case 4: /* HcInterruptEnable */
1622 ohci->intr |= val;
1623 ohci_intr_update(ohci);
1624 break;
1625
1626 case 5: /* HcInterruptDisable */
1627 ohci->intr &= ~val;
1628 ohci_intr_update(ohci);
1629 break;
1630
1631 case 6: /* HcHCCA */
1632 ohci->hcca = val & OHCI_HCCA_MASK;
1633 break;
1634
1635 case 7: /* HcPeriodCurrentED */
1636 /* Ignore writes to this read-only register, Linux does them */
1637 break;
1638
1639 case 8: /* HcControlHeadED */
1640 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1641 break;
1642
1643 case 9: /* HcControlCurrentED */
1644 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1645 break;
1646
1647 case 10: /* HcBulkHeadED */
1648 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1649 break;
1650
1651 case 11: /* HcBulkCurrentED */
1652 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1653 break;
1654
1655 case 13: /* HcFmInterval */
1656 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1657 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1658 ohci_set_frame_interval(ohci, val);
1659 break;
1660
1661 case 15: /* HcFmNumber */
1662 break;
1663
1664 case 16: /* HcPeriodicStart */
1665 ohci->pstart = val & 0xffff;
1666 break;
1667
1668 case 17: /* HcLSThreshold */
1669 ohci->lst = val & 0xffff;
1670 break;
1671
1672 case 18: /* HcRhDescriptorA */
1673 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1674 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1675 break;
1676
1677 case 19: /* HcRhDescriptorB */
1678 break;
1679
1680 case 20: /* HcRhStatus */
1681 ohci_set_hub_status(ohci, val);
1682 break;
1683
1684 /* PXA27x specific registers */
1685 case 24: /* HcStatus */
1686 ohci->hstatus &= ~(val & ohci->hmask);
1687
1688 case 25: /* HcHReset */
1689 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1690 if (val & OHCI_HRESET_FSBIR)
1691 ohci_reset(ohci);
1692 break;
1693
1694 case 26: /* HcHInterruptEnable */
1695 ohci->hmask = val;
1696 break;
1697
1698 case 27: /* HcHInterruptTest */
1699 ohci->htest = val;
1700 break;
1701
1702 default:
1703 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1704 break;
1705 }
1706 }
1707
1708 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev)
1709 {
1710 if (ohci->async_td &&
1711 ohci->usb_packet.owner != NULL &&
1712 ohci->usb_packet.owner->dev == dev) {
1713 usb_cancel_packet(&ohci->usb_packet);
1714 ohci->async_td = 0;
1715 }
1716 }
1717
1718 static const MemoryRegionOps ohci_mem_ops = {
1719 .read = ohci_mem_read,
1720 .write = ohci_mem_write,
1721 .endianness = DEVICE_LITTLE_ENDIAN,
1722 };
1723
1724 static USBPortOps ohci_port_ops = {
1725 .attach = ohci_attach,
1726 .detach = ohci_detach,
1727 .child_detach = ohci_child_detach,
1728 .wakeup = ohci_wakeup,
1729 .complete = ohci_async_complete_packet,
1730 };
1731
1732 static USBBusOps ohci_bus_ops = {
1733 };
1734
1735 static int usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1736 int num_ports, uint32_t localmem_base,
1737 char *masterbus, uint32_t firstport)
1738 {
1739 int i;
1740
1741 if (usb_frame_time == 0) {
1742 #ifdef OHCI_TIME_WARP
1743 usb_frame_time = get_ticks_per_sec();
1744 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1745 #else
1746 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1747 if (get_ticks_per_sec() >= USB_HZ) {
1748 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1749 } else {
1750 usb_bit_time = 1;
1751 }
1752 #endif
1753 DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1754 usb_frame_time, usb_bit_time);
1755 }
1756
1757 ohci->num_ports = num_ports;
1758 if (masterbus) {
1759 USBPort *ports[OHCI_MAX_PORTS];
1760 for(i = 0; i < num_ports; i++) {
1761 ports[i] = &ohci->rhport[i].port;
1762 }
1763 if (usb_register_companion(masterbus, ports, num_ports,
1764 firstport, ohci, &ohci_port_ops,
1765 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1766 return -1;
1767 }
1768 } else {
1769 usb_bus_new(&ohci->bus, &ohci_bus_ops, dev);
1770 for (i = 0; i < num_ports; i++) {
1771 usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1772 ohci, i, &ohci_port_ops,
1773 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1774 }
1775 }
1776
1777 memory_region_init_io(&ohci->mem, &ohci_mem_ops, ohci, "ohci", 256);
1778 ohci->localmem_base = localmem_base;
1779
1780 ohci->name = object_get_typename(OBJECT(dev));
1781 usb_packet_init(&ohci->usb_packet);
1782
1783 ohci->async_td = 0;
1784 qemu_register_reset(ohci_reset, ohci);
1785
1786 return 0;
1787 }
1788
1789 typedef struct {
1790 PCIDevice pci_dev;
1791 OHCIState state;
1792 char *masterbus;
1793 uint32_t num_ports;
1794 uint32_t firstport;
1795 } OHCIPCIState;
1796
1797 static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1798 {
1799 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1800
1801 ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1802 ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
1803
1804 if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0,
1805 ohci->masterbus, ohci->firstport) != 0) {
1806 return -1;
1807 }
1808 ohci->state.irq = ohci->pci_dev.irq[0];
1809
1810 /* TODO: avoid cast below by using dev */
1811 pci_register_bar(&ohci->pci_dev, 0, 0, &ohci->state.mem);
1812 return 0;
1813 }
1814
1815 void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1816 {
1817 pci_create_simple(bus, devfn, "pci-ohci");
1818 }
1819
1820 typedef struct {
1821 SysBusDevice busdev;
1822 OHCIState ohci;
1823 uint32_t num_ports;
1824 target_phys_addr_t dma_offset;
1825 } OHCISysBusState;
1826
1827 static int ohci_init_pxa(SysBusDevice *dev)
1828 {
1829 OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1830
1831 /* Cannot fail as we pass NULL for masterbus */
1832 usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0);
1833 sysbus_init_irq(dev, &s->ohci.irq);
1834 sysbus_init_mmio(dev, &s->ohci.mem);
1835
1836 return 0;
1837 }
1838
1839 static Property ohci_pci_properties[] = {
1840 DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
1841 DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
1842 DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
1843 DEFINE_PROP_END_OF_LIST(),
1844 };
1845
1846 static void ohci_pci_class_init(ObjectClass *klass, void *data)
1847 {
1848 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1849
1850 k->init = usb_ohci_initfn_pci;
1851 k->vendor_id = PCI_VENDOR_ID_APPLE;
1852 k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB;
1853 k->class_id = PCI_CLASS_SERIAL_USB;
1854 }
1855
1856 static DeviceInfo ohci_pci_info = {
1857 .name = "pci-ohci",
1858 .desc = "Apple USB Controller",
1859 .size = sizeof(OHCIPCIState),
1860 .props = ohci_pci_properties,
1861 .class_init = ohci_pci_class_init,
1862 };
1863
1864 static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
1865 {
1866 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1867
1868 sbc->init = ohci_init_pxa;
1869 }
1870
1871 static DeviceInfo ohci_sysbus_info = {
1872 .name = "sysbus-ohci",
1873 .desc = "OHCI USB Controller",
1874 .size = sizeof(OHCISysBusState),
1875 .class_init = ohci_sysbus_class_init,
1876 .props = (Property[]) {
1877 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1878 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1879 DEFINE_PROP_END_OF_LIST(),
1880 }
1881 };
1882
1883 static void ohci_register(void)
1884 {
1885 pci_qdev_register(&ohci_pci_info);
1886 sysbus_register_withprop(&ohci_sysbus_info);
1887 }
1888 device_init(ohci_register);