linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / usb-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw.h"
22 #include "qemu-timer.h"
23 #include "usb.h"
24 #include "pci.h"
25 #include "qdev-addr.h"
26 #include "msi.h"
27
28 //#define DEBUG_XHCI
29 //#define DEBUG_DATA
30
31 #ifdef DEBUG_XHCI
32 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
33 #else
34 #define DPRINTF(...) do {} while (0)
35 #endif
36 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
38
39 #define MAXSLOTS 8
40 #define MAXINTRS 1
41
42 #define USB2_PORTS 4
43 #define USB3_PORTS 4
44
45 #define MAXPORTS (USB2_PORTS+USB3_PORTS)
46
47 #define TD_QUEUE 24
48 #define BG_XFERS 8
49 #define BG_PKTS 8
50
51 /* Very pessimistic, let's hope it's enough for all cases */
52 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
53 /* Do not deliver ER Full events. NEC's driver does some things not bound
54 * to the specs when it gets them */
55 #define ER_FULL_HACK
56
57 #define LEN_CAP 0x40
58 #define OFF_OPER LEN_CAP
59 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
60 #define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
61 #define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
62 #define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
63 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
64
65 /* must be power of 2 */
66 #define LEN_REGS 0x2000
67
68 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
69 # error Increase LEN_REGS
70 #endif
71
72 #if MAXINTRS > 1
73 # error TODO: only one interrupter supported
74 #endif
75
76 /* bit definitions */
77 #define USBCMD_RS (1<<0)
78 #define USBCMD_HCRST (1<<1)
79 #define USBCMD_INTE (1<<2)
80 #define USBCMD_HSEE (1<<3)
81 #define USBCMD_LHCRST (1<<7)
82 #define USBCMD_CSS (1<<8)
83 #define USBCMD_CRS (1<<9)
84 #define USBCMD_EWE (1<<10)
85 #define USBCMD_EU3S (1<<11)
86
87 #define USBSTS_HCH (1<<0)
88 #define USBSTS_HSE (1<<2)
89 #define USBSTS_EINT (1<<3)
90 #define USBSTS_PCD (1<<4)
91 #define USBSTS_SSS (1<<8)
92 #define USBSTS_RSS (1<<9)
93 #define USBSTS_SRE (1<<10)
94 #define USBSTS_CNR (1<<11)
95 #define USBSTS_HCE (1<<12)
96
97
98 #define PORTSC_CCS (1<<0)
99 #define PORTSC_PED (1<<1)
100 #define PORTSC_OCA (1<<3)
101 #define PORTSC_PR (1<<4)
102 #define PORTSC_PLS_SHIFT 5
103 #define PORTSC_PLS_MASK 0xf
104 #define PORTSC_PP (1<<9)
105 #define PORTSC_SPEED_SHIFT 10
106 #define PORTSC_SPEED_MASK 0xf
107 #define PORTSC_SPEED_FULL (1<<10)
108 #define PORTSC_SPEED_LOW (2<<10)
109 #define PORTSC_SPEED_HIGH (3<<10)
110 #define PORTSC_SPEED_SUPER (4<<10)
111 #define PORTSC_PIC_SHIFT 14
112 #define PORTSC_PIC_MASK 0x3
113 #define PORTSC_LWS (1<<16)
114 #define PORTSC_CSC (1<<17)
115 #define PORTSC_PEC (1<<18)
116 #define PORTSC_WRC (1<<19)
117 #define PORTSC_OCC (1<<20)
118 #define PORTSC_PRC (1<<21)
119 #define PORTSC_PLC (1<<22)
120 #define PORTSC_CEC (1<<23)
121 #define PORTSC_CAS (1<<24)
122 #define PORTSC_WCE (1<<25)
123 #define PORTSC_WDE (1<<26)
124 #define PORTSC_WOE (1<<27)
125 #define PORTSC_DR (1<<30)
126 #define PORTSC_WPR (1<<31)
127
128 #define CRCR_RCS (1<<0)
129 #define CRCR_CS (1<<1)
130 #define CRCR_CA (1<<2)
131 #define CRCR_CRR (1<<3)
132
133 #define IMAN_IP (1<<0)
134 #define IMAN_IE (1<<1)
135
136 #define ERDP_EHB (1<<3)
137
138 #define TRB_SIZE 16
139 typedef struct XHCITRB {
140 uint64_t parameter;
141 uint32_t status;
142 uint32_t control;
143 target_phys_addr_t addr;
144 bool ccs;
145 } XHCITRB;
146
147
148 typedef enum TRBType {
149 TRB_RESERVED = 0,
150 TR_NORMAL,
151 TR_SETUP,
152 TR_DATA,
153 TR_STATUS,
154 TR_ISOCH,
155 TR_LINK,
156 TR_EVDATA,
157 TR_NOOP,
158 CR_ENABLE_SLOT,
159 CR_DISABLE_SLOT,
160 CR_ADDRESS_DEVICE,
161 CR_CONFIGURE_ENDPOINT,
162 CR_EVALUATE_CONTEXT,
163 CR_RESET_ENDPOINT,
164 CR_STOP_ENDPOINT,
165 CR_SET_TR_DEQUEUE,
166 CR_RESET_DEVICE,
167 CR_FORCE_EVENT,
168 CR_NEGOTIATE_BW,
169 CR_SET_LATENCY_TOLERANCE,
170 CR_GET_PORT_BANDWIDTH,
171 CR_FORCE_HEADER,
172 CR_NOOP,
173 ER_TRANSFER = 32,
174 ER_COMMAND_COMPLETE,
175 ER_PORT_STATUS_CHANGE,
176 ER_BANDWIDTH_REQUEST,
177 ER_DOORBELL,
178 ER_HOST_CONTROLLER,
179 ER_DEVICE_NOTIFICATION,
180 ER_MFINDEX_WRAP,
181 /* vendor specific bits */
182 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
183 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
184 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
185 } TRBType;
186
187 #define CR_LINK TR_LINK
188
189 typedef enum TRBCCode {
190 CC_INVALID = 0,
191 CC_SUCCESS,
192 CC_DATA_BUFFER_ERROR,
193 CC_BABBLE_DETECTED,
194 CC_USB_TRANSACTION_ERROR,
195 CC_TRB_ERROR,
196 CC_STALL_ERROR,
197 CC_RESOURCE_ERROR,
198 CC_BANDWIDTH_ERROR,
199 CC_NO_SLOTS_ERROR,
200 CC_INVALID_STREAM_TYPE_ERROR,
201 CC_SLOT_NOT_ENABLED_ERROR,
202 CC_EP_NOT_ENABLED_ERROR,
203 CC_SHORT_PACKET,
204 CC_RING_UNDERRUN,
205 CC_RING_OVERRUN,
206 CC_VF_ER_FULL,
207 CC_PARAMETER_ERROR,
208 CC_BANDWIDTH_OVERRUN,
209 CC_CONTEXT_STATE_ERROR,
210 CC_NO_PING_RESPONSE_ERROR,
211 CC_EVENT_RING_FULL_ERROR,
212 CC_INCOMPATIBLE_DEVICE_ERROR,
213 CC_MISSED_SERVICE_ERROR,
214 CC_COMMAND_RING_STOPPED,
215 CC_COMMAND_ABORTED,
216 CC_STOPPED,
217 CC_STOPPED_LENGTH_INVALID,
218 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
219 CC_ISOCH_BUFFER_OVERRUN = 31,
220 CC_EVENT_LOST_ERROR,
221 CC_UNDEFINED_ERROR,
222 CC_INVALID_STREAM_ID_ERROR,
223 CC_SECONDARY_BANDWIDTH_ERROR,
224 CC_SPLIT_TRANSACTION_ERROR
225 } TRBCCode;
226
227 #define TRB_C (1<<0)
228 #define TRB_TYPE_SHIFT 10
229 #define TRB_TYPE_MASK 0x3f
230 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
231
232 #define TRB_EV_ED (1<<2)
233
234 #define TRB_TR_ENT (1<<1)
235 #define TRB_TR_ISP (1<<2)
236 #define TRB_TR_NS (1<<3)
237 #define TRB_TR_CH (1<<4)
238 #define TRB_TR_IOC (1<<5)
239 #define TRB_TR_IDT (1<<6)
240 #define TRB_TR_TBC_SHIFT 7
241 #define TRB_TR_TBC_MASK 0x3
242 #define TRB_TR_BEI (1<<9)
243 #define TRB_TR_TLBPC_SHIFT 16
244 #define TRB_TR_TLBPC_MASK 0xf
245 #define TRB_TR_FRAMEID_SHIFT 20
246 #define TRB_TR_FRAMEID_MASK 0x7ff
247 #define TRB_TR_SIA (1<<31)
248
249 #define TRB_TR_DIR (1<<16)
250
251 #define TRB_CR_SLOTID_SHIFT 24
252 #define TRB_CR_SLOTID_MASK 0xff
253 #define TRB_CR_EPID_SHIFT 16
254 #define TRB_CR_EPID_MASK 0x1f
255
256 #define TRB_CR_BSR (1<<9)
257 #define TRB_CR_DC (1<<9)
258
259 #define TRB_LK_TC (1<<1)
260
261 #define EP_TYPE_MASK 0x7
262 #define EP_TYPE_SHIFT 3
263
264 #define EP_STATE_MASK 0x7
265 #define EP_DISABLED (0<<0)
266 #define EP_RUNNING (1<<0)
267 #define EP_HALTED (2<<0)
268 #define EP_STOPPED (3<<0)
269 #define EP_ERROR (4<<0)
270
271 #define SLOT_STATE_MASK 0x1f
272 #define SLOT_STATE_SHIFT 27
273 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
274 #define SLOT_ENABLED 0
275 #define SLOT_DEFAULT 1
276 #define SLOT_ADDRESSED 2
277 #define SLOT_CONFIGURED 3
278
279 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
280 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
281
282 typedef enum EPType {
283 ET_INVALID = 0,
284 ET_ISO_OUT,
285 ET_BULK_OUT,
286 ET_INTR_OUT,
287 ET_CONTROL,
288 ET_ISO_IN,
289 ET_BULK_IN,
290 ET_INTR_IN,
291 } EPType;
292
293 typedef struct XHCIRing {
294 target_phys_addr_t base;
295 target_phys_addr_t dequeue;
296 bool ccs;
297 } XHCIRing;
298
299 typedef struct XHCIPort {
300 USBPort port;
301 uint32_t portsc;
302 } XHCIPort;
303
304 struct XHCIState;
305 typedef struct XHCIState XHCIState;
306
307 typedef struct XHCITransfer {
308 XHCIState *xhci;
309 USBPacket packet;
310 bool running;
311 bool cancelled;
312 bool complete;
313 bool backgrounded;
314 unsigned int iso_pkts;
315 unsigned int slotid;
316 unsigned int epid;
317 bool in_xfer;
318 bool iso_xfer;
319 bool bg_xfer;
320
321 unsigned int trb_count;
322 unsigned int trb_alloced;
323 XHCITRB *trbs;
324
325 unsigned int data_length;
326 unsigned int data_alloced;
327 uint8_t *data;
328
329 TRBCCode status;
330
331 unsigned int pkts;
332 unsigned int pktsize;
333 unsigned int cur_pkt;
334 } XHCITransfer;
335
336 typedef struct XHCIEPContext {
337 XHCIRing ring;
338 unsigned int next_xfer;
339 unsigned int comp_xfer;
340 XHCITransfer transfers[TD_QUEUE];
341 bool bg_running;
342 bool bg_updating;
343 unsigned int next_bg;
344 XHCITransfer bg_transfers[BG_XFERS];
345 EPType type;
346 target_phys_addr_t pctx;
347 unsigned int max_psize;
348 bool has_bg;
349 uint32_t state;
350 } XHCIEPContext;
351
352 typedef struct XHCISlot {
353 bool enabled;
354 target_phys_addr_t ctx;
355 unsigned int port;
356 unsigned int devaddr;
357 XHCIEPContext * eps[31];
358 } XHCISlot;
359
360 typedef struct XHCIEvent {
361 TRBType type;
362 TRBCCode ccode;
363 uint64_t ptr;
364 uint32_t length;
365 uint32_t flags;
366 uint8_t slotid;
367 uint8_t epid;
368 } XHCIEvent;
369
370 struct XHCIState {
371 PCIDevice pci_dev;
372 USBBus bus;
373 qemu_irq irq;
374 MemoryRegion mem;
375 const char *name;
376 uint32_t msi;
377 unsigned int devaddr;
378
379 /* Operational Registers */
380 uint32_t usbcmd;
381 uint32_t usbsts;
382 uint32_t dnctrl;
383 uint32_t crcr_low;
384 uint32_t crcr_high;
385 uint32_t dcbaap_low;
386 uint32_t dcbaap_high;
387 uint32_t config;
388
389 XHCIPort ports[MAXPORTS];
390 XHCISlot slots[MAXSLOTS];
391
392 /* Runtime Registers */
393 uint32_t mfindex;
394 /* note: we only support one interrupter */
395 uint32_t iman;
396 uint32_t imod;
397 uint32_t erstsz;
398 uint32_t erstba_low;
399 uint32_t erstba_high;
400 uint32_t erdp_low;
401 uint32_t erdp_high;
402
403 target_phys_addr_t er_start;
404 uint32_t er_size;
405 bool er_pcs;
406 unsigned int er_ep_idx;
407 bool er_full;
408
409 XHCIEvent ev_buffer[EV_QUEUE];
410 unsigned int ev_buffer_put;
411 unsigned int ev_buffer_get;
412
413 XHCIRing cmd_ring;
414 };
415
416 typedef struct XHCIEvRingSeg {
417 uint32_t addr_low;
418 uint32_t addr_high;
419 uint32_t size;
420 uint32_t rsvd;
421 } XHCIEvRingSeg;
422
423 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
424 unsigned int epid);
425
426 static inline target_phys_addr_t xhci_addr64(uint32_t low, uint32_t high)
427 {
428 #if TARGET_PHYS_ADDR_BITS > 32
429 return low | ((target_phys_addr_t)high << 32);
430 #else
431 return low;
432 #endif
433 }
434
435 static inline target_phys_addr_t xhci_mask64(uint64_t addr)
436 {
437 #if TARGET_PHYS_ADDR_BITS > 32
438 return addr;
439 #else
440 return addr & 0xffffffff;
441 #endif
442 }
443
444 static void xhci_irq_update(XHCIState *xhci)
445 {
446 int level = 0;
447
448 if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
449 xhci->usbcmd && USBCMD_INTE) {
450 level = 1;
451 }
452
453 DPRINTF("xhci_irq_update(): %d\n", level);
454
455 if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
456 if (level) {
457 DPRINTF("xhci_irq_update(): MSI signal\n");
458 msi_notify(&xhci->pci_dev, 0);
459 }
460 } else {
461 qemu_set_irq(xhci->irq, level);
462 }
463 }
464
465 static inline int xhci_running(XHCIState *xhci)
466 {
467 return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
468 }
469
470 static void xhci_die(XHCIState *xhci)
471 {
472 xhci->usbsts |= USBSTS_HCE;
473 fprintf(stderr, "xhci: asserted controller error\n");
474 }
475
476 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event)
477 {
478 XHCITRB ev_trb;
479 target_phys_addr_t addr;
480
481 ev_trb.parameter = cpu_to_le64(event->ptr);
482 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
483 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
484 event->flags | (event->type << TRB_TYPE_SHIFT);
485 if (xhci->er_pcs) {
486 ev_trb.control |= TRB_C;
487 }
488 ev_trb.control = cpu_to_le32(ev_trb.control);
489
490 DPRINTF("xhci_write_event(): [%d] %016"PRIx64" %08x %08x\n",
491 xhci->er_ep_idx, ev_trb.parameter, ev_trb.status, ev_trb.control);
492
493 addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx;
494 cpu_physical_memory_write(addr, (uint8_t *) &ev_trb, TRB_SIZE);
495
496 xhci->er_ep_idx++;
497 if (xhci->er_ep_idx >= xhci->er_size) {
498 xhci->er_ep_idx = 0;
499 xhci->er_pcs = !xhci->er_pcs;
500 }
501 }
502
503 static void xhci_events_update(XHCIState *xhci)
504 {
505 target_phys_addr_t erdp;
506 unsigned int dp_idx;
507 bool do_irq = 0;
508
509 if (xhci->usbsts & USBSTS_HCH) {
510 return;
511 }
512
513 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
514 if (erdp < xhci->er_start ||
515 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
516 fprintf(stderr, "xhci: ERDP out of bounds: "TARGET_FMT_plx"\n", erdp);
517 fprintf(stderr, "xhci: ER at "TARGET_FMT_plx" len %d\n",
518 xhci->er_start, xhci->er_size);
519 xhci_die(xhci);
520 return;
521 }
522 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
523 assert(dp_idx < xhci->er_size);
524
525 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
526 * deadlocks when the ER is full. Hack it by holding off events until
527 * the driver decides to free at least half of the ring */
528 if (xhci->er_full) {
529 int er_free = dp_idx - xhci->er_ep_idx;
530 if (er_free <= 0) {
531 er_free += xhci->er_size;
532 }
533 if (er_free < (xhci->er_size/2)) {
534 DPRINTF("xhci_events_update(): event ring still "
535 "more than half full (hack)\n");
536 return;
537 }
538 }
539
540 while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
541 assert(xhci->er_full);
542 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) {
543 DPRINTF("xhci_events_update(): event ring full again\n");
544 #ifndef ER_FULL_HACK
545 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
546 xhci_write_event(xhci, &full);
547 #endif
548 do_irq = 1;
549 break;
550 }
551 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get];
552 xhci_write_event(xhci, event);
553 xhci->ev_buffer_get++;
554 do_irq = 1;
555 if (xhci->ev_buffer_get == EV_QUEUE) {
556 xhci->ev_buffer_get = 0;
557 }
558 }
559
560 if (do_irq) {
561 xhci->erdp_low |= ERDP_EHB;
562 xhci->iman |= IMAN_IP;
563 xhci->usbsts |= USBSTS_EINT;
564 xhci_irq_update(xhci);
565 }
566
567 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
568 DPRINTF("xhci_events_update(): event ring no longer full\n");
569 xhci->er_full = 0;
570 }
571 return;
572 }
573
574 static void xhci_event(XHCIState *xhci, XHCIEvent *event)
575 {
576 target_phys_addr_t erdp;
577 unsigned int dp_idx;
578
579 if (xhci->er_full) {
580 DPRINTF("xhci_event(): ER full, queueing\n");
581 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
582 fprintf(stderr, "xhci: event queue full, dropping event!\n");
583 return;
584 }
585 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
586 if (xhci->ev_buffer_put == EV_QUEUE) {
587 xhci->ev_buffer_put = 0;
588 }
589 return;
590 }
591
592 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
593 if (erdp < xhci->er_start ||
594 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
595 fprintf(stderr, "xhci: ERDP out of bounds: "TARGET_FMT_plx"\n", erdp);
596 fprintf(stderr, "xhci: ER at "TARGET_FMT_plx" len %d\n",
597 xhci->er_start, xhci->er_size);
598 xhci_die(xhci);
599 return;
600 }
601
602 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
603 assert(dp_idx < xhci->er_size);
604
605 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) {
606 DPRINTF("xhci_event(): ER full, queueing\n");
607 #ifndef ER_FULL_HACK
608 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
609 xhci_write_event(xhci, &full);
610 #endif
611 xhci->er_full = 1;
612 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
613 fprintf(stderr, "xhci: event queue full, dropping event!\n");
614 return;
615 }
616 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
617 if (xhci->ev_buffer_put == EV_QUEUE) {
618 xhci->ev_buffer_put = 0;
619 }
620 } else {
621 xhci_write_event(xhci, event);
622 }
623
624 xhci->erdp_low |= ERDP_EHB;
625 xhci->iman |= IMAN_IP;
626 xhci->usbsts |= USBSTS_EINT;
627
628 xhci_irq_update(xhci);
629 }
630
631 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
632 target_phys_addr_t base)
633 {
634 ring->base = base;
635 ring->dequeue = base;
636 ring->ccs = 1;
637 }
638
639 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
640 target_phys_addr_t *addr)
641 {
642 while (1) {
643 TRBType type;
644 cpu_physical_memory_read(ring->dequeue, (uint8_t *) trb, TRB_SIZE);
645 trb->addr = ring->dequeue;
646 trb->ccs = ring->ccs;
647 le64_to_cpus(&trb->parameter);
648 le32_to_cpus(&trb->status);
649 le32_to_cpus(&trb->control);
650
651 DPRINTF("xhci: TRB fetched [" TARGET_FMT_plx "]: "
652 "%016" PRIx64 " %08x %08x\n",
653 ring->dequeue, trb->parameter, trb->status, trb->control);
654
655 if ((trb->control & TRB_C) != ring->ccs) {
656 return 0;
657 }
658
659 type = TRB_TYPE(*trb);
660
661 if (type != TR_LINK) {
662 if (addr) {
663 *addr = ring->dequeue;
664 }
665 ring->dequeue += TRB_SIZE;
666 return type;
667 } else {
668 ring->dequeue = xhci_mask64(trb->parameter);
669 if (trb->control & TRB_LK_TC) {
670 ring->ccs = !ring->ccs;
671 }
672 }
673 }
674 }
675
676 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
677 {
678 XHCITRB trb;
679 int length = 0;
680 target_phys_addr_t dequeue = ring->dequeue;
681 bool ccs = ring->ccs;
682 /* hack to bundle together the two/three TDs that make a setup transfer */
683 bool control_td_set = 0;
684
685 while (1) {
686 TRBType type;
687 cpu_physical_memory_read(dequeue, (uint8_t *) &trb, TRB_SIZE);
688 le64_to_cpus(&trb.parameter);
689 le32_to_cpus(&trb.status);
690 le32_to_cpus(&trb.control);
691
692 DPRINTF("xhci: TRB peeked [" TARGET_FMT_plx "]: "
693 "%016" PRIx64 " %08x %08x\n",
694 dequeue, trb.parameter, trb.status, trb.control);
695
696 if ((trb.control & TRB_C) != ccs) {
697 return -length;
698 }
699
700 type = TRB_TYPE(trb);
701
702 if (type == TR_LINK) {
703 dequeue = xhci_mask64(trb.parameter);
704 if (trb.control & TRB_LK_TC) {
705 ccs = !ccs;
706 }
707 continue;
708 }
709
710 length += 1;
711 dequeue += TRB_SIZE;
712
713 if (type == TR_SETUP) {
714 control_td_set = 1;
715 } else if (type == TR_STATUS) {
716 control_td_set = 0;
717 }
718
719 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
720 return length;
721 }
722 }
723 }
724
725 static void xhci_er_reset(XHCIState *xhci)
726 {
727 XHCIEvRingSeg seg;
728
729 /* cache the (sole) event ring segment location */
730 if (xhci->erstsz != 1) {
731 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
732 xhci_die(xhci);
733 return;
734 }
735 target_phys_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high);
736 cpu_physical_memory_read(erstba, (uint8_t *) &seg, sizeof(seg));
737 le32_to_cpus(&seg.addr_low);
738 le32_to_cpus(&seg.addr_high);
739 le32_to_cpus(&seg.size);
740 if (seg.size < 16 || seg.size > 4096) {
741 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
742 xhci_die(xhci);
743 return;
744 }
745 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
746 xhci->er_size = seg.size;
747
748 xhci->er_ep_idx = 0;
749 xhci->er_pcs = 1;
750 xhci->er_full = 0;
751
752 DPRINTF("xhci: event ring:" TARGET_FMT_plx " [%d]\n",
753 xhci->er_start, xhci->er_size);
754 }
755
756 static void xhci_run(XHCIState *xhci)
757 {
758 DPRINTF("xhci_run()\n");
759
760 xhci->usbsts &= ~USBSTS_HCH;
761 }
762
763 static void xhci_stop(XHCIState *xhci)
764 {
765 DPRINTF("xhci_stop()\n");
766 xhci->usbsts |= USBSTS_HCH;
767 xhci->crcr_low &= ~CRCR_CRR;
768 }
769
770 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
771 uint32_t state)
772 {
773 uint32_t ctx[5];
774 if (epctx->state == state) {
775 return;
776 }
777
778 cpu_physical_memory_read(epctx->pctx, (uint8_t *) ctx, sizeof(ctx));
779 ctx[0] &= ~EP_STATE_MASK;
780 ctx[0] |= state;
781 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
782 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
783 DPRINTF("xhci: set epctx: " TARGET_FMT_plx " state=%d dequeue=%08x%08x\n",
784 epctx->pctx, state, ctx[3], ctx[2]);
785 cpu_physical_memory_write(epctx->pctx, (uint8_t *) ctx, sizeof(ctx));
786 epctx->state = state;
787 }
788
789 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
790 unsigned int epid, target_phys_addr_t pctx,
791 uint32_t *ctx)
792 {
793 XHCISlot *slot;
794 XHCIEPContext *epctx;
795 target_phys_addr_t dequeue;
796 int i;
797
798 assert(slotid >= 1 && slotid <= MAXSLOTS);
799 assert(epid >= 1 && epid <= 31);
800
801 DPRINTF("xhci_enable_ep(%d, %d)\n", slotid, epid);
802
803 slot = &xhci->slots[slotid-1];
804 if (slot->eps[epid-1]) {
805 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
806 return CC_TRB_ERROR;
807 }
808
809 epctx = g_malloc(sizeof(XHCIEPContext));
810 memset(epctx, 0, sizeof(XHCIEPContext));
811
812 slot->eps[epid-1] = epctx;
813
814 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
815 xhci_ring_init(xhci, &epctx->ring, dequeue);
816 epctx->ring.ccs = ctx[2] & 1;
817
818 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
819 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
820 epctx->pctx = pctx;
821 epctx->max_psize = ctx[1]>>16;
822 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
823 epctx->has_bg = false;
824 if (epctx->type == ET_ISO_IN) {
825 epctx->has_bg = true;
826 }
827 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
828 epid/2, epid%2, epctx->max_psize);
829 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
830 usb_packet_init(&epctx->transfers[i].packet);
831 }
832
833 epctx->state = EP_RUNNING;
834 ctx[0] &= ~EP_STATE_MASK;
835 ctx[0] |= EP_RUNNING;
836
837 return CC_SUCCESS;
838 }
839
840 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
841 unsigned int epid)
842 {
843 XHCISlot *slot;
844 XHCIEPContext *epctx;
845 int i, xferi, killed = 0;
846 assert(slotid >= 1 && slotid <= MAXSLOTS);
847 assert(epid >= 1 && epid <= 31);
848
849 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
850
851 slot = &xhci->slots[slotid-1];
852
853 if (!slot->eps[epid-1]) {
854 return 0;
855 }
856
857 epctx = slot->eps[epid-1];
858
859 xferi = epctx->next_xfer;
860 for (i = 0; i < TD_QUEUE; i++) {
861 XHCITransfer *t = &epctx->transfers[xferi];
862 if (t->running) {
863 t->cancelled = 1;
864 /* libusb_cancel_transfer(t->usbxfer) */
865 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
866 killed++;
867 }
868 if (t->backgrounded) {
869 t->backgrounded = 0;
870 }
871 if (t->trbs) {
872 g_free(t->trbs);
873 }
874 if (t->data) {
875 g_free(t->data);
876 }
877
878 t->trbs = NULL;
879 t->data = NULL;
880 t->trb_count = t->trb_alloced = 0;
881 t->data_length = t->data_alloced = 0;
882 xferi = (xferi + 1) % TD_QUEUE;
883 }
884 if (epctx->has_bg) {
885 xferi = epctx->next_bg;
886 for (i = 0; i < BG_XFERS; i++) {
887 XHCITransfer *t = &epctx->bg_transfers[xferi];
888 if (t->running) {
889 t->cancelled = 1;
890 /* libusb_cancel_transfer(t->usbxfer); */
891 DPRINTF("xhci: cancelling bg transfer %d, waiting for it to complete...\n", i);
892 killed++;
893 }
894 if (t->data) {
895 g_free(t->data);
896 }
897
898 t->data = NULL;
899 xferi = (xferi + 1) % BG_XFERS;
900 }
901 }
902 return killed;
903 }
904
905 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
906 unsigned int epid)
907 {
908 XHCISlot *slot;
909 XHCIEPContext *epctx;
910
911 assert(slotid >= 1 && slotid <= MAXSLOTS);
912 assert(epid >= 1 && epid <= 31);
913
914 DPRINTF("xhci_disable_ep(%d, %d)\n", slotid, epid);
915
916 slot = &xhci->slots[slotid-1];
917
918 if (!slot->eps[epid-1]) {
919 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
920 return CC_SUCCESS;
921 }
922
923 xhci_ep_nuke_xfers(xhci, slotid, epid);
924
925 epctx = slot->eps[epid-1];
926
927 xhci_set_ep_state(xhci, epctx, EP_DISABLED);
928
929 g_free(epctx);
930 slot->eps[epid-1] = NULL;
931
932 return CC_SUCCESS;
933 }
934
935 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
936 unsigned int epid)
937 {
938 XHCISlot *slot;
939 XHCIEPContext *epctx;
940
941 DPRINTF("xhci_stop_ep(%d, %d)\n", slotid, epid);
942
943 assert(slotid >= 1 && slotid <= MAXSLOTS);
944
945 if (epid < 1 || epid > 31) {
946 fprintf(stderr, "xhci: bad ep %d\n", epid);
947 return CC_TRB_ERROR;
948 }
949
950 slot = &xhci->slots[slotid-1];
951
952 if (!slot->eps[epid-1]) {
953 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
954 return CC_EP_NOT_ENABLED_ERROR;
955 }
956
957 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
958 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
959 "data might be lost\n");
960 }
961
962 epctx = slot->eps[epid-1];
963
964 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
965
966 return CC_SUCCESS;
967 }
968
969 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
970 unsigned int epid)
971 {
972 XHCISlot *slot;
973 XHCIEPContext *epctx;
974 USBDevice *dev;
975
976 assert(slotid >= 1 && slotid <= MAXSLOTS);
977
978 DPRINTF("xhci_reset_ep(%d, %d)\n", slotid, epid);
979
980 if (epid < 1 || epid > 31) {
981 fprintf(stderr, "xhci: bad ep %d\n", epid);
982 return CC_TRB_ERROR;
983 }
984
985 slot = &xhci->slots[slotid-1];
986
987 if (!slot->eps[epid-1]) {
988 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
989 return CC_EP_NOT_ENABLED_ERROR;
990 }
991
992 epctx = slot->eps[epid-1];
993
994 if (epctx->state != EP_HALTED) {
995 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
996 epid, epctx->state);
997 return CC_CONTEXT_STATE_ERROR;
998 }
999
1000 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1001 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1002 "data might be lost\n");
1003 }
1004
1005 uint8_t ep = epid>>1;
1006
1007 if (epid & 1) {
1008 ep |= 0x80;
1009 }
1010
1011 dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev;
1012 if (!dev) {
1013 return CC_USB_TRANSACTION_ERROR;
1014 }
1015
1016 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1017
1018 return CC_SUCCESS;
1019 }
1020
1021 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1022 unsigned int epid, uint64_t pdequeue)
1023 {
1024 XHCISlot *slot;
1025 XHCIEPContext *epctx;
1026 target_phys_addr_t dequeue;
1027
1028 assert(slotid >= 1 && slotid <= MAXSLOTS);
1029
1030 if (epid < 1 || epid > 31) {
1031 fprintf(stderr, "xhci: bad ep %d\n", epid);
1032 return CC_TRB_ERROR;
1033 }
1034
1035 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64")\n", slotid, epid, pdequeue);
1036 dequeue = xhci_mask64(pdequeue);
1037
1038 slot = &xhci->slots[slotid-1];
1039
1040 if (!slot->eps[epid-1]) {
1041 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1042 return CC_EP_NOT_ENABLED_ERROR;
1043 }
1044
1045 epctx = slot->eps[epid-1];
1046
1047
1048 if (epctx->state != EP_STOPPED) {
1049 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1050 return CC_CONTEXT_STATE_ERROR;
1051 }
1052
1053 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1054 epctx->ring.ccs = dequeue & 1;
1055
1056 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1057
1058 return CC_SUCCESS;
1059 }
1060
1061 static int xhci_xfer_data(XHCITransfer *xfer, uint8_t *data,
1062 unsigned int length, bool in_xfer, bool out_xfer,
1063 bool report)
1064 {
1065 int i;
1066 uint32_t edtla = 0;
1067 unsigned int transferred = 0;
1068 unsigned int left = length;
1069 bool reported = 0;
1070 bool shortpkt = 0;
1071 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1072 XHCIState *xhci = xfer->xhci;
1073
1074 DPRINTF("xhci_xfer_data(len=%d, in_xfer=%d, out_xfer=%d, report=%d)\n",
1075 length, in_xfer, out_xfer, report);
1076
1077 assert(!(in_xfer && out_xfer));
1078
1079 for (i = 0; i < xfer->trb_count; i++) {
1080 XHCITRB *trb = &xfer->trbs[i];
1081 target_phys_addr_t addr;
1082 unsigned int chunk = 0;
1083
1084 switch (TRB_TYPE(*trb)) {
1085 case TR_DATA:
1086 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1087 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
1088 xhci_die(xhci);
1089 return transferred;
1090 }
1091 /* fallthrough */
1092 case TR_NORMAL:
1093 case TR_ISOCH:
1094 addr = xhci_mask64(trb->parameter);
1095 chunk = trb->status & 0x1ffff;
1096 if (chunk > left) {
1097 chunk = left;
1098 shortpkt = 1;
1099 }
1100 if (in_xfer || out_xfer) {
1101 if (trb->control & TRB_TR_IDT) {
1102 uint64_t idata;
1103 if (chunk > 8 || in_xfer) {
1104 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1105 xhci_die(xhci);
1106 return transferred;
1107 }
1108 idata = le64_to_cpu(trb->parameter);
1109 memcpy(data, &idata, chunk);
1110 } else {
1111 DPRINTF("xhci_xfer_data: r/w(%d) %d bytes at "
1112 TARGET_FMT_plx "\n", in_xfer, chunk, addr);
1113 if (in_xfer) {
1114 cpu_physical_memory_write(addr, data, chunk);
1115 } else {
1116 cpu_physical_memory_read(addr, data, chunk);
1117 }
1118 #ifdef DEBUG_DATA
1119 unsigned int count = chunk;
1120 int i;
1121 if (count > 16) {
1122 count = 16;
1123 }
1124 DPRINTF(" ::");
1125 for (i = 0; i < count; i++) {
1126 DPRINTF(" %02x", data[i]);
1127 }
1128 DPRINTF("\n");
1129 #endif
1130 }
1131 }
1132 left -= chunk;
1133 data += chunk;
1134 edtla += chunk;
1135 transferred += chunk;
1136 break;
1137 case TR_STATUS:
1138 reported = 0;
1139 shortpkt = 0;
1140 break;
1141 }
1142
1143 if (report && !reported && (trb->control & TRB_TR_IOC ||
1144 (shortpkt && (trb->control & TRB_TR_ISP)))) {
1145 event.slotid = xfer->slotid;
1146 event.epid = xfer->epid;
1147 event.length = (trb->status & 0x1ffff) - chunk;
1148 event.flags = 0;
1149 event.ptr = trb->addr;
1150 if (xfer->status == CC_SUCCESS) {
1151 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1152 } else {
1153 event.ccode = xfer->status;
1154 }
1155 if (TRB_TYPE(*trb) == TR_EVDATA) {
1156 event.ptr = trb->parameter;
1157 event.flags |= TRB_EV_ED;
1158 event.length = edtla & 0xffffff;
1159 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1160 edtla = 0;
1161 }
1162 xhci_event(xhci, &event);
1163 reported = 1;
1164 }
1165 }
1166 return transferred;
1167 }
1168
1169 static void xhci_stall_ep(XHCITransfer *xfer)
1170 {
1171 XHCIState *xhci = xfer->xhci;
1172 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1173 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1174
1175 epctx->ring.dequeue = xfer->trbs[0].addr;
1176 epctx->ring.ccs = xfer->trbs[0].ccs;
1177 xhci_set_ep_state(xhci, epctx, EP_HALTED);
1178 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
1179 DPRINTF("xhci: will continue at "TARGET_FMT_plx"\n", epctx->ring.dequeue);
1180 }
1181
1182 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1183 XHCIEPContext *epctx);
1184
1185 static void xhci_bg_update(XHCIState *xhci, XHCIEPContext *epctx)
1186 {
1187 if (epctx->bg_updating) {
1188 return;
1189 }
1190 DPRINTF("xhci_bg_update(%p, %p)\n", xhci, epctx);
1191 assert(epctx->has_bg);
1192 DPRINTF("xhci: fg=%d bg=%d\n", epctx->comp_xfer, epctx->next_bg);
1193 epctx->bg_updating = 1;
1194 while (epctx->transfers[epctx->comp_xfer].backgrounded &&
1195 epctx->bg_transfers[epctx->next_bg].complete) {
1196 XHCITransfer *fg = &epctx->transfers[epctx->comp_xfer];
1197 XHCITransfer *bg = &epctx->bg_transfers[epctx->next_bg];
1198 #if 0
1199 DPRINTF("xhci: completing fg %d from bg %d.%d (stat: %d)\n",
1200 epctx->comp_xfer, epctx->next_bg, bg->cur_pkt,
1201 bg->usbxfer->iso_packet_desc[bg->cur_pkt].status
1202 );
1203 #endif
1204 assert(epctx->type == ET_ISO_IN);
1205 assert(bg->iso_xfer);
1206 assert(bg->in_xfer);
1207 uint8_t *p = bg->data + bg->cur_pkt * bg->pktsize;
1208 #if 0
1209 int len = bg->usbxfer->iso_packet_desc[bg->cur_pkt].actual_length;
1210 fg->status = libusb_to_ccode(bg->usbxfer->iso_packet_desc[bg->cur_pkt].status);
1211 #else
1212 int len = 0;
1213 FIXME();
1214 #endif
1215 fg->complete = 1;
1216 fg->backgrounded = 0;
1217
1218 if (fg->status == CC_STALL_ERROR) {
1219 xhci_stall_ep(fg);
1220 }
1221
1222 xhci_xfer_data(fg, p, len, 1, 0, 1);
1223
1224 epctx->comp_xfer++;
1225 if (epctx->comp_xfer == TD_QUEUE) {
1226 epctx->comp_xfer = 0;
1227 }
1228 DPRINTF("next fg xfer: %d\n", epctx->comp_xfer);
1229 bg->cur_pkt++;
1230 if (bg->cur_pkt == bg->pkts) {
1231 bg->complete = 0;
1232 if (xhci_submit(xhci, bg, epctx) < 0) {
1233 fprintf(stderr, "xhci: bg resubmit failed\n");
1234 }
1235 epctx->next_bg++;
1236 if (epctx->next_bg == BG_XFERS) {
1237 epctx->next_bg = 0;
1238 }
1239 DPRINTF("next bg xfer: %d\n", epctx->next_bg);
1240
1241 xhci_kick_ep(xhci, fg->slotid, fg->epid);
1242 }
1243 }
1244 epctx->bg_updating = 0;
1245 }
1246
1247 #if 0
1248 static void xhci_xfer_cb(struct libusb_transfer *transfer)
1249 {
1250 XHCIState *xhci;
1251 XHCITransfer *xfer;
1252
1253 xfer = (XHCITransfer *)transfer->user_data;
1254 xhci = xfer->xhci;
1255
1256 DPRINTF("xhci_xfer_cb(slot=%d, ep=%d, status=%d)\n", xfer->slotid,
1257 xfer->epid, transfer->status);
1258
1259 assert(xfer->slotid >= 1 && xfer->slotid <= MAXSLOTS);
1260 assert(xfer->epid >= 1 && xfer->epid <= 31);
1261
1262 if (xfer->cancelled) {
1263 DPRINTF("xhci: transfer cancelled, not reporting anything\n");
1264 xfer->running = 0;
1265 return;
1266 }
1267
1268 XHCIEPContext *epctx;
1269 XHCISlot *slot;
1270 slot = &xhci->slots[xfer->slotid-1];
1271 assert(slot->eps[xfer->epid-1]);
1272 epctx = slot->eps[xfer->epid-1];
1273
1274 if (xfer->bg_xfer) {
1275 DPRINTF("xhci: background transfer, updating\n");
1276 xfer->complete = 1;
1277 xfer->running = 0;
1278 xhci_bg_update(xhci, epctx);
1279 return;
1280 }
1281
1282 if (xfer->iso_xfer) {
1283 transfer->status = transfer->iso_packet_desc[0].status;
1284 transfer->actual_length = transfer->iso_packet_desc[0].actual_length;
1285 }
1286
1287 xfer->status = libusb_to_ccode(transfer->status);
1288
1289 xfer->complete = 1;
1290 xfer->running = 0;
1291
1292 if (transfer->status == LIBUSB_TRANSFER_STALL)
1293 xhci_stall_ep(xhci, epctx, xfer);
1294
1295 DPRINTF("xhci: transfer actual length = %d\n", transfer->actual_length);
1296
1297 if (xfer->in_xfer) {
1298 if (xfer->epid == 1) {
1299 xhci_xfer_data(xhci, xfer, xfer->data + 8,
1300 transfer->actual_length, 1, 0, 1);
1301 } else {
1302 xhci_xfer_data(xhci, xfer, xfer->data,
1303 transfer->actual_length, 1, 0, 1);
1304 }
1305 } else {
1306 xhci_xfer_data(xhci, xfer, NULL, transfer->actual_length, 0, 0, 1);
1307 }
1308
1309 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1310 }
1311
1312 static int xhci_hle_control(XHCIState *xhci, XHCITransfer *xfer,
1313 uint8_t bmRequestType, uint8_t bRequest,
1314 uint16_t wValue, uint16_t wIndex, uint16_t wLength)
1315 {
1316 uint16_t type_req = (bmRequestType << 8) | bRequest;
1317
1318 switch (type_req) {
1319 case 0x0000 | USB_REQ_SET_CONFIGURATION:
1320 DPRINTF("xhci: HLE switch configuration\n");
1321 return xhci_switch_config(xhci, xfer->slotid, wValue) == 0;
1322 case 0x0100 | USB_REQ_SET_INTERFACE:
1323 DPRINTF("xhci: HLE set interface altsetting\n");
1324 return xhci_set_iface_alt(xhci, xfer->slotid, wIndex, wValue) == 0;
1325 case 0x0200 | USB_REQ_CLEAR_FEATURE:
1326 if (wValue == 0) { // endpoint halt
1327 DPRINTF("xhci: HLE clear halt\n");
1328 return xhci_clear_halt(xhci, xfer->slotid, wIndex);
1329 }
1330 case 0x0000 | USB_REQ_SET_ADDRESS:
1331 fprintf(stderr, "xhci: warn: illegal SET_ADDRESS request\n");
1332 return 0;
1333 default:
1334 return 0;
1335 }
1336 }
1337 #endif
1338
1339 static int xhci_setup_packet(XHCITransfer *xfer, XHCIPort *port, int ep)
1340 {
1341 usb_packet_setup(&xfer->packet,
1342 xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT,
1343 xfer->xhci->slots[xfer->slotid-1].devaddr,
1344 ep & 0x7f);
1345 usb_packet_addbuf(&xfer->packet, xfer->data, xfer->data_length);
1346 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1347 xfer->packet.pid, xfer->packet.devaddr, xfer->packet.devep);
1348 return 0;
1349 }
1350
1351 static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1352 {
1353 if (ret == USB_RET_ASYNC) {
1354 xfer->running = 1;
1355 xfer->complete = 0;
1356 xfer->cancelled = 0;
1357 return 0;
1358 } else {
1359 xfer->running = 0;
1360 xfer->complete = 1;
1361 }
1362
1363 if (ret >= 0) {
1364 xfer->status = CC_SUCCESS;
1365 xhci_xfer_data(xfer, xfer->data, ret, xfer->in_xfer, 0, 1);
1366 return 0;
1367 }
1368
1369 /* error */
1370 switch (ret) {
1371 case USB_RET_NODEV:
1372 xfer->status = CC_USB_TRANSACTION_ERROR;
1373 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1374 xhci_stall_ep(xfer);
1375 break;
1376 case USB_RET_STALL:
1377 xfer->status = CC_STALL_ERROR;
1378 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1379 xhci_stall_ep(xfer);
1380 break;
1381 default:
1382 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1383 FIXME();
1384 }
1385 return 0;
1386 }
1387
1388 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1389 {
1390 XHCITRB *trb_setup, *trb_status;
1391 uint8_t bmRequestType, bRequest;
1392 uint16_t wValue, wLength, wIndex;
1393 XHCIPort *port;
1394 USBDevice *dev;
1395 int ret;
1396
1397 DPRINTF("xhci_fire_ctl_transfer(slot=%d)\n", xfer->slotid);
1398
1399 trb_setup = &xfer->trbs[0];
1400 trb_status = &xfer->trbs[xfer->trb_count-1];
1401
1402 /* at most one Event Data TRB allowed after STATUS */
1403 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1404 trb_status--;
1405 }
1406
1407 /* do some sanity checks */
1408 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1409 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1410 TRB_TYPE(*trb_setup));
1411 return -1;
1412 }
1413 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1414 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1415 TRB_TYPE(*trb_status));
1416 return -1;
1417 }
1418 if (!(trb_setup->control & TRB_TR_IDT)) {
1419 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1420 return -1;
1421 }
1422 if ((trb_setup->status & 0x1ffff) != 8) {
1423 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1424 (trb_setup->status & 0x1ffff));
1425 return -1;
1426 }
1427
1428 bmRequestType = trb_setup->parameter;
1429 bRequest = trb_setup->parameter >> 8;
1430 wValue = trb_setup->parameter >> 16;
1431 wIndex = trb_setup->parameter >> 32;
1432 wLength = trb_setup->parameter >> 48;
1433
1434 if (xfer->data && xfer->data_alloced < wLength) {
1435 xfer->data_alloced = 0;
1436 g_free(xfer->data);
1437 xfer->data = NULL;
1438 }
1439 if (!xfer->data) {
1440 DPRINTF("xhci: alloc %d bytes data\n", wLength);
1441 xfer->data = g_malloc(wLength+1);
1442 xfer->data_alloced = wLength;
1443 }
1444 xfer->data_length = wLength;
1445
1446 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1447 dev = port->port.dev;
1448 if (!dev) {
1449 fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1450 xhci->slots[xfer->slotid-1].port);
1451 return -1;
1452 }
1453
1454 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1455 xfer->iso_xfer = false;
1456
1457 xhci_setup_packet(xfer, port, 0);
1458 if (!xfer->in_xfer) {
1459 xhci_xfer_data(xfer, xfer->data, wLength, 0, 1, 0);
1460 }
1461 ret = usb_device_handle_control(dev, &xfer->packet,
1462 (bmRequestType << 8) | bRequest,
1463 wValue, wIndex, wLength, xfer->data);
1464
1465 xhci_complete_packet(xfer, ret);
1466 if (!xfer->running) {
1467 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1468 }
1469 return 0;
1470 }
1471
1472 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1473 {
1474 XHCIPort *port;
1475 USBDevice *dev;
1476 int ret;
1477
1478 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1479 uint8_t ep = xfer->epid>>1;
1480
1481 xfer->in_xfer = epctx->type>>2;
1482 if (xfer->in_xfer) {
1483 ep |= 0x80;
1484 }
1485
1486 if (xfer->data && xfer->data_alloced < xfer->data_length) {
1487 xfer->data_alloced = 0;
1488 g_free(xfer->data);
1489 xfer->data = NULL;
1490 }
1491 if (!xfer->data && xfer->data_length) {
1492 DPRINTF("xhci: alloc %d bytes data\n", xfer->data_length);
1493 xfer->data = g_malloc(xfer->data_length);
1494 xfer->data_alloced = xfer->data_length;
1495 }
1496 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1497 if (!xfer->bg_xfer) {
1498 xfer->pkts = 1;
1499 }
1500 } else {
1501 xfer->pkts = 0;
1502 }
1503
1504 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1505 dev = port->port.dev;
1506 if (!dev) {
1507 fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1508 xhci->slots[xfer->slotid-1].port);
1509 return -1;
1510 }
1511
1512 xhci_setup_packet(xfer, port, ep);
1513
1514 switch(epctx->type) {
1515 case ET_INTR_OUT:
1516 case ET_INTR_IN:
1517 case ET_BULK_OUT:
1518 case ET_BULK_IN:
1519 break;
1520 case ET_ISO_OUT:
1521 case ET_ISO_IN:
1522 FIXME();
1523 break;
1524 default:
1525 fprintf(stderr, "xhci: unknown or unhandled EP type %d (ep %02x)\n",
1526 epctx->type, ep);
1527 return -1;
1528 }
1529
1530 if (!xfer->in_xfer) {
1531 xhci_xfer_data(xfer, xfer->data, xfer->data_length, 0, 1, 0);
1532 }
1533 ret = usb_handle_packet(dev, &xfer->packet);
1534
1535 xhci_complete_packet(xfer, ret);
1536 if (!xfer->running) {
1537 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1538 }
1539 return 0;
1540 }
1541
1542 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1543 {
1544 int i;
1545 unsigned int length = 0;
1546 XHCITRB *trb;
1547
1548 DPRINTF("xhci_fire_transfer(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1549
1550 for (i = 0; i < xfer->trb_count; i++) {
1551 trb = &xfer->trbs[i];
1552 if (TRB_TYPE(*trb) == TR_NORMAL || TRB_TYPE(*trb) == TR_ISOCH) {
1553 length += trb->status & 0x1ffff;
1554 }
1555 }
1556 DPRINTF("xhci: total TD length=%d\n", length);
1557
1558 if (!epctx->has_bg) {
1559 xfer->data_length = length;
1560 xfer->backgrounded = 0;
1561 return xhci_submit(xhci, xfer, epctx);
1562 } else {
1563 if (!epctx->bg_running) {
1564 for (i = 0; i < BG_XFERS; i++) {
1565 XHCITransfer *t = &epctx->bg_transfers[i];
1566 t->xhci = xhci;
1567 t->epid = xfer->epid;
1568 t->slotid = xfer->slotid;
1569 t->pkts = BG_PKTS;
1570 t->pktsize = epctx->max_psize;
1571 t->data_length = t->pkts * t->pktsize;
1572 t->bg_xfer = 1;
1573 if (xhci_submit(xhci, t, epctx) < 0) {
1574 fprintf(stderr, "xhci: bg submit failed\n");
1575 return -1;
1576 }
1577 }
1578 epctx->bg_running = 1;
1579 }
1580 xfer->backgrounded = 1;
1581 xhci_bg_update(xhci, epctx);
1582 return 0;
1583 }
1584 }
1585
1586 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1587 {
1588 XHCIEPContext *epctx;
1589 int length;
1590 int i;
1591
1592 assert(slotid >= 1 && slotid <= MAXSLOTS);
1593 assert(epid >= 1 && epid <= 31);
1594 DPRINTF("xhci_kick_ep(%d, %d)\n", slotid, epid);
1595
1596 if (!xhci->slots[slotid-1].enabled) {
1597 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1598 return;
1599 }
1600 epctx = xhci->slots[slotid-1].eps[epid-1];
1601 if (!epctx) {
1602 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1603 epid, slotid);
1604 return;
1605 }
1606
1607 if (epctx->state == EP_HALTED) {
1608 DPRINTF("xhci: ep halted, not running schedule\n");
1609 return;
1610 }
1611
1612 xhci_set_ep_state(xhci, epctx, EP_RUNNING);
1613
1614 while (1) {
1615 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
1616 if (xfer->running || xfer->backgrounded) {
1617 DPRINTF("xhci: ep is busy\n");
1618 break;
1619 }
1620 length = xhci_ring_chain_length(xhci, &epctx->ring);
1621 if (length < 0) {
1622 DPRINTF("xhci: incomplete TD (%d TRBs)\n", -length);
1623 break;
1624 } else if (length == 0) {
1625 break;
1626 }
1627 DPRINTF("xhci: fetching %d-TRB TD\n", length);
1628 if (xfer->trbs && xfer->trb_alloced < length) {
1629 xfer->trb_count = 0;
1630 xfer->trb_alloced = 0;
1631 g_free(xfer->trbs);
1632 xfer->trbs = NULL;
1633 }
1634 if (!xfer->trbs) {
1635 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1636 xfer->trb_alloced = length;
1637 }
1638 xfer->trb_count = length;
1639
1640 for (i = 0; i < length; i++) {
1641 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
1642 }
1643 xfer->xhci = xhci;
1644 xfer->epid = epid;
1645 xfer->slotid = slotid;
1646
1647 if (epid == 1) {
1648 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1649 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1650 } else {
1651 fprintf(stderr, "xhci: error firing CTL transfer\n");
1652 }
1653 } else {
1654 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1655 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1656 } else {
1657 fprintf(stderr, "xhci: error firing data transfer\n");
1658 }
1659 }
1660
1661 /*
1662 * Qemu usb can't handle multiple in-flight xfers.
1663 * Also xfers might be finished here already,
1664 * possibly with an error. Stop here for now.
1665 */
1666 break;
1667 }
1668 }
1669
1670 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1671 {
1672 assert(slotid >= 1 && slotid <= MAXSLOTS);
1673 DPRINTF("xhci_enable_slot(%d)\n", slotid);
1674 xhci->slots[slotid-1].enabled = 1;
1675 xhci->slots[slotid-1].port = 0;
1676 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1677
1678 return CC_SUCCESS;
1679 }
1680
1681 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1682 {
1683 int i;
1684
1685 assert(slotid >= 1 && slotid <= MAXSLOTS);
1686 DPRINTF("xhci_disable_slot(%d)\n", slotid);
1687
1688 for (i = 1; i <= 31; i++) {
1689 if (xhci->slots[slotid-1].eps[i-1]) {
1690 xhci_disable_ep(xhci, slotid, i);
1691 }
1692 }
1693
1694 xhci->slots[slotid-1].enabled = 0;
1695 return CC_SUCCESS;
1696 }
1697
1698 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1699 uint64_t pictx, bool bsr)
1700 {
1701 XHCISlot *slot;
1702 USBDevice *dev;
1703 target_phys_addr_t ictx, octx, dcbaap;
1704 uint64_t poctx;
1705 uint32_t ictl_ctx[2];
1706 uint32_t slot_ctx[4];
1707 uint32_t ep0_ctx[5];
1708 unsigned int port;
1709 int i;
1710 TRBCCode res;
1711
1712 assert(slotid >= 1 && slotid <= MAXSLOTS);
1713 DPRINTF("xhci_address_slot(%d)\n", slotid);
1714
1715 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
1716 cpu_physical_memory_read(dcbaap + 8*slotid,
1717 (uint8_t *) &poctx, sizeof(poctx));
1718 ictx = xhci_mask64(pictx);
1719 octx = xhci_mask64(le64_to_cpu(poctx));
1720
1721 DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx);
1722 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
1723
1724 cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
1725
1726 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1727 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1728 ictl_ctx[0], ictl_ctx[1]);
1729 return CC_TRB_ERROR;
1730 }
1731
1732 cpu_physical_memory_read(ictx+32, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1733 cpu_physical_memory_read(ictx+64, (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
1734
1735 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1736 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1737
1738 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1739 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1740
1741 port = (slot_ctx[1]>>16) & 0xFF;
1742 dev = xhci->ports[port-1].port.dev;
1743
1744 if (port < 1 || port > MAXPORTS) {
1745 fprintf(stderr, "xhci: bad port %d\n", port);
1746 return CC_TRB_ERROR;
1747 } else if (!dev) {
1748 fprintf(stderr, "xhci: port %d not connected\n", port);
1749 return CC_USB_TRANSACTION_ERROR;
1750 }
1751
1752 for (i = 0; i < MAXSLOTS; i++) {
1753 if (xhci->slots[i].port == port) {
1754 fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
1755 port, i+1);
1756 return CC_TRB_ERROR;
1757 }
1758 }
1759
1760 slot = &xhci->slots[slotid-1];
1761 slot->port = port;
1762 slot->ctx = octx;
1763
1764 if (bsr) {
1765 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
1766 } else {
1767 slot->devaddr = xhci->devaddr++;
1768 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
1769 DPRINTF("xhci: device address is %d\n", slot->devaddr);
1770 usb_device_handle_control(dev, NULL,
1771 DeviceOutRequest | USB_REQ_SET_ADDRESS,
1772 slot->devaddr, 0, 0, NULL);
1773 }
1774
1775 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1776
1777 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1778 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1779 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1780 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1781
1782 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1783 cpu_physical_memory_write(octx+32, (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
1784
1785 return res;
1786 }
1787
1788
1789 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1790 uint64_t pictx, bool dc)
1791 {
1792 target_phys_addr_t ictx, octx;
1793 uint32_t ictl_ctx[2];
1794 uint32_t slot_ctx[4];
1795 uint32_t islot_ctx[4];
1796 uint32_t ep_ctx[5];
1797 int i;
1798 TRBCCode res;
1799
1800 assert(slotid >= 1 && slotid <= MAXSLOTS);
1801 DPRINTF("xhci_configure_slot(%d)\n", slotid);
1802
1803 ictx = xhci_mask64(pictx);
1804 octx = xhci->slots[slotid-1].ctx;
1805
1806 DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx);
1807 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
1808
1809 if (dc) {
1810 for (i = 2; i <= 31; i++) {
1811 if (xhci->slots[slotid-1].eps[i-1]) {
1812 xhci_disable_ep(xhci, slotid, i);
1813 }
1814 }
1815
1816 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1817 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1818 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
1819 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1820 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1821 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1822
1823 return CC_SUCCESS;
1824 }
1825
1826 cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
1827
1828 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1829 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1830 ictl_ctx[0], ictl_ctx[1]);
1831 return CC_TRB_ERROR;
1832 }
1833
1834 cpu_physical_memory_read(ictx+32, (uint8_t *) islot_ctx, sizeof(islot_ctx));
1835 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1836
1837 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
1838 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1839 return CC_CONTEXT_STATE_ERROR;
1840 }
1841
1842 for (i = 2; i <= 31; i++) {
1843 if (ictl_ctx[0] & (1<<i)) {
1844 xhci_disable_ep(xhci, slotid, i);
1845 }
1846 if (ictl_ctx[1] & (1<<i)) {
1847 cpu_physical_memory_read(ictx+32+(32*i),
1848 (uint8_t *) ep_ctx, sizeof(ep_ctx));
1849 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1850 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1851 ep_ctx[3], ep_ctx[4]);
1852 xhci_disable_ep(xhci, slotid, i);
1853 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1854 if (res != CC_SUCCESS) {
1855 return res;
1856 }
1857 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1858 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1859 ep_ctx[3], ep_ctx[4]);
1860 cpu_physical_memory_write(octx+(32*i),
1861 (uint8_t *) ep_ctx, sizeof(ep_ctx));
1862 }
1863 }
1864
1865 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1866 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
1867 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
1868 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
1869 SLOT_CONTEXT_ENTRIES_SHIFT);
1870 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1871 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1872
1873 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1874
1875 return CC_SUCCESS;
1876 }
1877
1878
1879 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1880 uint64_t pictx)
1881 {
1882 target_phys_addr_t ictx, octx;
1883 uint32_t ictl_ctx[2];
1884 uint32_t iep0_ctx[5];
1885 uint32_t ep0_ctx[5];
1886 uint32_t islot_ctx[4];
1887 uint32_t slot_ctx[4];
1888
1889 assert(slotid >= 1 && slotid <= MAXSLOTS);
1890 DPRINTF("xhci_evaluate_slot(%d)\n", slotid);
1891
1892 ictx = xhci_mask64(pictx);
1893 octx = xhci->slots[slotid-1].ctx;
1894
1895 DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx);
1896 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
1897
1898 cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
1899
1900 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1901 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1902 ictl_ctx[0], ictl_ctx[1]);
1903 return CC_TRB_ERROR;
1904 }
1905
1906 if (ictl_ctx[1] & 0x1) {
1907 cpu_physical_memory_read(ictx+32,
1908 (uint8_t *) islot_ctx, sizeof(islot_ctx));
1909
1910 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1911 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
1912
1913 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1914
1915 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
1916 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
1917 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
1918 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
1919
1920 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1921 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1922
1923 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1924 }
1925
1926 if (ictl_ctx[1] & 0x2) {
1927 cpu_physical_memory_read(ictx+64,
1928 (uint8_t *) iep0_ctx, sizeof(iep0_ctx));
1929
1930 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1931 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
1932 iep0_ctx[3], iep0_ctx[4]);
1933
1934 cpu_physical_memory_read(octx+32, (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
1935
1936 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
1937 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
1938
1939 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1940 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1941
1942 cpu_physical_memory_write(octx+32,
1943 (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
1944 }
1945
1946 return CC_SUCCESS;
1947 }
1948
1949 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
1950 {
1951 uint32_t slot_ctx[4];
1952 target_phys_addr_t octx;
1953 int i;
1954
1955 assert(slotid >= 1 && slotid <= MAXSLOTS);
1956 DPRINTF("xhci_reset_slot(%d)\n", slotid);
1957
1958 octx = xhci->slots[slotid-1].ctx;
1959
1960 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
1961
1962 for (i = 2; i <= 31; i++) {
1963 if (xhci->slots[slotid-1].eps[i-1]) {
1964 xhci_disable_ep(xhci, slotid, i);
1965 }
1966 }
1967
1968 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1969 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1970 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
1971 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1972 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1973 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1974
1975 return CC_SUCCESS;
1976 }
1977
1978 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
1979 {
1980 unsigned int slotid;
1981 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
1982 if (slotid < 1 || slotid > MAXSLOTS) {
1983 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
1984 event->ccode = CC_TRB_ERROR;
1985 return 0;
1986 } else if (!xhci->slots[slotid-1].enabled) {
1987 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
1988 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
1989 return 0;
1990 }
1991 return slotid;
1992 }
1993
1994 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
1995 {
1996 target_phys_addr_t ctx;
1997 uint8_t bw_ctx[MAXPORTS+1];
1998
1999 DPRINTF("xhci_get_port_bandwidth()\n");
2000
2001 ctx = xhci_mask64(pctx);
2002
2003 DPRINTF("xhci: bandwidth context at "TARGET_FMT_plx"\n", ctx);
2004
2005 /* TODO: actually implement real values here */
2006 bw_ctx[0] = 0;
2007 memset(&bw_ctx[1], 80, MAXPORTS); /* 80% */
2008 cpu_physical_memory_write(ctx, bw_ctx, sizeof(bw_ctx));
2009
2010 return CC_SUCCESS;
2011 }
2012
2013 static uint32_t rotl(uint32_t v, unsigned count)
2014 {
2015 count &= 31;
2016 return (v << count) | (v >> (32 - count));
2017 }
2018
2019
2020 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2021 {
2022 uint32_t val;
2023 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2024 val += rotl(lo + 0x49434878, hi & 0x1F);
2025 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2026 return ~val;
2027 }
2028
2029 static void xhci_via_challenge(uint64_t addr)
2030 {
2031 uint32_t buf[8];
2032 uint32_t obuf[8];
2033 target_phys_addr_t paddr = xhci_mask64(addr);
2034
2035 cpu_physical_memory_read(paddr, (uint8_t *) &buf, 32);
2036
2037 memcpy(obuf, buf, sizeof(obuf));
2038
2039 if ((buf[0] & 0xff) == 2) {
2040 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2041 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2042 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2043 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2044 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2045 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2046 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2047 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2048 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2049 }
2050
2051 cpu_physical_memory_write(paddr, (uint8_t *) &obuf, 32);
2052 }
2053
2054 static void xhci_process_commands(XHCIState *xhci)
2055 {
2056 XHCITRB trb;
2057 TRBType type;
2058 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2059 target_phys_addr_t addr;
2060 unsigned int i, slotid = 0;
2061
2062 DPRINTF("xhci_process_commands()\n");
2063 if (!xhci_running(xhci)) {
2064 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2065 return;
2066 }
2067
2068 xhci->crcr_low |= CRCR_CRR;
2069
2070 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2071 event.ptr = addr;
2072 switch (type) {
2073 case CR_ENABLE_SLOT:
2074 for (i = 0; i < MAXSLOTS; i++) {
2075 if (!xhci->slots[i].enabled) {
2076 break;
2077 }
2078 }
2079 if (i >= MAXSLOTS) {
2080 fprintf(stderr, "xhci: no device slots available\n");
2081 event.ccode = CC_NO_SLOTS_ERROR;
2082 } else {
2083 slotid = i+1;
2084 event.ccode = xhci_enable_slot(xhci, slotid);
2085 }
2086 break;
2087 case CR_DISABLE_SLOT:
2088 slotid = xhci_get_slot(xhci, &event, &trb);
2089 if (slotid) {
2090 event.ccode = xhci_disable_slot(xhci, slotid);
2091 }
2092 break;
2093 case CR_ADDRESS_DEVICE:
2094 slotid = xhci_get_slot(xhci, &event, &trb);
2095 if (slotid) {
2096 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2097 trb.control & TRB_CR_BSR);
2098 }
2099 break;
2100 case CR_CONFIGURE_ENDPOINT:
2101 slotid = xhci_get_slot(xhci, &event, &trb);
2102 if (slotid) {
2103 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2104 trb.control & TRB_CR_DC);
2105 }
2106 break;
2107 case CR_EVALUATE_CONTEXT:
2108 slotid = xhci_get_slot(xhci, &event, &trb);
2109 if (slotid) {
2110 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2111 }
2112 break;
2113 case CR_STOP_ENDPOINT:
2114 slotid = xhci_get_slot(xhci, &event, &trb);
2115 if (slotid) {
2116 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2117 & TRB_CR_EPID_MASK;
2118 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2119 }
2120 break;
2121 case CR_RESET_ENDPOINT:
2122 slotid = xhci_get_slot(xhci, &event, &trb);
2123 if (slotid) {
2124 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2125 & TRB_CR_EPID_MASK;
2126 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2127 }
2128 break;
2129 case CR_SET_TR_DEQUEUE:
2130 slotid = xhci_get_slot(xhci, &event, &trb);
2131 if (slotid) {
2132 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2133 & TRB_CR_EPID_MASK;
2134 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
2135 trb.parameter);
2136 }
2137 break;
2138 case CR_RESET_DEVICE:
2139 slotid = xhci_get_slot(xhci, &event, &trb);
2140 if (slotid) {
2141 event.ccode = xhci_reset_slot(xhci, slotid);
2142 }
2143 break;
2144 case CR_GET_PORT_BANDWIDTH:
2145 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2146 break;
2147 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2148 xhci_via_challenge(trb.parameter);
2149 break;
2150 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2151 event.type = 48; /* NEC reply */
2152 event.length = 0x3025;
2153 break;
2154 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2155 {
2156 uint32_t chi = trb.parameter >> 32;
2157 uint32_t clo = trb.parameter;
2158 uint32_t val = xhci_nec_challenge(chi, clo);
2159 event.length = val & 0xFFFF;
2160 event.epid = val >> 16;
2161 slotid = val >> 24;
2162 event.type = 48; /* NEC reply */
2163 }
2164 break;
2165 default:
2166 fprintf(stderr, "xhci: unimplemented command %d\n", type);
2167 event.ccode = CC_TRB_ERROR;
2168 break;
2169 }
2170 event.slotid = slotid;
2171 xhci_event(xhci, &event);
2172 }
2173 }
2174
2175 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2176 {
2177 int nr = port->port.index + 1;
2178
2179 port->portsc = PORTSC_PP;
2180 if (port->port.dev && !is_detach) {
2181 port->portsc |= PORTSC_CCS;
2182 switch (port->port.dev->speed) {
2183 case USB_SPEED_LOW:
2184 port->portsc |= PORTSC_SPEED_LOW;
2185 break;
2186 case USB_SPEED_FULL:
2187 port->portsc |= PORTSC_SPEED_FULL;
2188 break;
2189 case USB_SPEED_HIGH:
2190 port->portsc |= PORTSC_SPEED_HIGH;
2191 break;
2192 }
2193 }
2194
2195 if (xhci_running(xhci)) {
2196 port->portsc |= PORTSC_CSC;
2197 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2198 xhci_event(xhci, &ev);
2199 DPRINTF("xhci: port change event for port %d\n", nr);
2200 }
2201 }
2202
2203 static void xhci_reset(void *opaque)
2204 {
2205 XHCIState *xhci = opaque;
2206 int i;
2207
2208 DPRINTF("xhci: full reset\n");
2209 if (!(xhci->usbsts & USBSTS_HCH)) {
2210 fprintf(stderr, "xhci: reset while running!\n");
2211 }
2212
2213 xhci->usbcmd = 0;
2214 xhci->usbsts = USBSTS_HCH;
2215 xhci->dnctrl = 0;
2216 xhci->crcr_low = 0;
2217 xhci->crcr_high = 0;
2218 xhci->dcbaap_low = 0;
2219 xhci->dcbaap_high = 0;
2220 xhci->config = 0;
2221 xhci->devaddr = 2;
2222
2223 for (i = 0; i < MAXSLOTS; i++) {
2224 xhci_disable_slot(xhci, i+1);
2225 }
2226
2227 for (i = 0; i < MAXPORTS; i++) {
2228 xhci_update_port(xhci, xhci->ports + i, 0);
2229 }
2230
2231 xhci->mfindex = 0;
2232 xhci->iman = 0;
2233 xhci->imod = 0;
2234 xhci->erstsz = 0;
2235 xhci->erstba_low = 0;
2236 xhci->erstba_high = 0;
2237 xhci->erdp_low = 0;
2238 xhci->erdp_high = 0;
2239
2240 xhci->er_ep_idx = 0;
2241 xhci->er_pcs = 1;
2242 xhci->er_full = 0;
2243 xhci->ev_buffer_put = 0;
2244 xhci->ev_buffer_get = 0;
2245 }
2246
2247 static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2248 {
2249 DPRINTF("xhci_cap_read(0x%x)\n", reg);
2250
2251 switch (reg) {
2252 case 0x00: /* HCIVERSION, CAPLENGTH */
2253 return 0x01000000 | LEN_CAP;
2254 case 0x04: /* HCSPARAMS 1 */
2255 return (MAXPORTS<<24) | (MAXINTRS<<8) | MAXSLOTS;
2256 case 0x08: /* HCSPARAMS 2 */
2257 return 0x0000000f;
2258 case 0x0c: /* HCSPARAMS 3 */
2259 return 0x00000000;
2260 case 0x10: /* HCCPARAMS */
2261 #if TARGET_PHYS_ADDR_BITS > 32
2262 return 0x00081001;
2263 #else
2264 return 0x00081000;
2265 #endif
2266 case 0x14: /* DBOFF */
2267 return OFF_DOORBELL;
2268 case 0x18: /* RTSOFF */
2269 return OFF_RUNTIME;
2270
2271 /* extended capabilities */
2272 case 0x20: /* Supported Protocol:00 */
2273 #if USB3_PORTS > 0
2274 return 0x02000402; /* USB 2.0 */
2275 #else
2276 return 0x02000002; /* USB 2.0 */
2277 #endif
2278 case 0x24: /* Supported Protocol:04 */
2279 return 0x20425455; /* "USB " */
2280 case 0x28: /* Supported Protocol:08 */
2281 return 0x00000001 | (USB2_PORTS<<8);
2282 case 0x2c: /* Supported Protocol:0c */
2283 return 0x00000000; /* reserved */
2284 #if USB3_PORTS > 0
2285 case 0x30: /* Supported Protocol:00 */
2286 return 0x03000002; /* USB 3.0 */
2287 case 0x34: /* Supported Protocol:04 */
2288 return 0x20425455; /* "USB " */
2289 case 0x38: /* Supported Protocol:08 */
2290 return 0x00000000 | (USB2_PORTS+1) | (USB3_PORTS<<8);
2291 case 0x3c: /* Supported Protocol:0c */
2292 return 0x00000000; /* reserved */
2293 #endif
2294 default:
2295 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2296 }
2297 return 0;
2298 }
2299
2300 static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2301 {
2302 uint32_t port = reg >> 4;
2303 if (port >= MAXPORTS) {
2304 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2305 return 0;
2306 }
2307
2308 switch (reg & 0xf) {
2309 case 0x00: /* PORTSC */
2310 return xhci->ports[port].portsc;
2311 case 0x04: /* PORTPMSC */
2312 case 0x08: /* PORTLI */
2313 return 0;
2314 case 0x0c: /* reserved */
2315 default:
2316 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2317 port, reg);
2318 return 0;
2319 }
2320 }
2321
2322 static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2323 {
2324 uint32_t port = reg >> 4;
2325 uint32_t portsc;
2326
2327 if (port >= MAXPORTS) {
2328 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2329 return;
2330 }
2331
2332 switch (reg & 0xf) {
2333 case 0x00: /* PORTSC */
2334 portsc = xhci->ports[port].portsc;
2335 /* write-1-to-clear bits*/
2336 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2337 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2338 if (val & PORTSC_LWS) {
2339 /* overwrite PLS only when LWS=1 */
2340 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2341 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2342 }
2343 /* read/write bits */
2344 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2345 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2346 /* write-1-to-start bits */
2347 if (val & PORTSC_PR) {
2348 DPRINTF("xhci: port %d reset\n", port);
2349 if (xhci->ports[port].port.dev) {
2350 usb_send_msg(xhci->ports[port].port.dev, USB_MSG_RESET);
2351 }
2352 portsc |= PORTSC_PRC | PORTSC_PED;
2353 }
2354 xhci->ports[port].portsc = portsc;
2355 break;
2356 case 0x04: /* PORTPMSC */
2357 case 0x08: /* PORTLI */
2358 default:
2359 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2360 port, reg);
2361 }
2362 }
2363
2364 static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2365 {
2366 DPRINTF("xhci_oper_read(0x%x)\n", reg);
2367
2368 if (reg >= 0x400) {
2369 return xhci_port_read(xhci, reg - 0x400);
2370 }
2371
2372 switch (reg) {
2373 case 0x00: /* USBCMD */
2374 return xhci->usbcmd;
2375 case 0x04: /* USBSTS */
2376 return xhci->usbsts;
2377 case 0x08: /* PAGESIZE */
2378 return 1; /* 4KiB */
2379 case 0x14: /* DNCTRL */
2380 return xhci->dnctrl;
2381 case 0x18: /* CRCR low */
2382 return xhci->crcr_low & ~0xe;
2383 case 0x1c: /* CRCR high */
2384 return xhci->crcr_high;
2385 case 0x30: /* DCBAAP low */
2386 return xhci->dcbaap_low;
2387 case 0x34: /* DCBAAP high */
2388 return xhci->dcbaap_high;
2389 case 0x38: /* CONFIG */
2390 return xhci->config;
2391 default:
2392 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2393 }
2394 return 0;
2395 }
2396
2397 static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2398 {
2399 DPRINTF("xhci_oper_write(0x%x, 0x%08x)\n", reg, val);
2400
2401 if (reg >= 0x400) {
2402 xhci_port_write(xhci, reg - 0x400, val);
2403 return;
2404 }
2405
2406 switch (reg) {
2407 case 0x00: /* USBCMD */
2408 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2409 xhci_run(xhci);
2410 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2411 xhci_stop(xhci);
2412 }
2413 xhci->usbcmd = val & 0xc0f;
2414 if (val & USBCMD_HCRST) {
2415 xhci_reset(xhci);
2416 }
2417 xhci_irq_update(xhci);
2418 break;
2419
2420 case 0x04: /* USBSTS */
2421 /* these bits are write-1-to-clear */
2422 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2423 xhci_irq_update(xhci);
2424 break;
2425
2426 case 0x14: /* DNCTRL */
2427 xhci->dnctrl = val & 0xffff;
2428 break;
2429 case 0x18: /* CRCR low */
2430 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2431 break;
2432 case 0x1c: /* CRCR high */
2433 xhci->crcr_high = val;
2434 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2435 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2436 xhci->crcr_low &= ~CRCR_CRR;
2437 xhci_event(xhci, &event);
2438 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2439 } else {
2440 target_phys_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2441 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2442 }
2443 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2444 break;
2445 case 0x30: /* DCBAAP low */
2446 xhci->dcbaap_low = val & 0xffffffc0;
2447 break;
2448 case 0x34: /* DCBAAP high */
2449 xhci->dcbaap_high = val;
2450 break;
2451 case 0x38: /* CONFIG */
2452 xhci->config = val & 0xff;
2453 break;
2454 default:
2455 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2456 }
2457 }
2458
2459 static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2460 {
2461 DPRINTF("xhci_runtime_read(0x%x)\n", reg);
2462
2463 switch (reg) {
2464 case 0x00: /* MFINDEX */
2465 fprintf(stderr, "xhci_runtime_read: MFINDEX not yet implemented\n");
2466 return xhci->mfindex;
2467 case 0x20: /* IMAN */
2468 return xhci->iman;
2469 case 0x24: /* IMOD */
2470 return xhci->imod;
2471 case 0x28: /* ERSTSZ */
2472 return xhci->erstsz;
2473 case 0x30: /* ERSTBA low */
2474 return xhci->erstba_low;
2475 case 0x34: /* ERSTBA high */
2476 return xhci->erstba_high;
2477 case 0x38: /* ERDP low */
2478 return xhci->erdp_low;
2479 case 0x3c: /* ERDP high */
2480 return xhci->erdp_high;
2481 default:
2482 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2483 }
2484 return 0;
2485 }
2486
2487 static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2488 {
2489 DPRINTF("xhci_runtime_write(0x%x, 0x%08x)\n", reg, val);
2490
2491 switch (reg) {
2492 case 0x20: /* IMAN */
2493 if (val & IMAN_IP) {
2494 xhci->iman &= ~IMAN_IP;
2495 }
2496 xhci->iman &= ~IMAN_IE;
2497 xhci->iman |= val & IMAN_IE;
2498 xhci_irq_update(xhci);
2499 break;
2500 case 0x24: /* IMOD */
2501 xhci->imod = val;
2502 break;
2503 case 0x28: /* ERSTSZ */
2504 xhci->erstsz = val & 0xffff;
2505 break;
2506 case 0x30: /* ERSTBA low */
2507 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2508 xhci->erstba_low = val & 0xffffffc0; */
2509 xhci->erstba_low = val & 0xfffffff0;
2510 break;
2511 case 0x34: /* ERSTBA high */
2512 xhci->erstba_high = val;
2513 xhci_er_reset(xhci);
2514 break;
2515 case 0x38: /* ERDP low */
2516 if (val & ERDP_EHB) {
2517 xhci->erdp_low &= ~ERDP_EHB;
2518 }
2519 xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB);
2520 break;
2521 case 0x3c: /* ERDP high */
2522 xhci->erdp_high = val;
2523 xhci_events_update(xhci);
2524 break;
2525 default:
2526 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2527 }
2528 }
2529
2530 static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2531 {
2532 DPRINTF("xhci_doorbell_read(0x%x)\n", reg);
2533 /* doorbells always read as 0 */
2534 return 0;
2535 }
2536
2537 static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2538 {
2539 DPRINTF("xhci_doorbell_write(0x%x, 0x%08x)\n", reg, val);
2540
2541 if (!xhci_running(xhci)) {
2542 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2543 return;
2544 }
2545
2546 reg >>= 2;
2547
2548 if (reg == 0) {
2549 if (val == 0) {
2550 xhci_process_commands(xhci);
2551 } else {
2552 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2553 }
2554 } else {
2555 if (reg > MAXSLOTS) {
2556 fprintf(stderr, "xhci: bad doorbell %d\n", reg);
2557 } else if (val > 31) {
2558 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2559 } else {
2560 xhci_kick_ep(xhci, reg, val);
2561 }
2562 }
2563 }
2564
2565 static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2566 unsigned size)
2567 {
2568 XHCIState *xhci = ptr;
2569
2570 /* Only aligned reads are allowed on xHCI */
2571 if (addr & 3) {
2572 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
2573 return 0;
2574 }
2575
2576 if (addr < LEN_CAP) {
2577 return xhci_cap_read(xhci, addr);
2578 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2579 return xhci_oper_read(xhci, addr - OFF_OPER);
2580 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2581 return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
2582 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2583 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
2584 } else {
2585 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2586 return 0;
2587 }
2588 }
2589
2590 static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2591 uint64_t val, unsigned size)
2592 {
2593 XHCIState *xhci = ptr;
2594
2595 /* Only aligned writes are allowed on xHCI */
2596 if (addr & 3) {
2597 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
2598 return;
2599 }
2600
2601 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2602 xhci_oper_write(xhci, addr - OFF_OPER, val);
2603 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2604 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
2605 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2606 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
2607 } else {
2608 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2609 }
2610 }
2611
2612 static const MemoryRegionOps xhci_mem_ops = {
2613 .read = xhci_mem_read,
2614 .write = xhci_mem_write,
2615 .valid.min_access_size = 4,
2616 .valid.max_access_size = 4,
2617 .endianness = DEVICE_LITTLE_ENDIAN,
2618 };
2619
2620 static void xhci_attach(USBPort *usbport)
2621 {
2622 XHCIState *xhci = usbport->opaque;
2623 XHCIPort *port = &xhci->ports[usbport->index];
2624
2625 xhci_update_port(xhci, port, 0);
2626 }
2627
2628 static void xhci_detach(USBPort *usbport)
2629 {
2630 XHCIState *xhci = usbport->opaque;
2631 XHCIPort *port = &xhci->ports[usbport->index];
2632
2633 xhci_update_port(xhci, port, 1);
2634 }
2635
2636 static void xhci_complete(USBPort *port, USBPacket *packet)
2637 {
2638 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
2639
2640 xhci_complete_packet(xfer, packet->result);
2641 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2642 }
2643
2644 static void xhci_child_detach(USBPort *port, USBDevice *child)
2645 {
2646 FIXME();
2647 }
2648
2649 static USBPortOps xhci_port_ops = {
2650 .attach = xhci_attach,
2651 .detach = xhci_detach,
2652 .complete = xhci_complete,
2653 .child_detach = xhci_child_detach,
2654 };
2655
2656 static USBBusOps xhci_bus_ops = {
2657 };
2658
2659 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2660 {
2661 int i;
2662
2663 xhci->usbsts = USBSTS_HCH;
2664
2665 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2666
2667 for (i = 0; i < MAXPORTS; i++) {
2668 memset(&xhci->ports[i], 0, sizeof(xhci->ports[i]));
2669 usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i,
2670 &xhci_port_ops, USB_SPEED_MASK_HIGH);
2671 }
2672 for (i = 0; i < MAXSLOTS; i++) {
2673 xhci->slots[i].enabled = 0;
2674 }
2675
2676 qemu_register_reset(xhci_reset, xhci);
2677 }
2678
2679 static int usb_xhci_initfn(struct PCIDevice *dev)
2680 {
2681 int ret;
2682
2683 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2684
2685 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
2686 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
2687 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
2688 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2689
2690 usb_xhci_init(xhci, &dev->qdev);
2691
2692 xhci->irq = xhci->pci_dev.irq[0];
2693
2694 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2695 "xhci", LEN_REGS);
2696 pci_register_bar(&xhci->pci_dev, 0,
2697 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
2698 &xhci->mem);
2699
2700 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0);
2701 assert(ret >= 0);
2702
2703 if (xhci->msi) {
2704 ret = msi_init(&xhci->pci_dev, 0x70, 1, true, false);
2705 assert(ret >= 0);
2706 }
2707
2708 return 0;
2709 }
2710
2711 static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
2712 int len)
2713 {
2714 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2715
2716 pci_default_write_config(dev, addr, val, len);
2717 if (xhci->msi) {
2718 msi_write_config(dev, addr, val, len);
2719 }
2720 }
2721
2722 static const VMStateDescription vmstate_xhci = {
2723 .name = "xhci",
2724 .unmigratable = 1,
2725 };
2726
2727 static void xhci_class_init(ObjectClass *klass, void *data)
2728 {
2729 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2730
2731 k->init = usb_xhci_initfn;
2732 k->vendor_id = PCI_VENDOR_ID_NEC;
2733 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
2734 k->class_id = PCI_CLASS_SERIAL_USB;
2735 k->revision = 0x03;
2736 k->is_express = 1;
2737 k->config_write = xhci_write_config;
2738 }
2739
2740 static DeviceInfo xhci_info = {
2741 .name = "nec-usb-xhci",
2742 .alias = "xhci",
2743 .size = sizeof(XHCIState),
2744 .vmsd = &vmstate_xhci,
2745 .class_init = xhci_class_init,
2746 .props = (Property[]) {
2747 DEFINE_PROP_UINT32("msi", XHCIState, msi, 0),
2748 DEFINE_PROP_END_OF_LIST(),
2749 }
2750 };
2751
2752 static void xhci_register(void)
2753 {
2754 pci_qdev_register(&xhci_info);
2755 }
2756 device_init(xhci_register);