Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging
[qemu.git] / hw / usb / hcd-ohci.c
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o BIOS work to boot from USB storage
26 */
27
28 #include "qemu/osdep.h"
29 #include "hw/irq.h"
30 #include "qapi/error.h"
31 #include "qemu/module.h"
32 #include "qemu/timer.h"
33 #include "hw/usb.h"
34 #include "migration/vmstate.h"
35 #include "hw/sysbus.h"
36 #include "hw/qdev-dma.h"
37 #include "hw/qdev-properties.h"
38 #include "trace.h"
39 #include "hcd-ohci.h"
40
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #define ED_LINK_LIMIT 32
45
46 static int64_t usb_frame_time;
47 static int64_t usb_bit_time;
48
49 /* Host Controller Communications Area */
50 struct ohci_hcca {
51 uint32_t intr[32];
52 uint16_t frame, pad;
53 uint32_t done;
54 };
55 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame)
56 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */
57
58 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
59 #define ED_WBACK_SIZE 4
60
61 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev);
62
63 /* Bitfields for the first word of an Endpoint Desciptor. */
64 #define OHCI_ED_FA_SHIFT 0
65 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
66 #define OHCI_ED_EN_SHIFT 7
67 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
68 #define OHCI_ED_D_SHIFT 11
69 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
70 #define OHCI_ED_S (1<<13)
71 #define OHCI_ED_K (1<<14)
72 #define OHCI_ED_F (1<<15)
73 #define OHCI_ED_MPS_SHIFT 16
74 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
75
76 /* Flags in the head field of an Endpoint Desciptor. */
77 #define OHCI_ED_H 1
78 #define OHCI_ED_C 2
79
80 /* Bitfields for the first word of a Transfer Desciptor. */
81 #define OHCI_TD_R (1<<18)
82 #define OHCI_TD_DP_SHIFT 19
83 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
84 #define OHCI_TD_DI_SHIFT 21
85 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
86 #define OHCI_TD_T0 (1<<24)
87 #define OHCI_TD_T1 (1<<25)
88 #define OHCI_TD_EC_SHIFT 26
89 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
90 #define OHCI_TD_CC_SHIFT 28
91 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
92
93 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
94 /* CC & DI - same as in the General Transfer Desciptor */
95 #define OHCI_TD_SF_SHIFT 0
96 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
97 #define OHCI_TD_FC_SHIFT 24
98 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
99
100 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
101 #define OHCI_TD_PSW_CC_SHIFT 12
102 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
103 #define OHCI_TD_PSW_SIZE_SHIFT 0
104 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
105
106 #define OHCI_PAGE_MASK 0xfffff000
107 #define OHCI_OFFSET_MASK 0xfff
108
109 #define OHCI_DPTR_MASK 0xfffffff0
110
111 #define OHCI_BM(val, field) \
112 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
113
114 #define OHCI_SET_BM(val, field, newval) do { \
115 val &= ~OHCI_##field##_MASK; \
116 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
117 } while(0)
118
119 /* endpoint descriptor */
120 struct ohci_ed {
121 uint32_t flags;
122 uint32_t tail;
123 uint32_t head;
124 uint32_t next;
125 };
126
127 /* General transfer descriptor */
128 struct ohci_td {
129 uint32_t flags;
130 uint32_t cbp;
131 uint32_t next;
132 uint32_t be;
133 };
134
135 /* Isochronous transfer descriptor */
136 struct ohci_iso_td {
137 uint32_t flags;
138 uint32_t bp;
139 uint32_t next;
140 uint32_t be;
141 uint16_t offset[8];
142 };
143
144 #define USB_HZ 12000000
145
146 /* OHCI Local stuff */
147 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
148 #define OHCI_CTL_PLE (1<<2)
149 #define OHCI_CTL_IE (1<<3)
150 #define OHCI_CTL_CLE (1<<4)
151 #define OHCI_CTL_BLE (1<<5)
152 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
153 #define OHCI_USB_RESET 0x00
154 #define OHCI_USB_RESUME 0x40
155 #define OHCI_USB_OPERATIONAL 0x80
156 #define OHCI_USB_SUSPEND 0xc0
157 #define OHCI_CTL_IR (1<<8)
158 #define OHCI_CTL_RWC (1<<9)
159 #define OHCI_CTL_RWE (1<<10)
160
161 #define OHCI_STATUS_HCR (1<<0)
162 #define OHCI_STATUS_CLF (1<<1)
163 #define OHCI_STATUS_BLF (1<<2)
164 #define OHCI_STATUS_OCR (1<<3)
165 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
166
167 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
168 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
169 #define OHCI_INTR_SF (1U<<2) /* Start of frame */
170 #define OHCI_INTR_RD (1U<<3) /* Resume detect */
171 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
172 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
173 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
174 #define OHCI_INTR_OC (1U<<30) /* Ownership change */
175 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
176
177 #define OHCI_HCCA_SIZE 0x100
178 #define OHCI_HCCA_MASK 0xffffff00
179
180 #define OHCI_EDPTR_MASK 0xfffffff0
181
182 #define OHCI_FMI_FI 0x00003fff
183 #define OHCI_FMI_FSMPS 0xffff0000
184 #define OHCI_FMI_FIT 0x80000000
185
186 #define OHCI_FR_RT (1U<<31)
187
188 #define OHCI_LS_THRESH 0x628
189
190 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
191 #define OHCI_RHA_PSM (1<<8)
192 #define OHCI_RHA_NPS (1<<9)
193 #define OHCI_RHA_DT (1<<10)
194 #define OHCI_RHA_OCPM (1<<11)
195 #define OHCI_RHA_NOCP (1<<12)
196 #define OHCI_RHA_POTPGT_MASK 0xff000000
197
198 #define OHCI_RHS_LPS (1U<<0)
199 #define OHCI_RHS_OCI (1U<<1)
200 #define OHCI_RHS_DRWE (1U<<15)
201 #define OHCI_RHS_LPSC (1U<<16)
202 #define OHCI_RHS_OCIC (1U<<17)
203 #define OHCI_RHS_CRWE (1U<<31)
204
205 #define OHCI_PORT_CCS (1<<0)
206 #define OHCI_PORT_PES (1<<1)
207 #define OHCI_PORT_PSS (1<<2)
208 #define OHCI_PORT_POCI (1<<3)
209 #define OHCI_PORT_PRS (1<<4)
210 #define OHCI_PORT_PPS (1<<8)
211 #define OHCI_PORT_LSDA (1<<9)
212 #define OHCI_PORT_CSC (1<<16)
213 #define OHCI_PORT_PESC (1<<17)
214 #define OHCI_PORT_PSSC (1<<18)
215 #define OHCI_PORT_OCIC (1<<19)
216 #define OHCI_PORT_PRSC (1<<20)
217 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
218 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
219
220 #define OHCI_TD_DIR_SETUP 0x0
221 #define OHCI_TD_DIR_OUT 0x1
222 #define OHCI_TD_DIR_IN 0x2
223 #define OHCI_TD_DIR_RESERVED 0x3
224
225 #define OHCI_CC_NOERROR 0x0
226 #define OHCI_CC_CRC 0x1
227 #define OHCI_CC_BITSTUFFING 0x2
228 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
229 #define OHCI_CC_STALL 0x4
230 #define OHCI_CC_DEVICENOTRESPONDING 0x5
231 #define OHCI_CC_PIDCHECKFAILURE 0x6
232 #define OHCI_CC_UNDEXPETEDPID 0x7
233 #define OHCI_CC_DATAOVERRUN 0x8
234 #define OHCI_CC_DATAUNDERRUN 0x9
235 #define OHCI_CC_BUFFEROVERRUN 0xc
236 #define OHCI_CC_BUFFERUNDERRUN 0xd
237
238 #define OHCI_HRESET_FSBIR (1 << 0)
239
240 static void ohci_die(OHCIState *ohci)
241 {
242 ohci->ohci_die(ohci);
243 }
244
245 /* Update IRQ levels */
246 static inline void ohci_intr_update(OHCIState *ohci)
247 {
248 int level = 0;
249
250 if ((ohci->intr & OHCI_INTR_MIE) &&
251 (ohci->intr_status & ohci->intr))
252 level = 1;
253
254 qemu_set_irq(ohci->irq, level);
255 }
256
257 /* Set an interrupt */
258 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
259 {
260 ohci->intr_status |= intr;
261 ohci_intr_update(ohci);
262 }
263
264 /* Attach or detach a device on a root hub port. */
265 static void ohci_attach(USBPort *port1)
266 {
267 OHCIState *s = port1->opaque;
268 OHCIPort *port = &s->rhport[port1->index];
269 uint32_t old_state = port->ctrl;
270
271 /* set connect status */
272 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
273
274 /* update speed */
275 if (port->port.dev->speed == USB_SPEED_LOW) {
276 port->ctrl |= OHCI_PORT_LSDA;
277 } else {
278 port->ctrl &= ~OHCI_PORT_LSDA;
279 }
280
281 /* notify of remote-wakeup */
282 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
283 ohci_set_interrupt(s, OHCI_INTR_RD);
284 }
285
286 trace_usb_ohci_port_attach(port1->index);
287
288 if (old_state != port->ctrl) {
289 ohci_set_interrupt(s, OHCI_INTR_RHSC);
290 }
291 }
292
293 static void ohci_detach(USBPort *port1)
294 {
295 OHCIState *s = port1->opaque;
296 OHCIPort *port = &s->rhport[port1->index];
297 uint32_t old_state = port->ctrl;
298
299 ohci_async_cancel_device(s, port1->dev);
300
301 /* set connect status */
302 if (port->ctrl & OHCI_PORT_CCS) {
303 port->ctrl &= ~OHCI_PORT_CCS;
304 port->ctrl |= OHCI_PORT_CSC;
305 }
306 /* disable port */
307 if (port->ctrl & OHCI_PORT_PES) {
308 port->ctrl &= ~OHCI_PORT_PES;
309 port->ctrl |= OHCI_PORT_PESC;
310 }
311 trace_usb_ohci_port_detach(port1->index);
312
313 if (old_state != port->ctrl) {
314 ohci_set_interrupt(s, OHCI_INTR_RHSC);
315 }
316 }
317
318 static void ohci_wakeup(USBPort *port1)
319 {
320 OHCIState *s = port1->opaque;
321 OHCIPort *port = &s->rhport[port1->index];
322 uint32_t intr = 0;
323 if (port->ctrl & OHCI_PORT_PSS) {
324 trace_usb_ohci_port_wakeup(port1->index);
325 port->ctrl |= OHCI_PORT_PSSC;
326 port->ctrl &= ~OHCI_PORT_PSS;
327 intr = OHCI_INTR_RHSC;
328 }
329 /* Note that the controller can be suspended even if this port is not */
330 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
331 trace_usb_ohci_remote_wakeup(s->name);
332 /* This is the one state transition the controller can do by itself */
333 s->ctl &= ~OHCI_CTL_HCFS;
334 s->ctl |= OHCI_USB_RESUME;
335 /* In suspend mode only ResumeDetected is possible, not RHSC:
336 * see the OHCI spec 5.1.2.3.
337 */
338 intr = OHCI_INTR_RD;
339 }
340 ohci_set_interrupt(s, intr);
341 }
342
343 static void ohci_child_detach(USBPort *port1, USBDevice *child)
344 {
345 OHCIState *s = port1->opaque;
346
347 ohci_async_cancel_device(s, child);
348 }
349
350 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr)
351 {
352 USBDevice *dev;
353 int i;
354
355 for (i = 0; i < ohci->num_ports; i++) {
356 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) {
357 continue;
358 }
359 dev = usb_find_device(&ohci->rhport[i].port, addr);
360 if (dev != NULL) {
361 return dev;
362 }
363 }
364 return NULL;
365 }
366
367 void ohci_stop_endpoints(OHCIState *ohci)
368 {
369 USBDevice *dev;
370 int i, j;
371
372 for (i = 0; i < ohci->num_ports; i++) {
373 dev = ohci->rhport[i].port.dev;
374 if (dev && dev->attached) {
375 usb_device_ep_stopped(dev, &dev->ep_ctl);
376 for (j = 0; j < USB_MAX_ENDPOINTS; j++) {
377 usb_device_ep_stopped(dev, &dev->ep_in[j]);
378 usb_device_ep_stopped(dev, &dev->ep_out[j]);
379 }
380 }
381 }
382 }
383
384 static void ohci_roothub_reset(OHCIState *ohci)
385 {
386 OHCIPort *port;
387 int i;
388
389 ohci_bus_stop(ohci);
390 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
391 ohci->rhdesc_b = 0x0; /* Impl. specific */
392 ohci->rhstatus = 0;
393
394 for (i = 0; i < ohci->num_ports; i++) {
395 port = &ohci->rhport[i];
396 port->ctrl = 0;
397 if (port->port.dev && port->port.dev->attached) {
398 usb_port_reset(&port->port);
399 }
400 }
401 if (ohci->async_td) {
402 usb_cancel_packet(&ohci->usb_packet);
403 ohci->async_td = 0;
404 }
405 ohci_stop_endpoints(ohci);
406 }
407
408 /* Reset the controller */
409 static void ohci_soft_reset(OHCIState *ohci)
410 {
411 trace_usb_ohci_reset(ohci->name);
412
413 ohci_bus_stop(ohci);
414 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND;
415 ohci->old_ctl = 0;
416 ohci->status = 0;
417 ohci->intr_status = 0;
418 ohci->intr = OHCI_INTR_MIE;
419
420 ohci->hcca = 0;
421 ohci->ctrl_head = ohci->ctrl_cur = 0;
422 ohci->bulk_head = ohci->bulk_cur = 0;
423 ohci->per_cur = 0;
424 ohci->done = 0;
425 ohci->done_count = 7;
426
427 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
428 * I took the value linux sets ...
429 */
430 ohci->fsmps = 0x2778;
431 ohci->fi = 0x2edf;
432 ohci->fit = 0;
433 ohci->frt = 0;
434 ohci->frame_number = 0;
435 ohci->pstart = 0;
436 ohci->lst = OHCI_LS_THRESH;
437 }
438
439 void ohci_hard_reset(OHCIState *ohci)
440 {
441 ohci_soft_reset(ohci);
442 ohci->ctl = 0;
443 ohci_roothub_reset(ohci);
444 }
445
446 /* Get an array of dwords from main memory */
447 static inline int get_dwords(OHCIState *ohci,
448 dma_addr_t addr, uint32_t *buf, int num)
449 {
450 int i;
451
452 addr += ohci->localmem_base;
453
454 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
455 if (dma_memory_read(ohci->as, addr,
456 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
457 return -1;
458 }
459 *buf = le32_to_cpu(*buf);
460 }
461
462 return 0;
463 }
464
465 /* Put an array of dwords in to main memory */
466 static inline int put_dwords(OHCIState *ohci,
467 dma_addr_t addr, uint32_t *buf, int num)
468 {
469 int i;
470
471 addr += ohci->localmem_base;
472
473 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
474 uint32_t tmp = cpu_to_le32(*buf);
475 if (dma_memory_write(ohci->as, addr,
476 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
477 return -1;
478 }
479 }
480
481 return 0;
482 }
483
484 /* Get an array of words from main memory */
485 static inline int get_words(OHCIState *ohci,
486 dma_addr_t addr, uint16_t *buf, int num)
487 {
488 int i;
489
490 addr += ohci->localmem_base;
491
492 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
493 if (dma_memory_read(ohci->as, addr,
494 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
495 return -1;
496 }
497 *buf = le16_to_cpu(*buf);
498 }
499
500 return 0;
501 }
502
503 /* Put an array of words in to main memory */
504 static inline int put_words(OHCIState *ohci,
505 dma_addr_t addr, uint16_t *buf, int num)
506 {
507 int i;
508
509 addr += ohci->localmem_base;
510
511 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
512 uint16_t tmp = cpu_to_le16(*buf);
513 if (dma_memory_write(ohci->as, addr,
514 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
515 return -1;
516 }
517 }
518
519 return 0;
520 }
521
522 static inline int ohci_read_ed(OHCIState *ohci,
523 dma_addr_t addr, struct ohci_ed *ed)
524 {
525 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
526 }
527
528 static inline int ohci_read_td(OHCIState *ohci,
529 dma_addr_t addr, struct ohci_td *td)
530 {
531 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
532 }
533
534 static inline int ohci_read_iso_td(OHCIState *ohci,
535 dma_addr_t addr, struct ohci_iso_td *td)
536 {
537 return get_dwords(ohci, addr, (uint32_t *)td, 4) ||
538 get_words(ohci, addr + 16, td->offset, 8);
539 }
540
541 static inline int ohci_read_hcca(OHCIState *ohci,
542 dma_addr_t addr, struct ohci_hcca *hcca)
543 {
544 return dma_memory_read(ohci->as, addr + ohci->localmem_base, hcca,
545 sizeof(*hcca), MEMTXATTRS_UNSPECIFIED);
546 }
547
548 static inline int ohci_put_ed(OHCIState *ohci,
549 dma_addr_t addr, struct ohci_ed *ed)
550 {
551 /* ed->tail is under control of the HCD.
552 * Since just ed->head is changed by HC, just write back this
553 */
554
555 return put_dwords(ohci, addr + ED_WBACK_OFFSET,
556 (uint32_t *)((char *)ed + ED_WBACK_OFFSET),
557 ED_WBACK_SIZE >> 2);
558 }
559
560 static inline int ohci_put_td(OHCIState *ohci,
561 dma_addr_t addr, struct ohci_td *td)
562 {
563 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
564 }
565
566 static inline int ohci_put_iso_td(OHCIState *ohci,
567 dma_addr_t addr, struct ohci_iso_td *td)
568 {
569 return put_dwords(ohci, addr, (uint32_t *)td, 4) ||
570 put_words(ohci, addr + 16, td->offset, 8);
571 }
572
573 static inline int ohci_put_hcca(OHCIState *ohci,
574 dma_addr_t addr, struct ohci_hcca *hcca)
575 {
576 return dma_memory_write(ohci->as,
577 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET,
578 (char *)hcca + HCCA_WRITEBACK_OFFSET,
579 HCCA_WRITEBACK_SIZE, MEMTXATTRS_UNSPECIFIED);
580 }
581
582 /* Read/Write the contents of a TD from/to main memory. */
583 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
584 uint8_t *buf, int len, DMADirection dir)
585 {
586 dma_addr_t ptr, n;
587
588 ptr = td->cbp;
589 n = 0x1000 - (ptr & 0xfff);
590 if (n > len)
591 n = len;
592
593 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
594 n, dir, MEMTXATTRS_UNSPECIFIED)) {
595 return -1;
596 }
597 if (n == len) {
598 return 0;
599 }
600 ptr = td->be & ~0xfffu;
601 buf += n;
602 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
603 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
604 return -1;
605 }
606 return 0;
607 }
608
609 /* Read/Write the contents of an ISO TD from/to main memory. */
610 static int ohci_copy_iso_td(OHCIState *ohci,
611 uint32_t start_addr, uint32_t end_addr,
612 uint8_t *buf, int len, DMADirection dir)
613 {
614 dma_addr_t ptr, n;
615
616 ptr = start_addr;
617 n = 0x1000 - (ptr & 0xfff);
618 if (n > len)
619 n = len;
620
621 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
622 n, dir, MEMTXATTRS_UNSPECIFIED)) {
623 return -1;
624 }
625 if (n == len) {
626 return 0;
627 }
628 ptr = end_addr & ~0xfffu;
629 buf += n;
630 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
631 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
632 return -1;
633 }
634 return 0;
635 }
636
637 static void ohci_process_lists(OHCIState *ohci, int completion);
638
639 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
640 {
641 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
642
643 trace_usb_ohci_async_complete();
644 ohci->async_complete = true;
645 ohci_process_lists(ohci, 1);
646 }
647
648 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
649
650 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
651 int completion)
652 {
653 int dir;
654 size_t len = 0;
655 const char *str = NULL;
656 int pid;
657 int ret;
658 int i;
659 USBDevice *dev;
660 USBEndpoint *ep;
661 struct ohci_iso_td iso_td;
662 uint32_t addr;
663 uint16_t starting_frame;
664 int16_t relative_frame_number;
665 int frame_count;
666 uint32_t start_offset, next_offset, end_offset = 0;
667 uint32_t start_addr, end_addr;
668
669 addr = ed->head & OHCI_DPTR_MASK;
670
671 if (ohci_read_iso_td(ohci, addr, &iso_td)) {
672 trace_usb_ohci_iso_td_read_failed(addr);
673 ohci_die(ohci);
674 return 1;
675 }
676
677 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
678 frame_count = OHCI_BM(iso_td.flags, TD_FC);
679 relative_frame_number = USUB(ohci->frame_number, starting_frame);
680
681 trace_usb_ohci_iso_td_head(
682 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
683 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
684 ohci->frame_number, starting_frame,
685 frame_count, relative_frame_number);
686 trace_usb_ohci_iso_td_head_offset(
687 iso_td.offset[0], iso_td.offset[1],
688 iso_td.offset[2], iso_td.offset[3],
689 iso_td.offset[4], iso_td.offset[5],
690 iso_td.offset[6], iso_td.offset[7]);
691
692 if (relative_frame_number < 0) {
693 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number);
694 return 1;
695 } else if (relative_frame_number > frame_count) {
696 /* ISO TD expired - retire the TD to the Done Queue and continue with
697 the next ISO TD of the same ED */
698 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number,
699 frame_count);
700 if (OHCI_CC_DATAOVERRUN == OHCI_BM(iso_td.flags, TD_CC)) {
701 /* avoid infinite loop */
702 return 1;
703 }
704 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
705 ed->head &= ~OHCI_DPTR_MASK;
706 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
707 iso_td.next = ohci->done;
708 ohci->done = addr;
709 i = OHCI_BM(iso_td.flags, TD_DI);
710 if (i < ohci->done_count)
711 ohci->done_count = i;
712 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
713 ohci_die(ohci);
714 return 1;
715 }
716 return 0;
717 }
718
719 dir = OHCI_BM(ed->flags, ED_D);
720 switch (dir) {
721 case OHCI_TD_DIR_IN:
722 str = "in";
723 pid = USB_TOKEN_IN;
724 break;
725 case OHCI_TD_DIR_OUT:
726 str = "out";
727 pid = USB_TOKEN_OUT;
728 break;
729 case OHCI_TD_DIR_SETUP:
730 str = "setup";
731 pid = USB_TOKEN_SETUP;
732 break;
733 default:
734 trace_usb_ohci_iso_td_bad_direction(dir);
735 return 1;
736 }
737
738 if (!iso_td.bp || !iso_td.be) {
739 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be);
740 return 1;
741 }
742
743 start_offset = iso_td.offset[relative_frame_number];
744 if (relative_frame_number < frame_count) {
745 next_offset = iso_td.offset[relative_frame_number + 1];
746 } else {
747 next_offset = iso_td.be;
748 }
749
750 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
751 ((relative_frame_number < frame_count) &&
752 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
753 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset);
754 return 1;
755 }
756
757 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
758 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset);
759 return 1;
760 }
761
762 if ((start_offset & 0x1000) == 0) {
763 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
764 (start_offset & OHCI_OFFSET_MASK);
765 } else {
766 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
767 (start_offset & OHCI_OFFSET_MASK);
768 }
769
770 if (relative_frame_number < frame_count) {
771 end_offset = next_offset - 1;
772 if ((end_offset & 0x1000) == 0) {
773 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
774 (end_offset & OHCI_OFFSET_MASK);
775 } else {
776 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
777 (end_offset & OHCI_OFFSET_MASK);
778 }
779 } else {
780 /* Last packet in the ISO TD */
781 end_addr = next_offset;
782 }
783
784 if (start_addr > end_addr) {
785 trace_usb_ohci_iso_td_bad_cc_overrun(start_addr, end_addr);
786 return 1;
787 }
788
789 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
790 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
791 - (start_addr & OHCI_OFFSET_MASK);
792 } else {
793 len = end_addr - start_addr + 1;
794 }
795 if (len > sizeof(ohci->usb_buf)) {
796 len = sizeof(ohci->usb_buf);
797 }
798
799 if (len && dir != OHCI_TD_DIR_IN) {
800 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len,
801 DMA_DIRECTION_TO_DEVICE)) {
802 ohci_die(ohci);
803 return 1;
804 }
805 }
806
807 if (!completion) {
808 bool int_req = relative_frame_number == frame_count &&
809 OHCI_BM(iso_td.flags, TD_DI) == 0;
810 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
811 if (dev == NULL) {
812 trace_usb_ohci_td_dev_error();
813 return 1;
814 }
815 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
816 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, false, int_req);
817 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len);
818 usb_handle_packet(dev, &ohci->usb_packet);
819 if (ohci->usb_packet.status == USB_RET_ASYNC) {
820 usb_device_flush_ep_queue(dev, ep);
821 return 1;
822 }
823 }
824 if (ohci->usb_packet.status == USB_RET_SUCCESS) {
825 ret = ohci->usb_packet.actual_length;
826 } else {
827 ret = ohci->usb_packet.status;
828 }
829
830 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr,
831 str, len, ret);
832
833 /* Writeback */
834 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
835 /* IN transfer succeeded */
836 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret,
837 DMA_DIRECTION_FROM_DEVICE)) {
838 ohci_die(ohci);
839 return 1;
840 }
841 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
842 OHCI_CC_NOERROR);
843 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
844 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
845 /* OUT transfer succeeded */
846 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
847 OHCI_CC_NOERROR);
848 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
849 } else {
850 if (ret > (ssize_t) len) {
851 trace_usb_ohci_iso_td_data_overrun(ret, len);
852 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
853 OHCI_CC_DATAOVERRUN);
854 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
855 len);
856 } else if (ret >= 0) {
857 trace_usb_ohci_iso_td_data_underrun(ret);
858 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
859 OHCI_CC_DATAUNDERRUN);
860 } else {
861 switch (ret) {
862 case USB_RET_IOERROR:
863 case USB_RET_NODEV:
864 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
865 OHCI_CC_DEVICENOTRESPONDING);
866 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
867 0);
868 break;
869 case USB_RET_NAK:
870 case USB_RET_STALL:
871 trace_usb_ohci_iso_td_nak(ret);
872 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
873 OHCI_CC_STALL);
874 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
875 0);
876 break;
877 default:
878 trace_usb_ohci_iso_td_bad_response(ret);
879 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
880 OHCI_CC_UNDEXPETEDPID);
881 break;
882 }
883 }
884 }
885
886 if (relative_frame_number == frame_count) {
887 /* Last data packet of ISO TD - retire the TD to the Done Queue */
888 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
889 ed->head &= ~OHCI_DPTR_MASK;
890 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
891 iso_td.next = ohci->done;
892 ohci->done = addr;
893 i = OHCI_BM(iso_td.flags, TD_DI);
894 if (i < ohci->done_count)
895 ohci->done_count = i;
896 }
897 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
898 ohci_die(ohci);
899 }
900 return 1;
901 }
902
903 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
904 {
905 bool print16;
906 bool printall;
907 const int width = 16;
908 int i;
909 char tmp[3 * width + 1];
910 char *p = tmp;
911
912 print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
913 printall = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL);
914
915 if (!printall && !print16) {
916 return;
917 }
918
919 for (i = 0; ; i++) {
920 if (i && (!(i % width) || (i == len))) {
921 if (!printall) {
922 trace_usb_ohci_td_pkt_short(msg, tmp);
923 break;
924 }
925 trace_usb_ohci_td_pkt_full(msg, tmp);
926 p = tmp;
927 *p = 0;
928 }
929 if (i == len) {
930 break;
931 }
932
933 p += sprintf(p, " %.2x", buf[i]);
934 }
935 }
936
937 /* Service a transport descriptor.
938 Returns nonzero to terminate processing of this endpoint. */
939
940 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
941 {
942 int dir;
943 size_t len = 0, pktlen = 0;
944 const char *str = NULL;
945 int pid;
946 int ret;
947 int i;
948 USBDevice *dev;
949 USBEndpoint *ep;
950 struct ohci_td td;
951 uint32_t addr;
952 int flag_r;
953 int completion;
954
955 addr = ed->head & OHCI_DPTR_MASK;
956 /* See if this TD has already been submitted to the device. */
957 completion = (addr == ohci->async_td);
958 if (completion && !ohci->async_complete) {
959 trace_usb_ohci_td_skip_async();
960 return 1;
961 }
962 if (ohci_read_td(ohci, addr, &td)) {
963 trace_usb_ohci_td_read_error(addr);
964 ohci_die(ohci);
965 return 1;
966 }
967
968 dir = OHCI_BM(ed->flags, ED_D);
969 switch (dir) {
970 case OHCI_TD_DIR_OUT:
971 case OHCI_TD_DIR_IN:
972 /* Same value. */
973 break;
974 default:
975 dir = OHCI_BM(td.flags, TD_DP);
976 break;
977 }
978
979 switch (dir) {
980 case OHCI_TD_DIR_IN:
981 str = "in";
982 pid = USB_TOKEN_IN;
983 break;
984 case OHCI_TD_DIR_OUT:
985 str = "out";
986 pid = USB_TOKEN_OUT;
987 break;
988 case OHCI_TD_DIR_SETUP:
989 str = "setup";
990 pid = USB_TOKEN_SETUP;
991 break;
992 default:
993 trace_usb_ohci_td_bad_direction(dir);
994 return 1;
995 }
996 if (td.cbp && td.be) {
997 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
998 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
999 } else {
1000 if (td.cbp > td.be) {
1001 trace_usb_ohci_iso_td_bad_cc_overrun(td.cbp, td.be);
1002 ohci_die(ohci);
1003 return 1;
1004 }
1005 len = (td.be - td.cbp) + 1;
1006 }
1007 if (len > sizeof(ohci->usb_buf)) {
1008 len = sizeof(ohci->usb_buf);
1009 }
1010
1011 pktlen = len;
1012 if (len && dir != OHCI_TD_DIR_IN) {
1013 /* The endpoint may not allow us to transfer it all now */
1014 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT;
1015 if (pktlen > len) {
1016 pktlen = len;
1017 }
1018 if (!completion) {
1019 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen,
1020 DMA_DIRECTION_TO_DEVICE)) {
1021 ohci_die(ohci);
1022 }
1023 }
1024 }
1025 }
1026
1027 flag_r = (td.flags & OHCI_TD_R) != 0;
1028 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str,
1029 flag_r, td.cbp, td.be);
1030 ohci_td_pkt("OUT", ohci->usb_buf, pktlen);
1031
1032 if (completion) {
1033 ohci->async_td = 0;
1034 ohci->async_complete = false;
1035 } else {
1036 if (ohci->async_td) {
1037 /* ??? The hardware should allow one active packet per
1038 endpoint. We only allow one active packet per controller.
1039 This should be sufficient as long as devices respond in a
1040 timely manner.
1041 */
1042 trace_usb_ohci_td_too_many_pending();
1043 return 1;
1044 }
1045 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
1046 if (dev == NULL) {
1047 trace_usb_ohci_td_dev_error();
1048 return 1;
1049 }
1050 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
1051 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r,
1052 OHCI_BM(td.flags, TD_DI) == 0);
1053 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen);
1054 usb_handle_packet(dev, &ohci->usb_packet);
1055 trace_usb_ohci_td_packet_status(ohci->usb_packet.status);
1056
1057 if (ohci->usb_packet.status == USB_RET_ASYNC) {
1058 usb_device_flush_ep_queue(dev, ep);
1059 ohci->async_td = addr;
1060 return 1;
1061 }
1062 }
1063 if (ohci->usb_packet.status == USB_RET_SUCCESS) {
1064 ret = ohci->usb_packet.actual_length;
1065 } else {
1066 ret = ohci->usb_packet.status;
1067 }
1068
1069 if (ret >= 0) {
1070 if (dir == OHCI_TD_DIR_IN) {
1071 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret,
1072 DMA_DIRECTION_FROM_DEVICE)) {
1073 ohci_die(ohci);
1074 }
1075 ohci_td_pkt("IN", ohci->usb_buf, pktlen);
1076 } else {
1077 ret = pktlen;
1078 }
1079 }
1080
1081 /* Writeback */
1082 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
1083 /* Transmission succeeded. */
1084 if (ret == len) {
1085 td.cbp = 0;
1086 } else {
1087 if ((td.cbp & 0xfff) + ret > 0xfff) {
1088 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff);
1089 } else {
1090 td.cbp += ret;
1091 }
1092 }
1093 td.flags |= OHCI_TD_T1;
1094 td.flags ^= OHCI_TD_T0;
1095 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1096 OHCI_SET_BM(td.flags, TD_EC, 0);
1097
1098 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) {
1099 /* Partial packet transfer: TD not ready to retire yet */
1100 goto exit_no_retire;
1101 }
1102
1103 /* Setting ED_C is part of the TD retirement process */
1104 ed->head &= ~OHCI_ED_C;
1105 if (td.flags & OHCI_TD_T0)
1106 ed->head |= OHCI_ED_C;
1107 } else {
1108 if (ret >= 0) {
1109 trace_usb_ohci_td_underrun();
1110 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1111 } else {
1112 switch (ret) {
1113 case USB_RET_IOERROR:
1114 case USB_RET_NODEV:
1115 trace_usb_ohci_td_dev_error();
1116 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1117 break;
1118 case USB_RET_NAK:
1119 trace_usb_ohci_td_nak();
1120 return 1;
1121 case USB_RET_STALL:
1122 trace_usb_ohci_td_stall();
1123 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1124 break;
1125 case USB_RET_BABBLE:
1126 trace_usb_ohci_td_babble();
1127 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1128 break;
1129 default:
1130 trace_usb_ohci_td_bad_device_response(ret);
1131 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1132 OHCI_SET_BM(td.flags, TD_EC, 3);
1133 break;
1134 }
1135 /* An error occurred so we have to clear the interrupt counter. See
1136 * spec at 6.4.4 on page 104 */
1137 ohci->done_count = 0;
1138 }
1139 ed->head |= OHCI_ED_H;
1140 }
1141
1142 /* Retire this TD */
1143 ed->head &= ~OHCI_DPTR_MASK;
1144 ed->head |= td.next & OHCI_DPTR_MASK;
1145 td.next = ohci->done;
1146 ohci->done = addr;
1147 i = OHCI_BM(td.flags, TD_DI);
1148 if (i < ohci->done_count)
1149 ohci->done_count = i;
1150 exit_no_retire:
1151 if (ohci_put_td(ohci, addr, &td)) {
1152 ohci_die(ohci);
1153 return 1;
1154 }
1155 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1156 }
1157
1158 /* Service an endpoint list. Returns nonzero if active TD were found. */
1159 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1160 {
1161 struct ohci_ed ed;
1162 uint32_t next_ed;
1163 uint32_t cur;
1164 int active;
1165 uint32_t link_cnt = 0;
1166 active = 0;
1167
1168 if (head == 0)
1169 return 0;
1170
1171 for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) {
1172 if (ohci_read_ed(ohci, cur, &ed)) {
1173 trace_usb_ohci_ed_read_error(cur);
1174 ohci_die(ohci);
1175 return 0;
1176 }
1177
1178 next_ed = ed.next & OHCI_DPTR_MASK;
1179
1180 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1181 uint32_t addr;
1182 /* Cancel pending packets for ED that have been paused. */
1183 addr = ed.head & OHCI_DPTR_MASK;
1184 if (ohci->async_td && addr == ohci->async_td) {
1185 usb_cancel_packet(&ohci->usb_packet);
1186 ohci->async_td = 0;
1187 usb_device_ep_stopped(ohci->usb_packet.ep->dev,
1188 ohci->usb_packet.ep);
1189 }
1190 continue;
1191 }
1192
1193 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1194 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0,
1195 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1196 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1197 trace_usb_ohci_ed_pkt_flags(
1198 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1199 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1200 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1201 OHCI_BM(ed.flags, ED_MPS));
1202
1203 active = 1;
1204
1205 if ((ed.flags & OHCI_ED_F) == 0) {
1206 if (ohci_service_td(ohci, &ed))
1207 break;
1208 } else {
1209 /* Handle isochronous endpoints */
1210 if (ohci_service_iso_td(ohci, &ed, completion))
1211 break;
1212 }
1213 }
1214
1215 if (ohci_put_ed(ohci, cur, &ed)) {
1216 ohci_die(ohci);
1217 return 0;
1218 }
1219 }
1220
1221 return active;
1222 }
1223
1224 /* set a timer for EOF */
1225 static void ohci_eof_timer(OHCIState *ohci)
1226 {
1227 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1228 }
1229 /* Set a timer for EOF and generate a SOF event */
1230 static void ohci_sof(OHCIState *ohci)
1231 {
1232 ohci->sof_time += usb_frame_time;
1233 ohci_eof_timer(ohci);
1234 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1235 }
1236
1237 /* Process Control and Bulk lists. */
1238 static void ohci_process_lists(OHCIState *ohci, int completion)
1239 {
1240 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1241 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1242 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur);
1243 }
1244 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1245 ohci->ctrl_cur = 0;
1246 ohci->status &= ~OHCI_STATUS_CLF;
1247 }
1248 }
1249
1250 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1251 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1252 ohci->bulk_cur = 0;
1253 ohci->status &= ~OHCI_STATUS_BLF;
1254 }
1255 }
1256 }
1257
1258 /* Do frame processing on frame boundary */
1259 static void ohci_frame_boundary(void *opaque)
1260 {
1261 OHCIState *ohci = opaque;
1262 struct ohci_hcca hcca;
1263
1264 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) {
1265 trace_usb_ohci_hcca_read_error(ohci->hcca);
1266 ohci_die(ohci);
1267 return;
1268 }
1269
1270 /* Process all the lists at the end of the frame */
1271 if (ohci->ctl & OHCI_CTL_PLE) {
1272 int n;
1273
1274 n = ohci->frame_number & 0x1f;
1275 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1276 }
1277
1278 /* Cancel all pending packets if either of the lists has been disabled. */
1279 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1280 if (ohci->async_td) {
1281 usb_cancel_packet(&ohci->usb_packet);
1282 ohci->async_td = 0;
1283 }
1284 ohci_stop_endpoints(ohci);
1285 }
1286 ohci->old_ctl = ohci->ctl;
1287 ohci_process_lists(ohci, 0);
1288
1289 /* Stop if UnrecoverableError happened or ohci_sof will crash */
1290 if (ohci->intr_status & OHCI_INTR_UE) {
1291 return;
1292 }
1293
1294 /* Frame boundary, so do EOF stuf here */
1295 ohci->frt = ohci->fit;
1296
1297 /* Increment frame number and take care of endianness. */
1298 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1299 hcca.frame = cpu_to_le16(ohci->frame_number);
1300
1301 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1302 if (!ohci->done)
1303 abort();
1304 if (ohci->intr & ohci->intr_status)
1305 ohci->done |= 1;
1306 hcca.done = cpu_to_le32(ohci->done);
1307 ohci->done = 0;
1308 ohci->done_count = 7;
1309 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1310 }
1311
1312 if (ohci->done_count != 7 && ohci->done_count != 0)
1313 ohci->done_count--;
1314
1315 /* Do SOF stuff here */
1316 ohci_sof(ohci);
1317
1318 /* Writeback HCCA */
1319 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) {
1320 ohci_die(ohci);
1321 }
1322 }
1323
1324 /* Start sending SOF tokens across the USB bus, lists are processed in
1325 * next frame
1326 */
1327 static int ohci_bus_start(OHCIState *ohci)
1328 {
1329 trace_usb_ohci_start(ohci->name);
1330
1331 /* Delay the first SOF event by one frame time as
1332 * linux driver is not ready to receive it and
1333 * can meet some race conditions
1334 */
1335
1336 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1337 ohci_eof_timer(ohci);
1338
1339 return 1;
1340 }
1341
1342 /* Stop sending SOF tokens on the bus */
1343 void ohci_bus_stop(OHCIState *ohci)
1344 {
1345 trace_usb_ohci_stop(ohci->name);
1346 timer_del(ohci->eof_timer);
1347 }
1348
1349 /* Sets a flag in a port status register but only set it if the port is
1350 * connected, if not set ConnectStatusChange flag. If flag is enabled
1351 * return 1.
1352 */
1353 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1354 {
1355 int ret = 1;
1356
1357 /* writing a 0 has no effect */
1358 if (val == 0)
1359 return 0;
1360
1361 /* If CurrentConnectStatus is cleared we set
1362 * ConnectStatusChange
1363 */
1364 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1365 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1366 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1367 /* TODO: CSC is a wakeup event */
1368 }
1369 return 0;
1370 }
1371
1372 if (ohci->rhport[i].ctrl & val)
1373 ret = 0;
1374
1375 /* set the bit */
1376 ohci->rhport[i].ctrl |= val;
1377
1378 return ret;
1379 }
1380
1381 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1382 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1383 {
1384 val &= OHCI_FMI_FI;
1385
1386 if (val != ohci->fi) {
1387 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi);
1388 }
1389
1390 ohci->fi = val;
1391 }
1392
1393 static void ohci_port_power(OHCIState *ohci, int i, int p)
1394 {
1395 if (p) {
1396 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1397 } else {
1398 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1399 OHCI_PORT_CCS|
1400 OHCI_PORT_PSS|
1401 OHCI_PORT_PRS);
1402 }
1403 }
1404
1405 /* Set HcControlRegister */
1406 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1407 {
1408 uint32_t old_state;
1409 uint32_t new_state;
1410
1411 old_state = ohci->ctl & OHCI_CTL_HCFS;
1412 ohci->ctl = val;
1413 new_state = ohci->ctl & OHCI_CTL_HCFS;
1414
1415 /* no state change */
1416 if (old_state == new_state)
1417 return;
1418
1419 trace_usb_ohci_set_ctl(ohci->name, new_state);
1420 switch (new_state) {
1421 case OHCI_USB_OPERATIONAL:
1422 ohci_bus_start(ohci);
1423 break;
1424 case OHCI_USB_SUSPEND:
1425 ohci_bus_stop(ohci);
1426 /* clear pending SF otherwise linux driver loops in ohci_irq() */
1427 ohci->intr_status &= ~OHCI_INTR_SF;
1428 ohci_intr_update(ohci);
1429 break;
1430 case OHCI_USB_RESUME:
1431 trace_usb_ohci_resume(ohci->name);
1432 break;
1433 case OHCI_USB_RESET:
1434 ohci_roothub_reset(ohci);
1435 break;
1436 }
1437 }
1438
1439 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1440 {
1441 uint16_t fr;
1442 int64_t tks;
1443
1444 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1445 return (ohci->frt << 31);
1446
1447 /* Being in USB operational state guarnatees sof_time was
1448 * set already.
1449 */
1450 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time;
1451 if (tks < 0) {
1452 tks = 0;
1453 }
1454
1455 /* avoid muldiv if possible */
1456 if (tks >= usb_frame_time)
1457 return (ohci->frt << 31);
1458
1459 tks = tks / usb_bit_time;
1460 fr = (uint16_t)(ohci->fi - tks);
1461
1462 return (ohci->frt << 31) | fr;
1463 }
1464
1465
1466 /* Set root hub status */
1467 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1468 {
1469 uint32_t old_state;
1470
1471 old_state = ohci->rhstatus;
1472
1473 /* write 1 to clear OCIC */
1474 if (val & OHCI_RHS_OCIC)
1475 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1476
1477 if (val & OHCI_RHS_LPS) {
1478 int i;
1479
1480 for (i = 0; i < ohci->num_ports; i++)
1481 ohci_port_power(ohci, i, 0);
1482 trace_usb_ohci_hub_power_down();
1483 }
1484
1485 if (val & OHCI_RHS_LPSC) {
1486 int i;
1487
1488 for (i = 0; i < ohci->num_ports; i++)
1489 ohci_port_power(ohci, i, 1);
1490 trace_usb_ohci_hub_power_up();
1491 }
1492
1493 if (val & OHCI_RHS_DRWE)
1494 ohci->rhstatus |= OHCI_RHS_DRWE;
1495
1496 if (val & OHCI_RHS_CRWE)
1497 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1498
1499 if (old_state != ohci->rhstatus)
1500 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1501 }
1502
1503 /* Set root hub port status */
1504 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1505 {
1506 uint32_t old_state;
1507 OHCIPort *port;
1508
1509 port = &ohci->rhport[portnum];
1510 old_state = port->ctrl;
1511
1512 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1513 if (val & OHCI_PORT_WTC)
1514 port->ctrl &= ~(val & OHCI_PORT_WTC);
1515
1516 if (val & OHCI_PORT_CCS)
1517 port->ctrl &= ~OHCI_PORT_PES;
1518
1519 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1520
1521 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1522 trace_usb_ohci_port_suspend(portnum);
1523 }
1524
1525 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1526 trace_usb_ohci_port_reset(portnum);
1527 usb_device_reset(port->port.dev);
1528 port->ctrl &= ~OHCI_PORT_PRS;
1529 /* ??? Should this also set OHCI_PORT_PESC. */
1530 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1531 }
1532
1533 /* Invert order here to ensure in ambiguous case, device is
1534 * powered up...
1535 */
1536 if (val & OHCI_PORT_LSDA)
1537 ohci_port_power(ohci, portnum, 0);
1538 if (val & OHCI_PORT_PPS)
1539 ohci_port_power(ohci, portnum, 1);
1540
1541 if (old_state != port->ctrl)
1542 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1543 }
1544
1545 static uint64_t ohci_mem_read(void *opaque,
1546 hwaddr addr,
1547 unsigned size)
1548 {
1549 OHCIState *ohci = opaque;
1550 uint32_t retval;
1551
1552 /* Only aligned reads are allowed on OHCI */
1553 if (addr & 3) {
1554 trace_usb_ohci_mem_read_unaligned(addr);
1555 return 0xffffffff;
1556 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1557 /* HcRhPortStatus */
1558 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1559 } else {
1560 switch (addr >> 2) {
1561 case 0: /* HcRevision */
1562 retval = 0x10;
1563 break;
1564
1565 case 1: /* HcControl */
1566 retval = ohci->ctl;
1567 break;
1568
1569 case 2: /* HcCommandStatus */
1570 retval = ohci->status;
1571 break;
1572
1573 case 3: /* HcInterruptStatus */
1574 retval = ohci->intr_status;
1575 break;
1576
1577 case 4: /* HcInterruptEnable */
1578 case 5: /* HcInterruptDisable */
1579 retval = ohci->intr;
1580 break;
1581
1582 case 6: /* HcHCCA */
1583 retval = ohci->hcca;
1584 break;
1585
1586 case 7: /* HcPeriodCurrentED */
1587 retval = ohci->per_cur;
1588 break;
1589
1590 case 8: /* HcControlHeadED */
1591 retval = ohci->ctrl_head;
1592 break;
1593
1594 case 9: /* HcControlCurrentED */
1595 retval = ohci->ctrl_cur;
1596 break;
1597
1598 case 10: /* HcBulkHeadED */
1599 retval = ohci->bulk_head;
1600 break;
1601
1602 case 11: /* HcBulkCurrentED */
1603 retval = ohci->bulk_cur;
1604 break;
1605
1606 case 12: /* HcDoneHead */
1607 retval = ohci->done;
1608 break;
1609
1610 case 13: /* HcFmInterretval */
1611 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1612 break;
1613
1614 case 14: /* HcFmRemaining */
1615 retval = ohci_get_frame_remaining(ohci);
1616 break;
1617
1618 case 15: /* HcFmNumber */
1619 retval = ohci->frame_number;
1620 break;
1621
1622 case 16: /* HcPeriodicStart */
1623 retval = ohci->pstart;
1624 break;
1625
1626 case 17: /* HcLSThreshold */
1627 retval = ohci->lst;
1628 break;
1629
1630 case 18: /* HcRhDescriptorA */
1631 retval = ohci->rhdesc_a;
1632 break;
1633
1634 case 19: /* HcRhDescriptorB */
1635 retval = ohci->rhdesc_b;
1636 break;
1637
1638 case 20: /* HcRhStatus */
1639 retval = ohci->rhstatus;
1640 break;
1641
1642 /* PXA27x specific registers */
1643 case 24: /* HcStatus */
1644 retval = ohci->hstatus & ohci->hmask;
1645 break;
1646
1647 case 25: /* HcHReset */
1648 retval = ohci->hreset;
1649 break;
1650
1651 case 26: /* HcHInterruptEnable */
1652 retval = ohci->hmask;
1653 break;
1654
1655 case 27: /* HcHInterruptTest */
1656 retval = ohci->htest;
1657 break;
1658
1659 default:
1660 trace_usb_ohci_mem_read_bad_offset(addr);
1661 retval = 0xffffffff;
1662 }
1663 }
1664
1665 return retval;
1666 }
1667
1668 static void ohci_mem_write(void *opaque,
1669 hwaddr addr,
1670 uint64_t val,
1671 unsigned size)
1672 {
1673 OHCIState *ohci = opaque;
1674
1675 /* Only aligned reads are allowed on OHCI */
1676 if (addr & 3) {
1677 trace_usb_ohci_mem_write_unaligned(addr);
1678 return;
1679 }
1680
1681 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1682 /* HcRhPortStatus */
1683 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1684 return;
1685 }
1686
1687 switch (addr >> 2) {
1688 case 1: /* HcControl */
1689 ohci_set_ctl(ohci, val);
1690 break;
1691
1692 case 2: /* HcCommandStatus */
1693 /* SOC is read-only */
1694 val = (val & ~OHCI_STATUS_SOC);
1695
1696 /* Bits written as '0' remain unchanged in the register */
1697 ohci->status |= val;
1698
1699 if (ohci->status & OHCI_STATUS_HCR)
1700 ohci_soft_reset(ohci);
1701 break;
1702
1703 case 3: /* HcInterruptStatus */
1704 ohci->intr_status &= ~val;
1705 ohci_intr_update(ohci);
1706 break;
1707
1708 case 4: /* HcInterruptEnable */
1709 ohci->intr |= val;
1710 ohci_intr_update(ohci);
1711 break;
1712
1713 case 5: /* HcInterruptDisable */
1714 ohci->intr &= ~val;
1715 ohci_intr_update(ohci);
1716 break;
1717
1718 case 6: /* HcHCCA */
1719 ohci->hcca = val & OHCI_HCCA_MASK;
1720 break;
1721
1722 case 7: /* HcPeriodCurrentED */
1723 /* Ignore writes to this read-only register, Linux does them */
1724 break;
1725
1726 case 8: /* HcControlHeadED */
1727 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1728 break;
1729
1730 case 9: /* HcControlCurrentED */
1731 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1732 break;
1733
1734 case 10: /* HcBulkHeadED */
1735 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1736 break;
1737
1738 case 11: /* HcBulkCurrentED */
1739 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1740 break;
1741
1742 case 13: /* HcFmInterval */
1743 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1744 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1745 ohci_set_frame_interval(ohci, val);
1746 break;
1747
1748 case 15: /* HcFmNumber */
1749 break;
1750
1751 case 16: /* HcPeriodicStart */
1752 ohci->pstart = val & 0xffff;
1753 break;
1754
1755 case 17: /* HcLSThreshold */
1756 ohci->lst = val & 0xffff;
1757 break;
1758
1759 case 18: /* HcRhDescriptorA */
1760 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1761 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1762 break;
1763
1764 case 19: /* HcRhDescriptorB */
1765 break;
1766
1767 case 20: /* HcRhStatus */
1768 ohci_set_hub_status(ohci, val);
1769 break;
1770
1771 /* PXA27x specific registers */
1772 case 24: /* HcStatus */
1773 ohci->hstatus &= ~(val & ohci->hmask);
1774 break;
1775
1776 case 25: /* HcHReset */
1777 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1778 if (val & OHCI_HRESET_FSBIR)
1779 ohci_hard_reset(ohci);
1780 break;
1781
1782 case 26: /* HcHInterruptEnable */
1783 ohci->hmask = val;
1784 break;
1785
1786 case 27: /* HcHInterruptTest */
1787 ohci->htest = val;
1788 break;
1789
1790 default:
1791 trace_usb_ohci_mem_write_bad_offset(addr);
1792 break;
1793 }
1794 }
1795
1796 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev)
1797 {
1798 if (ohci->async_td &&
1799 usb_packet_is_inflight(&ohci->usb_packet) &&
1800 ohci->usb_packet.ep->dev == dev) {
1801 usb_cancel_packet(&ohci->usb_packet);
1802 ohci->async_td = 0;
1803 }
1804 }
1805
1806 static const MemoryRegionOps ohci_mem_ops = {
1807 .read = ohci_mem_read,
1808 .write = ohci_mem_write,
1809 .endianness = DEVICE_LITTLE_ENDIAN,
1810 };
1811
1812 static USBPortOps ohci_port_ops = {
1813 .attach = ohci_attach,
1814 .detach = ohci_detach,
1815 .child_detach = ohci_child_detach,
1816 .wakeup = ohci_wakeup,
1817 .complete = ohci_async_complete_packet,
1818 };
1819
1820 static USBBusOps ohci_bus_ops = {
1821 };
1822
1823 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
1824 dma_addr_t localmem_base, char *masterbus,
1825 uint32_t firstport, AddressSpace *as,
1826 void (*ohci_die_fn)(struct OHCIState *), Error **errp)
1827 {
1828 Error *err = NULL;
1829 int i;
1830
1831 ohci->as = as;
1832 ohci->ohci_die = ohci_die_fn;
1833
1834 if (num_ports > OHCI_MAX_PORTS) {
1835 error_setg(errp, "OHCI num-ports=%u is too big (limit is %u ports)",
1836 num_ports, OHCI_MAX_PORTS);
1837 return;
1838 }
1839
1840 if (usb_frame_time == 0) {
1841 #ifdef OHCI_TIME_WARP
1842 usb_frame_time = NANOSECONDS_PER_SECOND;
1843 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000);
1844 #else
1845 usb_frame_time = NANOSECONDS_PER_SECOND / 1000;
1846 if (NANOSECONDS_PER_SECOND >= USB_HZ) {
1847 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ;
1848 } else {
1849 usb_bit_time = 1;
1850 }
1851 #endif
1852 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time);
1853 }
1854
1855 ohci->num_ports = num_ports;
1856 if (masterbus) {
1857 USBPort *ports[OHCI_MAX_PORTS];
1858 for(i = 0; i < num_ports; i++) {
1859 ports[i] = &ohci->rhport[i].port;
1860 }
1861 usb_register_companion(masterbus, ports, num_ports,
1862 firstport, ohci, &ohci_port_ops,
1863 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1864 &err);
1865 if (err) {
1866 error_propagate(errp, err);
1867 return;
1868 }
1869 } else {
1870 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev);
1871 for (i = 0; i < num_ports; i++) {
1872 usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1873 ohci, i, &ohci_port_ops,
1874 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1875 }
1876 }
1877
1878 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops,
1879 ohci, "ohci", 256);
1880 ohci->localmem_base = localmem_base;
1881
1882 ohci->name = object_get_typename(OBJECT(dev));
1883 usb_packet_init(&ohci->usb_packet);
1884
1885 ohci->async_td = 0;
1886
1887 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1888 ohci_frame_boundary, ohci);
1889 }
1890
1891 /**
1892 * A typical OHCI will stop operating and set itself into error state
1893 * (which can be queried by MMIO) to signal that it got an error.
1894 */
1895 void ohci_sysbus_die(struct OHCIState *ohci)
1896 {
1897 trace_usb_ohci_die();
1898
1899 ohci_set_interrupt(ohci, OHCI_INTR_UE);
1900 ohci_bus_stop(ohci);
1901 }
1902
1903 static void ohci_realize_pxa(DeviceState *dev, Error **errp)
1904 {
1905 OHCISysBusState *s = SYSBUS_OHCI(dev);
1906 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1907 Error *err = NULL;
1908
1909 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
1910 s->masterbus, s->firstport,
1911 &address_space_memory, ohci_sysbus_die, &err);
1912 if (err) {
1913 error_propagate(errp, err);
1914 return;
1915 }
1916 sysbus_init_irq(sbd, &s->ohci.irq);
1917 sysbus_init_mmio(sbd, &s->ohci.mem);
1918 }
1919
1920 static void usb_ohci_reset_sysbus(DeviceState *dev)
1921 {
1922 OHCISysBusState *s = SYSBUS_OHCI(dev);
1923 OHCIState *ohci = &s->ohci;
1924
1925 ohci_hard_reset(ohci);
1926 }
1927
1928 static const VMStateDescription vmstate_ohci_state_port = {
1929 .name = "ohci-core/port",
1930 .version_id = 1,
1931 .minimum_version_id = 1,
1932 .fields = (VMStateField[]) {
1933 VMSTATE_UINT32(ctrl, OHCIPort),
1934 VMSTATE_END_OF_LIST()
1935 },
1936 };
1937
1938 static bool ohci_eof_timer_needed(void *opaque)
1939 {
1940 OHCIState *ohci = opaque;
1941
1942 return timer_pending(ohci->eof_timer);
1943 }
1944
1945 static const VMStateDescription vmstate_ohci_eof_timer = {
1946 .name = "ohci-core/eof-timer",
1947 .version_id = 1,
1948 .minimum_version_id = 1,
1949 .needed = ohci_eof_timer_needed,
1950 .fields = (VMStateField[]) {
1951 VMSTATE_TIMER_PTR(eof_timer, OHCIState),
1952 VMSTATE_END_OF_LIST()
1953 },
1954 };
1955
1956 const VMStateDescription vmstate_ohci_state = {
1957 .name = "ohci-core",
1958 .version_id = 1,
1959 .minimum_version_id = 1,
1960 .fields = (VMStateField[]) {
1961 VMSTATE_INT64(sof_time, OHCIState),
1962 VMSTATE_UINT32(ctl, OHCIState),
1963 VMSTATE_UINT32(status, OHCIState),
1964 VMSTATE_UINT32(intr_status, OHCIState),
1965 VMSTATE_UINT32(intr, OHCIState),
1966 VMSTATE_UINT32(hcca, OHCIState),
1967 VMSTATE_UINT32(ctrl_head, OHCIState),
1968 VMSTATE_UINT32(ctrl_cur, OHCIState),
1969 VMSTATE_UINT32(bulk_head, OHCIState),
1970 VMSTATE_UINT32(bulk_cur, OHCIState),
1971 VMSTATE_UINT32(per_cur, OHCIState),
1972 VMSTATE_UINT32(done, OHCIState),
1973 VMSTATE_INT32(done_count, OHCIState),
1974 VMSTATE_UINT16(fsmps, OHCIState),
1975 VMSTATE_UINT8(fit, OHCIState),
1976 VMSTATE_UINT16(fi, OHCIState),
1977 VMSTATE_UINT8(frt, OHCIState),
1978 VMSTATE_UINT16(frame_number, OHCIState),
1979 VMSTATE_UINT16(padding, OHCIState),
1980 VMSTATE_UINT32(pstart, OHCIState),
1981 VMSTATE_UINT32(lst, OHCIState),
1982 VMSTATE_UINT32(rhdesc_a, OHCIState),
1983 VMSTATE_UINT32(rhdesc_b, OHCIState),
1984 VMSTATE_UINT32(rhstatus, OHCIState),
1985 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0,
1986 vmstate_ohci_state_port, OHCIPort),
1987 VMSTATE_UINT32(hstatus, OHCIState),
1988 VMSTATE_UINT32(hmask, OHCIState),
1989 VMSTATE_UINT32(hreset, OHCIState),
1990 VMSTATE_UINT32(htest, OHCIState),
1991 VMSTATE_UINT32(old_ctl, OHCIState),
1992 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192),
1993 VMSTATE_UINT32(async_td, OHCIState),
1994 VMSTATE_BOOL(async_complete, OHCIState),
1995 VMSTATE_END_OF_LIST()
1996 },
1997 .subsections = (const VMStateDescription*[]) {
1998 &vmstate_ohci_eof_timer,
1999 NULL
2000 }
2001 };
2002
2003 static Property ohci_sysbus_properties[] = {
2004 DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
2005 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
2006 DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
2007 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
2008 DEFINE_PROP_END_OF_LIST(),
2009 };
2010
2011 static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
2012 {
2013 DeviceClass *dc = DEVICE_CLASS(klass);
2014
2015 dc->realize = ohci_realize_pxa;
2016 set_bit(DEVICE_CATEGORY_USB, dc->categories);
2017 dc->desc = "OHCI USB Controller";
2018 device_class_set_props(dc, ohci_sysbus_properties);
2019 dc->reset = usb_ohci_reset_sysbus;
2020 }
2021
2022 static const TypeInfo ohci_sysbus_info = {
2023 .name = TYPE_SYSBUS_OHCI,
2024 .parent = TYPE_SYS_BUS_DEVICE,
2025 .instance_size = sizeof(OHCISysBusState),
2026 .class_init = ohci_sysbus_class_init,
2027 };
2028
2029 static void ohci_register_types(void)
2030 {
2031 type_register_static(&ohci_sysbus_info);
2032 }
2033
2034 type_init(ohci_register_types)