hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / usb / hcd-ohci.h
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #ifndef HCD_OHCI_H
22 #define HCD_OHCI_H
23
24 #include "sysemu/dma.h"
25 #include "hw/usb.h"
26 #include "qom/object.h"
27
28 /* Number of Downstream Ports on the root hub: */
29 #define OHCI_MAX_PORTS 15
30
31 typedef struct OHCIPort {
32 USBPort port;
33 uint32_t ctrl;
34 } OHCIPort;
35
36 typedef struct OHCIState {
37 USBBus bus;
38 qemu_irq irq;
39 MemoryRegion mem;
40 AddressSpace *as;
41 uint32_t num_ports;
42 const char *name;
43
44 QEMUTimer *eof_timer;
45 int64_t sof_time;
46
47 /* OHCI state */
48 /* Control partition */
49 uint32_t ctl, status;
50 uint32_t intr_status;
51 uint32_t intr;
52
53 /* memory pointer partition */
54 uint32_t hcca;
55 uint32_t ctrl_head, ctrl_cur;
56 uint32_t bulk_head, bulk_cur;
57 uint32_t per_cur;
58 uint32_t done;
59 int32_t done_count;
60
61 /* Frame counter partition */
62 uint16_t fsmps;
63 uint8_t fit;
64 uint16_t fi;
65 uint8_t frt;
66 uint16_t frame_number;
67 uint16_t padding;
68 uint32_t pstart;
69 uint32_t lst;
70
71 /* Root Hub partition */
72 uint32_t rhdesc_a, rhdesc_b;
73 uint32_t rhstatus;
74 OHCIPort rhport[OHCI_MAX_PORTS];
75
76 /* PXA27x Non-OHCI events */
77 uint32_t hstatus;
78 uint32_t hmask;
79 uint32_t hreset;
80 uint32_t htest;
81
82 /* SM501 local memory offset */
83 dma_addr_t localmem_base;
84
85 /* Active packets. */
86 uint32_t old_ctl;
87 USBPacket usb_packet;
88 uint8_t usb_buf[8192];
89 uint32_t async_td;
90 bool async_complete;
91
92 void (*ohci_die)(struct OHCIState *ohci);
93 } OHCIState;
94
95 #define TYPE_SYSBUS_OHCI "sysbus-ohci"
96 OBJECT_DECLARE_SIMPLE_TYPE(OHCISysBusState, SYSBUS_OHCI)
97
98 struct OHCISysBusState {
99 /*< private >*/
100 SysBusDevice parent_obj;
101 /*< public >*/
102
103 OHCIState ohci;
104 char *masterbus;
105 uint32_t num_ports;
106 uint32_t firstport;
107 dma_addr_t dma_offset;
108 };
109
110 extern const VMStateDescription vmstate_ohci_state;
111
112 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
113 dma_addr_t localmem_base, char *masterbus,
114 uint32_t firstport, AddressSpace *as,
115 void (*ohci_die_fn)(struct OHCIState *), Error **errp);
116 void ohci_bus_stop(OHCIState *ohci);
117 void ohci_stop_endpoints(OHCIState *ohci);
118 void ohci_hard_reset(OHCIState *ohci);
119 void ohci_sysbus_die(struct OHCIState *ohci);
120
121 #endif