hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / usb / hcd-xhci-sysbus.c
1 /*
2 * USB xHCI controller for system-bus interface
3 * Based on hcd-echi-sysbus.c
4
5 * SPDX-FileCopyrightText: 2020 Xilinx
6 * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10 #include "qemu/osdep.h"
11 #include "hw/qdev-properties.h"
12 #include "migration/vmstate.h"
13 #include "trace.h"
14 #include "qapi/error.h"
15 #include "hcd-xhci-sysbus.h"
16 #include "hw/acpi/aml-build.h"
17 #include "hw/irq.h"
18
19 static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
20 {
21 XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
22
23 qemu_set_irq(s->irq[n], level);
24 }
25
26 void xhci_sysbus_reset(DeviceState *dev)
27 {
28 XHCISysbusState *s = XHCI_SYSBUS(dev);
29
30 device_legacy_reset(DEVICE(&s->xhci));
31 }
32
33 static void xhci_sysbus_realize(DeviceState *dev, Error **errp)
34 {
35 XHCISysbusState *s = XHCI_SYSBUS(dev);
36 Error *err = NULL;
37
38 object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
39 object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err);
40 if (err) {
41 error_propagate(errp, err);
42 return;
43 }
44 s->irq = g_new0(qemu_irq, s->xhci.numintrs);
45 qdev_init_gpio_out_named(dev, s->irq, SYSBUS_DEVICE_GPIO_IRQ,
46 s->xhci.numintrs);
47 if (s->xhci.dma_mr) {
48 s->xhci.as = g_malloc0(sizeof(AddressSpace));
49 address_space_init(s->xhci.as, s->xhci.dma_mr, NULL);
50 } else {
51 s->xhci.as = &address_space_memory;
52 }
53
54 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->xhci.mem);
55 }
56
57 static void xhci_sysbus_instance_init(Object *obj)
58 {
59 XHCISysbusState *s = XHCI_SYSBUS(obj);
60
61 object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
62 qdev_alias_all_properties(DEVICE(&s->xhci), obj);
63
64 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
65 (Object **)&s->xhci.dma_mr,
66 qdev_prop_allow_set_link_before_realize,
67 OBJ_PROP_LINK_STRONG);
68 s->xhci.intr_update = NULL;
69 s->xhci.intr_raise = xhci_sysbus_intr_raise;
70 }
71
72 void xhci_sysbus_build_aml(Aml *scope, uint32_t mmio, unsigned int irq)
73 {
74 Aml *dev = aml_device("XHCI");
75 Aml *crs = aml_resource_template();
76
77 aml_append(crs, aml_memory32_fixed(mmio, XHCI_LEN_REGS, AML_READ_WRITE));
78 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
79 AML_EXCLUSIVE, &irq, 1));
80
81 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0D10")));
82 aml_append(dev, aml_name_decl("_CRS", crs));
83 aml_append(scope, dev);
84 }
85
86 static Property xhci_sysbus_props[] = {
87 DEFINE_PROP_UINT32("intrs", XHCISysbusState, xhci.numintrs, XHCI_MAXINTRS),
88 DEFINE_PROP_UINT32("slots", XHCISysbusState, xhci.numslots, XHCI_MAXSLOTS),
89 DEFINE_PROP_END_OF_LIST(),
90 };
91
92 static const VMStateDescription vmstate_xhci_sysbus = {
93 .name = "xhci-sysbus",
94 .version_id = 1,
95 .fields = (VMStateField[]) {
96 VMSTATE_STRUCT(xhci, XHCISysbusState, 1, vmstate_xhci, XHCIState),
97 VMSTATE_END_OF_LIST()
98 }
99 };
100
101 static void xhci_sysbus_class_init(ObjectClass *klass, void *data)
102 {
103 DeviceClass *dc = DEVICE_CLASS(klass);
104
105 dc->reset = xhci_sysbus_reset;
106 dc->realize = xhci_sysbus_realize;
107 dc->vmsd = &vmstate_xhci_sysbus;
108 device_class_set_props(dc, xhci_sysbus_props);
109 }
110
111 static const TypeInfo xhci_sysbus_info = {
112 .name = TYPE_XHCI_SYSBUS,
113 .parent = TYPE_SYS_BUS_DEVICE,
114 .instance_size = sizeof(XHCISysbusState),
115 .class_init = xhci_sysbus_class_init,
116 .instance_init = xhci_sysbus_instance_init
117 };
118
119 static void xhci_sysbus_register_types(void)
120 {
121 type_register_static(&xhci_sysbus_info);
122 }
123
124 type_init(xhci_sysbus_register_types);