Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging
[qemu.git] / hw / usb / hcd-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qemu/timer.h"
24 #include "qemu/module.h"
25 #include "qemu/queue.h"
26 #include "migration/vmstate.h"
27 #include "hw/qdev-properties.h"
28 #include "trace.h"
29 #include "qapi/error.h"
30
31 #include "hcd-xhci.h"
32
33 //#define DEBUG_XHCI
34 //#define DEBUG_DATA
35
36 #ifdef DEBUG_XHCI
37 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
38 #else
39 #define DPRINTF(...) do {} while (0)
40 #endif
41 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
42 __func__, __LINE__, _msg); abort(); } while (0)
43
44 #define TRB_LINK_LIMIT 32
45 #define COMMAND_LIMIT 256
46 #define TRANSFER_LIMIT 256
47
48 #define LEN_CAP 0x40
49 #define LEN_OPER (0x400 + 0x10 * XHCI_MAXPORTS)
50 #define LEN_RUNTIME ((XHCI_MAXINTRS + 1) * 0x20)
51 #define LEN_DOORBELL ((XHCI_MAXSLOTS + 1) * 0x20)
52
53 #define OFF_OPER LEN_CAP
54 #define OFF_RUNTIME 0x1000
55 #define OFF_DOORBELL 0x2000
56
57 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
58 #error Increase OFF_RUNTIME
59 #endif
60 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
61 #error Increase OFF_DOORBELL
62 #endif
63 #if (OFF_DOORBELL + LEN_DOORBELL) > XHCI_LEN_REGS
64 # error Increase XHCI_LEN_REGS
65 #endif
66
67 /* bit definitions */
68 #define USBCMD_RS (1<<0)
69 #define USBCMD_HCRST (1<<1)
70 #define USBCMD_INTE (1<<2)
71 #define USBCMD_HSEE (1<<3)
72 #define USBCMD_LHCRST (1<<7)
73 #define USBCMD_CSS (1<<8)
74 #define USBCMD_CRS (1<<9)
75 #define USBCMD_EWE (1<<10)
76 #define USBCMD_EU3S (1<<11)
77
78 #define USBSTS_HCH (1<<0)
79 #define USBSTS_HSE (1<<2)
80 #define USBSTS_EINT (1<<3)
81 #define USBSTS_PCD (1<<4)
82 #define USBSTS_SSS (1<<8)
83 #define USBSTS_RSS (1<<9)
84 #define USBSTS_SRE (1<<10)
85 #define USBSTS_CNR (1<<11)
86 #define USBSTS_HCE (1<<12)
87
88
89 #define PORTSC_CCS (1<<0)
90 #define PORTSC_PED (1<<1)
91 #define PORTSC_OCA (1<<3)
92 #define PORTSC_PR (1<<4)
93 #define PORTSC_PLS_SHIFT 5
94 #define PORTSC_PLS_MASK 0xf
95 #define PORTSC_PP (1<<9)
96 #define PORTSC_SPEED_SHIFT 10
97 #define PORTSC_SPEED_MASK 0xf
98 #define PORTSC_SPEED_FULL (1<<10)
99 #define PORTSC_SPEED_LOW (2<<10)
100 #define PORTSC_SPEED_HIGH (3<<10)
101 #define PORTSC_SPEED_SUPER (4<<10)
102 #define PORTSC_PIC_SHIFT 14
103 #define PORTSC_PIC_MASK 0x3
104 #define PORTSC_LWS (1<<16)
105 #define PORTSC_CSC (1<<17)
106 #define PORTSC_PEC (1<<18)
107 #define PORTSC_WRC (1<<19)
108 #define PORTSC_OCC (1<<20)
109 #define PORTSC_PRC (1<<21)
110 #define PORTSC_PLC (1<<22)
111 #define PORTSC_CEC (1<<23)
112 #define PORTSC_CAS (1<<24)
113 #define PORTSC_WCE (1<<25)
114 #define PORTSC_WDE (1<<26)
115 #define PORTSC_WOE (1<<27)
116 #define PORTSC_DR (1<<30)
117 #define PORTSC_WPR (1<<31)
118
119 #define CRCR_RCS (1<<0)
120 #define CRCR_CS (1<<1)
121 #define CRCR_CA (1<<2)
122 #define CRCR_CRR (1<<3)
123
124 #define IMAN_IP (1<<0)
125 #define IMAN_IE (1<<1)
126
127 #define ERDP_EHB (1<<3)
128
129 #define TRB_SIZE 16
130 typedef struct XHCITRB {
131 uint64_t parameter;
132 uint32_t status;
133 uint32_t control;
134 dma_addr_t addr;
135 bool ccs;
136 } XHCITRB;
137
138 enum {
139 PLS_U0 = 0,
140 PLS_U1 = 1,
141 PLS_U2 = 2,
142 PLS_U3 = 3,
143 PLS_DISABLED = 4,
144 PLS_RX_DETECT = 5,
145 PLS_INACTIVE = 6,
146 PLS_POLLING = 7,
147 PLS_RECOVERY = 8,
148 PLS_HOT_RESET = 9,
149 PLS_COMPILANCE_MODE = 10,
150 PLS_TEST_MODE = 11,
151 PLS_RESUME = 15,
152 };
153
154 #define CR_LINK TR_LINK
155
156 #define TRB_C (1<<0)
157 #define TRB_TYPE_SHIFT 10
158 #define TRB_TYPE_MASK 0x3f
159 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
160
161 #define TRB_EV_ED (1<<2)
162
163 #define TRB_TR_ENT (1<<1)
164 #define TRB_TR_ISP (1<<2)
165 #define TRB_TR_NS (1<<3)
166 #define TRB_TR_CH (1<<4)
167 #define TRB_TR_IOC (1<<5)
168 #define TRB_TR_IDT (1<<6)
169 #define TRB_TR_TBC_SHIFT 7
170 #define TRB_TR_TBC_MASK 0x3
171 #define TRB_TR_BEI (1<<9)
172 #define TRB_TR_TLBPC_SHIFT 16
173 #define TRB_TR_TLBPC_MASK 0xf
174 #define TRB_TR_FRAMEID_SHIFT 20
175 #define TRB_TR_FRAMEID_MASK 0x7ff
176 #define TRB_TR_SIA (1<<31)
177
178 #define TRB_TR_DIR (1<<16)
179
180 #define TRB_CR_SLOTID_SHIFT 24
181 #define TRB_CR_SLOTID_MASK 0xff
182 #define TRB_CR_EPID_SHIFT 16
183 #define TRB_CR_EPID_MASK 0x1f
184
185 #define TRB_CR_BSR (1<<9)
186 #define TRB_CR_DC (1<<9)
187
188 #define TRB_LK_TC (1<<1)
189
190 #define TRB_INTR_SHIFT 22
191 #define TRB_INTR_MASK 0x3ff
192 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
193
194 #define EP_TYPE_MASK 0x7
195 #define EP_TYPE_SHIFT 3
196
197 #define EP_STATE_MASK 0x7
198 #define EP_DISABLED (0<<0)
199 #define EP_RUNNING (1<<0)
200 #define EP_HALTED (2<<0)
201 #define EP_STOPPED (3<<0)
202 #define EP_ERROR (4<<0)
203
204 #define SLOT_STATE_MASK 0x1f
205 #define SLOT_STATE_SHIFT 27
206 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
207 #define SLOT_ENABLED 0
208 #define SLOT_DEFAULT 1
209 #define SLOT_ADDRESSED 2
210 #define SLOT_CONFIGURED 3
211
212 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
213 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
214
215 #define get_field(data, field) \
216 (((data) >> field##_SHIFT) & field##_MASK)
217
218 #define set_field(data, newval, field) do { \
219 uint32_t val = *data; \
220 val &= ~(field##_MASK << field##_SHIFT); \
221 val |= ((newval) & field##_MASK) << field##_SHIFT; \
222 *data = val; \
223 } while (0)
224
225 typedef enum EPType {
226 ET_INVALID = 0,
227 ET_ISO_OUT,
228 ET_BULK_OUT,
229 ET_INTR_OUT,
230 ET_CONTROL,
231 ET_ISO_IN,
232 ET_BULK_IN,
233 ET_INTR_IN,
234 } EPType;
235
236 typedef struct XHCITransfer {
237 XHCIEPContext *epctx;
238 USBPacket packet;
239 QEMUSGList sgl;
240 bool running_async;
241 bool running_retry;
242 bool complete;
243 bool int_req;
244 unsigned int iso_pkts;
245 unsigned int streamid;
246 bool in_xfer;
247 bool iso_xfer;
248 bool timed_xfer;
249
250 unsigned int trb_count;
251 XHCITRB *trbs;
252
253 TRBCCode status;
254
255 unsigned int pkts;
256 unsigned int pktsize;
257 unsigned int cur_pkt;
258
259 uint64_t mfindex_kick;
260
261 QTAILQ_ENTRY(XHCITransfer) next;
262 } XHCITransfer;
263
264 struct XHCIStreamContext {
265 dma_addr_t pctx;
266 unsigned int sct;
267 XHCIRing ring;
268 };
269
270 struct XHCIEPContext {
271 XHCIState *xhci;
272 unsigned int slotid;
273 unsigned int epid;
274
275 XHCIRing ring;
276 uint32_t xfer_count;
277 QTAILQ_HEAD(, XHCITransfer) transfers;
278 XHCITransfer *retry;
279 EPType type;
280 dma_addr_t pctx;
281 unsigned int max_psize;
282 uint32_t state;
283 uint32_t kick_active;
284
285 /* streams */
286 unsigned int max_pstreams;
287 bool lsa;
288 unsigned int nr_pstreams;
289 XHCIStreamContext *pstreams;
290
291 /* iso xfer scheduling */
292 unsigned int interval;
293 int64_t mfindex_last;
294 QEMUTimer *kick_timer;
295 };
296
297 typedef struct XHCIEvRingSeg {
298 uint32_t addr_low;
299 uint32_t addr_high;
300 uint32_t size;
301 uint32_t rsvd;
302 } XHCIEvRingSeg;
303
304 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
305 unsigned int epid, unsigned int streamid);
306 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
307 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
308 unsigned int epid);
309 static void xhci_xfer_report(XHCITransfer *xfer);
310 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
311 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
312 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx);
313
314 static const char *TRBType_names[] = {
315 [TRB_RESERVED] = "TRB_RESERVED",
316 [TR_NORMAL] = "TR_NORMAL",
317 [TR_SETUP] = "TR_SETUP",
318 [TR_DATA] = "TR_DATA",
319 [TR_STATUS] = "TR_STATUS",
320 [TR_ISOCH] = "TR_ISOCH",
321 [TR_LINK] = "TR_LINK",
322 [TR_EVDATA] = "TR_EVDATA",
323 [TR_NOOP] = "TR_NOOP",
324 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
325 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
326 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
327 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
328 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
329 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
330 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
331 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
332 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
333 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
334 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
335 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
336 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
337 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
338 [CR_NOOP] = "CR_NOOP",
339 [ER_TRANSFER] = "ER_TRANSFER",
340 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
341 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
342 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
343 [ER_DOORBELL] = "ER_DOORBELL",
344 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
345 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
346 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
347 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
348 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
349 };
350
351 static const char *TRBCCode_names[] = {
352 [CC_INVALID] = "CC_INVALID",
353 [CC_SUCCESS] = "CC_SUCCESS",
354 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
355 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
356 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
357 [CC_TRB_ERROR] = "CC_TRB_ERROR",
358 [CC_STALL_ERROR] = "CC_STALL_ERROR",
359 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
360 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
361 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
362 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
363 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
364 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
365 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
366 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
367 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
368 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
369 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
370 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
371 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
372 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
373 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
374 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
375 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
376 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
377 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
378 [CC_STOPPED] = "CC_STOPPED",
379 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
380 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
381 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
382 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
383 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
384 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
385 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
386 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
387 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
388 };
389
390 static const char *ep_state_names[] = {
391 [EP_DISABLED] = "disabled",
392 [EP_RUNNING] = "running",
393 [EP_HALTED] = "halted",
394 [EP_STOPPED] = "stopped",
395 [EP_ERROR] = "error",
396 };
397
398 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
399 {
400 if (index >= llen || list[index] == NULL) {
401 return "???";
402 }
403 return list[index];
404 }
405
406 static const char *trb_name(XHCITRB *trb)
407 {
408 return lookup_name(TRB_TYPE(*trb), TRBType_names,
409 ARRAY_SIZE(TRBType_names));
410 }
411
412 static const char *event_name(XHCIEvent *event)
413 {
414 return lookup_name(event->ccode, TRBCCode_names,
415 ARRAY_SIZE(TRBCCode_names));
416 }
417
418 static const char *ep_state_name(uint32_t state)
419 {
420 return lookup_name(state, ep_state_names,
421 ARRAY_SIZE(ep_state_names));
422 }
423
424 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
425 {
426 return xhci->flags & (1 << bit);
427 }
428
429 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
430 {
431 xhci->flags |= (1 << bit);
432 }
433
434 static uint64_t xhci_mfindex_get(XHCIState *xhci)
435 {
436 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
437 return (now - xhci->mfindex_start) / 125000;
438 }
439
440 static void xhci_mfwrap_update(XHCIState *xhci)
441 {
442 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
443 uint32_t mfindex, left;
444 int64_t now;
445
446 if ((xhci->usbcmd & bits) == bits) {
447 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
448 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
449 left = 0x4000 - mfindex;
450 timer_mod(xhci->mfwrap_timer, now + left * 125000);
451 } else {
452 timer_del(xhci->mfwrap_timer);
453 }
454 }
455
456 static void xhci_mfwrap_timer(void *opaque)
457 {
458 XHCIState *xhci = opaque;
459 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
460
461 xhci_event(xhci, &wrap, 0);
462 xhci_mfwrap_update(xhci);
463 }
464
465 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
466 {
467 if (sizeof(dma_addr_t) == 4) {
468 return low;
469 } else {
470 return low | (((dma_addr_t)high << 16) << 16);
471 }
472 }
473
474 static inline dma_addr_t xhci_mask64(uint64_t addr)
475 {
476 if (sizeof(dma_addr_t) == 4) {
477 return addr & 0xffffffff;
478 } else {
479 return addr;
480 }
481 }
482
483 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
484 uint32_t *buf, size_t len)
485 {
486 int i;
487
488 assert((len % sizeof(uint32_t)) == 0);
489
490 dma_memory_read(xhci->as, addr, buf, len, MEMTXATTRS_UNSPECIFIED);
491
492 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
493 buf[i] = le32_to_cpu(buf[i]);
494 }
495 }
496
497 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
498 uint32_t *buf, size_t len)
499 {
500 int i;
501 uint32_t tmp[5];
502 uint32_t n = len / sizeof(uint32_t);
503
504 assert((len % sizeof(uint32_t)) == 0);
505 assert(n <= ARRAY_SIZE(tmp));
506
507 for (i = 0; i < n; i++) {
508 tmp[i] = cpu_to_le32(buf[i]);
509 }
510 dma_memory_write(xhci->as, addr, tmp, len, MEMTXATTRS_UNSPECIFIED);
511 }
512
513 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
514 {
515 int index;
516
517 if (!uport->dev) {
518 return NULL;
519 }
520 switch (uport->dev->speed) {
521 case USB_SPEED_LOW:
522 case USB_SPEED_FULL:
523 case USB_SPEED_HIGH:
524 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
525 index = uport->index + xhci->numports_3;
526 } else {
527 index = uport->index;
528 }
529 break;
530 case USB_SPEED_SUPER:
531 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
532 index = uport->index;
533 } else {
534 index = uport->index + xhci->numports_2;
535 }
536 break;
537 default:
538 return NULL;
539 }
540 return &xhci->ports[index];
541 }
542
543 static void xhci_intr_update(XHCIState *xhci, int v)
544 {
545 int level = 0;
546
547 if (v == 0) {
548 if (xhci->intr[0].iman & IMAN_IP &&
549 xhci->intr[0].iman & IMAN_IE &&
550 xhci->usbcmd & USBCMD_INTE) {
551 level = 1;
552 }
553 if (xhci->intr_raise) {
554 if (xhci->intr_raise(xhci, 0, level)) {
555 xhci->intr[0].iman &= ~IMAN_IP;
556 }
557 }
558 }
559 if (xhci->intr_update) {
560 xhci->intr_update(xhci, v,
561 xhci->intr[v].iman & IMAN_IE);
562 }
563 }
564
565 static void xhci_intr_raise(XHCIState *xhci, int v)
566 {
567 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
568
569 xhci->intr[v].erdp_low |= ERDP_EHB;
570 xhci->intr[v].iman |= IMAN_IP;
571 xhci->usbsts |= USBSTS_EINT;
572
573 if (pending) {
574 return;
575 }
576 if (!(xhci->intr[v].iman & IMAN_IE)) {
577 return;
578 }
579
580 if (!(xhci->usbcmd & USBCMD_INTE)) {
581 return;
582 }
583 if (xhci->intr_raise) {
584 if (xhci->intr_raise(xhci, v, true)) {
585 xhci->intr[v].iman &= ~IMAN_IP;
586 }
587 }
588 }
589
590 static inline int xhci_running(XHCIState *xhci)
591 {
592 return !(xhci->usbsts & USBSTS_HCH);
593 }
594
595 static void xhci_die(XHCIState *xhci)
596 {
597 xhci->usbsts |= USBSTS_HCE;
598 DPRINTF("xhci: asserted controller error\n");
599 }
600
601 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
602 {
603 XHCIInterrupter *intr = &xhci->intr[v];
604 XHCITRB ev_trb;
605 dma_addr_t addr;
606
607 ev_trb.parameter = cpu_to_le64(event->ptr);
608 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
609 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
610 event->flags | (event->type << TRB_TYPE_SHIFT);
611 if (intr->er_pcs) {
612 ev_trb.control |= TRB_C;
613 }
614 ev_trb.control = cpu_to_le32(ev_trb.control);
615
616 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
617 event_name(event), ev_trb.parameter,
618 ev_trb.status, ev_trb.control);
619
620 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
621 dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE, MEMTXATTRS_UNSPECIFIED);
622
623 intr->er_ep_idx++;
624 if (intr->er_ep_idx >= intr->er_size) {
625 intr->er_ep_idx = 0;
626 intr->er_pcs = !intr->er_pcs;
627 }
628 }
629
630 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
631 {
632 XHCIInterrupter *intr;
633 dma_addr_t erdp;
634 unsigned int dp_idx;
635
636 if (v >= xhci->numintrs) {
637 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
638 return;
639 }
640 intr = &xhci->intr[v];
641
642 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
643 if (erdp < intr->er_start ||
644 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
645 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
646 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
647 v, intr->er_start, intr->er_size);
648 xhci_die(xhci);
649 return;
650 }
651
652 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
653 assert(dp_idx < intr->er_size);
654
655 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) {
656 DPRINTF("xhci: ER %d full, send ring full error\n", v);
657 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
658 xhci_write_event(xhci, &full, v);
659 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) {
660 DPRINTF("xhci: ER %d full, drop event\n", v);
661 } else {
662 xhci_write_event(xhci, event, v);
663 }
664
665 xhci_intr_raise(xhci, v);
666 }
667
668 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
669 dma_addr_t base)
670 {
671 ring->dequeue = base;
672 ring->ccs = 1;
673 }
674
675 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
676 dma_addr_t *addr)
677 {
678 uint32_t link_cnt = 0;
679
680 while (1) {
681 TRBType type;
682 dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE,
683 MEMTXATTRS_UNSPECIFIED);
684 trb->addr = ring->dequeue;
685 trb->ccs = ring->ccs;
686 le64_to_cpus(&trb->parameter);
687 le32_to_cpus(&trb->status);
688 le32_to_cpus(&trb->control);
689
690 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
691 trb->parameter, trb->status, trb->control);
692
693 if ((trb->control & TRB_C) != ring->ccs) {
694 return 0;
695 }
696
697 type = TRB_TYPE(*trb);
698
699 if (type != TR_LINK) {
700 if (addr) {
701 *addr = ring->dequeue;
702 }
703 ring->dequeue += TRB_SIZE;
704 return type;
705 } else {
706 if (++link_cnt > TRB_LINK_LIMIT) {
707 trace_usb_xhci_enforced_limit("trb-link");
708 return 0;
709 }
710 ring->dequeue = xhci_mask64(trb->parameter);
711 if (trb->control & TRB_LK_TC) {
712 ring->ccs = !ring->ccs;
713 }
714 }
715 }
716 }
717
718 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
719 {
720 XHCITRB trb;
721 int length = 0;
722 dma_addr_t dequeue = ring->dequeue;
723 bool ccs = ring->ccs;
724 /* hack to bundle together the two/three TDs that make a setup transfer */
725 bool control_td_set = 0;
726 uint32_t link_cnt = 0;
727
728 while (1) {
729 TRBType type;
730 dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE,
731 MEMTXATTRS_UNSPECIFIED);
732 le64_to_cpus(&trb.parameter);
733 le32_to_cpus(&trb.status);
734 le32_to_cpus(&trb.control);
735
736 if ((trb.control & TRB_C) != ccs) {
737 return -length;
738 }
739
740 type = TRB_TYPE(trb);
741
742 if (type == TR_LINK) {
743 if (++link_cnt > TRB_LINK_LIMIT) {
744 return -length;
745 }
746 dequeue = xhci_mask64(trb.parameter);
747 if (trb.control & TRB_LK_TC) {
748 ccs = !ccs;
749 }
750 continue;
751 }
752
753 length += 1;
754 dequeue += TRB_SIZE;
755
756 if (type == TR_SETUP) {
757 control_td_set = 1;
758 } else if (type == TR_STATUS) {
759 control_td_set = 0;
760 }
761
762 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
763 return length;
764 }
765 }
766 }
767
768 static void xhci_er_reset(XHCIState *xhci, int v)
769 {
770 XHCIInterrupter *intr = &xhci->intr[v];
771 XHCIEvRingSeg seg;
772 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
773
774 if (intr->erstsz == 0 || erstba == 0) {
775 /* disabled */
776 intr->er_start = 0;
777 intr->er_size = 0;
778 return;
779 }
780 /* cache the (sole) event ring segment location */
781 if (intr->erstsz != 1) {
782 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
783 xhci_die(xhci);
784 return;
785 }
786 dma_memory_read(xhci->as, erstba, &seg, sizeof(seg),
787 MEMTXATTRS_UNSPECIFIED);
788 le32_to_cpus(&seg.addr_low);
789 le32_to_cpus(&seg.addr_high);
790 le32_to_cpus(&seg.size);
791 if (seg.size < 16 || seg.size > 4096) {
792 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
793 xhci_die(xhci);
794 return;
795 }
796 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
797 intr->er_size = seg.size;
798
799 intr->er_ep_idx = 0;
800 intr->er_pcs = 1;
801
802 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
803 v, intr->er_start, intr->er_size);
804 }
805
806 static void xhci_run(XHCIState *xhci)
807 {
808 trace_usb_xhci_run();
809 xhci->usbsts &= ~USBSTS_HCH;
810 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
811 }
812
813 static void xhci_stop(XHCIState *xhci)
814 {
815 trace_usb_xhci_stop();
816 xhci->usbsts |= USBSTS_HCH;
817 xhci->crcr_low &= ~CRCR_CRR;
818 }
819
820 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
821 dma_addr_t base)
822 {
823 XHCIStreamContext *stctx;
824 unsigned int i;
825
826 stctx = g_new0(XHCIStreamContext, count);
827 for (i = 0; i < count; i++) {
828 stctx[i].pctx = base + i * 16;
829 stctx[i].sct = -1;
830 }
831 return stctx;
832 }
833
834 static void xhci_reset_streams(XHCIEPContext *epctx)
835 {
836 unsigned int i;
837
838 for (i = 0; i < epctx->nr_pstreams; i++) {
839 epctx->pstreams[i].sct = -1;
840 }
841 }
842
843 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
844 {
845 assert(epctx->pstreams == NULL);
846 epctx->nr_pstreams = 2 << epctx->max_pstreams;
847 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
848 }
849
850 static void xhci_free_streams(XHCIEPContext *epctx)
851 {
852 assert(epctx->pstreams != NULL);
853
854 g_free(epctx->pstreams);
855 epctx->pstreams = NULL;
856 epctx->nr_pstreams = 0;
857 }
858
859 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
860 unsigned int slotid,
861 uint32_t epmask,
862 XHCIEPContext **epctxs,
863 USBEndpoint **eps)
864 {
865 XHCISlot *slot;
866 XHCIEPContext *epctx;
867 USBEndpoint *ep;
868 int i, j;
869
870 assert(slotid >= 1 && slotid <= xhci->numslots);
871
872 slot = &xhci->slots[slotid - 1];
873
874 for (i = 2, j = 0; i <= 31; i++) {
875 if (!(epmask & (1u << i))) {
876 continue;
877 }
878
879 epctx = slot->eps[i - 1];
880 ep = xhci_epid_to_usbep(epctx);
881 if (!epctx || !epctx->nr_pstreams || !ep) {
882 continue;
883 }
884
885 if (epctxs) {
886 epctxs[j] = epctx;
887 }
888 eps[j++] = ep;
889 }
890 return j;
891 }
892
893 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
894 uint32_t epmask)
895 {
896 USBEndpoint *eps[30];
897 int nr_eps;
898
899 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
900 if (nr_eps) {
901 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
902 }
903 }
904
905 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
906 uint32_t epmask)
907 {
908 XHCIEPContext *epctxs[30];
909 USBEndpoint *eps[30];
910 int i, r, nr_eps, req_nr_streams, dev_max_streams;
911
912 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
913 eps);
914 if (nr_eps == 0) {
915 return CC_SUCCESS;
916 }
917
918 req_nr_streams = epctxs[0]->nr_pstreams;
919 dev_max_streams = eps[0]->max_streams;
920
921 for (i = 1; i < nr_eps; i++) {
922 /*
923 * HdG: I don't expect these to ever trigger, but if they do we need
924 * to come up with another solution, ie group identical endpoints
925 * together and make an usb_device_alloc_streams call per group.
926 */
927 if (epctxs[i]->nr_pstreams != req_nr_streams) {
928 FIXME("guest streams config not identical for all eps");
929 return CC_RESOURCE_ERROR;
930 }
931 if (eps[i]->max_streams != dev_max_streams) {
932 FIXME("device streams config not identical for all eps");
933 return CC_RESOURCE_ERROR;
934 }
935 }
936
937 /*
938 * max-streams in both the device descriptor and in the controller is a
939 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
940 * streams the guest will ask for 5 rounded up to the next power of 2 which
941 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
942 *
943 * For redirected devices however this is an issue, as there we must ask
944 * the real xhci controller to alloc streams, and the host driver for the
945 * real xhci controller will likely disallow allocating more streams then
946 * the device can handle.
947 *
948 * So we limit the requested nr_streams to the maximum number the device
949 * can handle.
950 */
951 if (req_nr_streams > dev_max_streams) {
952 req_nr_streams = dev_max_streams;
953 }
954
955 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
956 if (r != 0) {
957 DPRINTF("xhci: alloc streams failed\n");
958 return CC_RESOURCE_ERROR;
959 }
960
961 return CC_SUCCESS;
962 }
963
964 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
965 unsigned int streamid,
966 uint32_t *cc_error)
967 {
968 XHCIStreamContext *sctx;
969 dma_addr_t base;
970 uint32_t ctx[2], sct;
971
972 assert(streamid != 0);
973 if (epctx->lsa) {
974 if (streamid >= epctx->nr_pstreams) {
975 *cc_error = CC_INVALID_STREAM_ID_ERROR;
976 return NULL;
977 }
978 sctx = epctx->pstreams + streamid;
979 } else {
980 FIXME("secondary streams not implemented yet");
981 }
982
983 if (sctx->sct == -1) {
984 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
985 sct = (ctx[0] >> 1) & 0x07;
986 if (epctx->lsa && sct != 1) {
987 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
988 return NULL;
989 }
990 sctx->sct = sct;
991 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
992 xhci_ring_init(epctx->xhci, &sctx->ring, base);
993 }
994 return sctx;
995 }
996
997 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
998 XHCIStreamContext *sctx, uint32_t state)
999 {
1000 XHCIRing *ring = NULL;
1001 uint32_t ctx[5];
1002 uint32_t ctx2[2];
1003
1004 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1005 ctx[0] &= ~EP_STATE_MASK;
1006 ctx[0] |= state;
1007
1008 /* update ring dequeue ptr */
1009 if (epctx->nr_pstreams) {
1010 if (sctx != NULL) {
1011 ring = &sctx->ring;
1012 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1013 ctx2[0] &= 0xe;
1014 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1015 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1016 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1017 }
1018 } else {
1019 ring = &epctx->ring;
1020 }
1021 if (ring) {
1022 ctx[2] = ring->dequeue | ring->ccs;
1023 ctx[3] = (ring->dequeue >> 16) >> 16;
1024
1025 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1026 epctx->pctx, state, ctx[3], ctx[2]);
1027 }
1028
1029 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1030 if (epctx->state != state) {
1031 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1032 ep_state_name(epctx->state),
1033 ep_state_name(state));
1034 }
1035 epctx->state = state;
1036 }
1037
1038 static void xhci_ep_kick_timer(void *opaque)
1039 {
1040 XHCIEPContext *epctx = opaque;
1041 xhci_kick_epctx(epctx, 0);
1042 }
1043
1044 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1045 unsigned int slotid,
1046 unsigned int epid)
1047 {
1048 XHCIEPContext *epctx;
1049
1050 epctx = g_new0(XHCIEPContext, 1);
1051 epctx->xhci = xhci;
1052 epctx->slotid = slotid;
1053 epctx->epid = epid;
1054
1055 QTAILQ_INIT(&epctx->transfers);
1056 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1057
1058 return epctx;
1059 }
1060
1061 static void xhci_init_epctx(XHCIEPContext *epctx,
1062 dma_addr_t pctx, uint32_t *ctx)
1063 {
1064 dma_addr_t dequeue;
1065
1066 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1067
1068 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1069 epctx->pctx = pctx;
1070 epctx->max_psize = ctx[1]>>16;
1071 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1072 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1073 epctx->lsa = (ctx[0] >> 15) & 1;
1074 if (epctx->max_pstreams) {
1075 xhci_alloc_streams(epctx, dequeue);
1076 } else {
1077 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1078 epctx->ring.ccs = ctx[2] & 1;
1079 }
1080
1081 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1082 }
1083
1084 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1085 unsigned int epid, dma_addr_t pctx,
1086 uint32_t *ctx)
1087 {
1088 XHCISlot *slot;
1089 XHCIEPContext *epctx;
1090
1091 trace_usb_xhci_ep_enable(slotid, epid);
1092 assert(slotid >= 1 && slotid <= xhci->numslots);
1093 assert(epid >= 1 && epid <= 31);
1094
1095 slot = &xhci->slots[slotid-1];
1096 if (slot->eps[epid-1]) {
1097 xhci_disable_ep(xhci, slotid, epid);
1098 }
1099
1100 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1101 slot->eps[epid-1] = epctx;
1102 xhci_init_epctx(epctx, pctx, ctx);
1103
1104 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1105 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1106
1107 epctx->mfindex_last = 0;
1108
1109 epctx->state = EP_RUNNING;
1110 ctx[0] &= ~EP_STATE_MASK;
1111 ctx[0] |= EP_RUNNING;
1112
1113 return CC_SUCCESS;
1114 }
1115
1116 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx,
1117 uint32_t length)
1118 {
1119 uint32_t limit = epctx->nr_pstreams + 16;
1120 XHCITransfer *xfer;
1121
1122 if (epctx->xfer_count >= limit) {
1123 return NULL;
1124 }
1125
1126 xfer = g_new0(XHCITransfer, 1);
1127 xfer->epctx = epctx;
1128 xfer->trbs = g_new(XHCITRB, length);
1129 xfer->trb_count = length;
1130 usb_packet_init(&xfer->packet);
1131
1132 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next);
1133 epctx->xfer_count++;
1134
1135 return xfer;
1136 }
1137
1138 static void xhci_ep_free_xfer(XHCITransfer *xfer)
1139 {
1140 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next);
1141 xfer->epctx->xfer_count--;
1142
1143 usb_packet_cleanup(&xfer->packet);
1144 g_free(xfer->trbs);
1145 g_free(xfer);
1146 }
1147
1148 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1149 {
1150 int killed = 0;
1151
1152 if (report && (t->running_async || t->running_retry)) {
1153 t->status = report;
1154 xhci_xfer_report(t);
1155 }
1156
1157 if (t->running_async) {
1158 usb_cancel_packet(&t->packet);
1159 t->running_async = 0;
1160 killed = 1;
1161 }
1162 if (t->running_retry) {
1163 if (t->epctx) {
1164 t->epctx->retry = NULL;
1165 timer_del(t->epctx->kick_timer);
1166 }
1167 t->running_retry = 0;
1168 killed = 1;
1169 }
1170 g_free(t->trbs);
1171
1172 t->trbs = NULL;
1173 t->trb_count = 0;
1174
1175 return killed;
1176 }
1177
1178 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1179 unsigned int epid, TRBCCode report)
1180 {
1181 XHCISlot *slot;
1182 XHCIEPContext *epctx;
1183 XHCITransfer *xfer;
1184 int killed = 0;
1185 USBEndpoint *ep = NULL;
1186 assert(slotid >= 1 && slotid <= xhci->numslots);
1187 assert(epid >= 1 && epid <= 31);
1188
1189 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1190
1191 slot = &xhci->slots[slotid-1];
1192
1193 if (!slot->eps[epid-1]) {
1194 return 0;
1195 }
1196
1197 epctx = slot->eps[epid-1];
1198
1199 for (;;) {
1200 xfer = QTAILQ_FIRST(&epctx->transfers);
1201 if (xfer == NULL) {
1202 break;
1203 }
1204 killed += xhci_ep_nuke_one_xfer(xfer, report);
1205 if (killed) {
1206 report = 0; /* Only report once */
1207 }
1208 xhci_ep_free_xfer(xfer);
1209 }
1210
1211 ep = xhci_epid_to_usbep(epctx);
1212 if (ep) {
1213 usb_device_ep_stopped(ep->dev, ep);
1214 }
1215 return killed;
1216 }
1217
1218 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1219 unsigned int epid)
1220 {
1221 XHCISlot *slot;
1222 XHCIEPContext *epctx;
1223
1224 trace_usb_xhci_ep_disable(slotid, epid);
1225 assert(slotid >= 1 && slotid <= xhci->numslots);
1226 assert(epid >= 1 && epid <= 31);
1227
1228 slot = &xhci->slots[slotid-1];
1229
1230 if (!slot->eps[epid-1]) {
1231 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1232 return CC_SUCCESS;
1233 }
1234
1235 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1236
1237 epctx = slot->eps[epid-1];
1238
1239 if (epctx->nr_pstreams) {
1240 xhci_free_streams(epctx);
1241 }
1242
1243 /* only touch guest RAM if we're not resetting the HC */
1244 if (xhci->dcbaap_low || xhci->dcbaap_high) {
1245 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1246 }
1247
1248 timer_free(epctx->kick_timer);
1249 g_free(epctx);
1250 slot->eps[epid-1] = NULL;
1251
1252 return CC_SUCCESS;
1253 }
1254
1255 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1256 unsigned int epid)
1257 {
1258 XHCISlot *slot;
1259 XHCIEPContext *epctx;
1260
1261 trace_usb_xhci_ep_stop(slotid, epid);
1262 assert(slotid >= 1 && slotid <= xhci->numslots);
1263
1264 if (epid < 1 || epid > 31) {
1265 DPRINTF("xhci: bad ep %d\n", epid);
1266 return CC_TRB_ERROR;
1267 }
1268
1269 slot = &xhci->slots[slotid-1];
1270
1271 if (!slot->eps[epid-1]) {
1272 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1273 return CC_EP_NOT_ENABLED_ERROR;
1274 }
1275
1276 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1277 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1278 "data might be lost\n");
1279 }
1280
1281 epctx = slot->eps[epid-1];
1282
1283 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1284
1285 if (epctx->nr_pstreams) {
1286 xhci_reset_streams(epctx);
1287 }
1288
1289 return CC_SUCCESS;
1290 }
1291
1292 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1293 unsigned int epid)
1294 {
1295 XHCISlot *slot;
1296 XHCIEPContext *epctx;
1297
1298 trace_usb_xhci_ep_reset(slotid, epid);
1299 assert(slotid >= 1 && slotid <= xhci->numslots);
1300
1301 if (epid < 1 || epid > 31) {
1302 DPRINTF("xhci: bad ep %d\n", epid);
1303 return CC_TRB_ERROR;
1304 }
1305
1306 slot = &xhci->slots[slotid-1];
1307
1308 if (!slot->eps[epid-1]) {
1309 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1310 return CC_EP_NOT_ENABLED_ERROR;
1311 }
1312
1313 epctx = slot->eps[epid-1];
1314
1315 if (epctx->state != EP_HALTED) {
1316 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1317 epid, epctx->state);
1318 return CC_CONTEXT_STATE_ERROR;
1319 }
1320
1321 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1322 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1323 "data might be lost\n");
1324 }
1325
1326 if (!xhci->slots[slotid-1].uport ||
1327 !xhci->slots[slotid-1].uport->dev ||
1328 !xhci->slots[slotid-1].uport->dev->attached) {
1329 return CC_USB_TRANSACTION_ERROR;
1330 }
1331
1332 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1333
1334 if (epctx->nr_pstreams) {
1335 xhci_reset_streams(epctx);
1336 }
1337
1338 return CC_SUCCESS;
1339 }
1340
1341 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1342 unsigned int epid, unsigned int streamid,
1343 uint64_t pdequeue)
1344 {
1345 XHCISlot *slot;
1346 XHCIEPContext *epctx;
1347 XHCIStreamContext *sctx;
1348 dma_addr_t dequeue;
1349
1350 assert(slotid >= 1 && slotid <= xhci->numslots);
1351
1352 if (epid < 1 || epid > 31) {
1353 DPRINTF("xhci: bad ep %d\n", epid);
1354 return CC_TRB_ERROR;
1355 }
1356
1357 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1358 dequeue = xhci_mask64(pdequeue);
1359
1360 slot = &xhci->slots[slotid-1];
1361
1362 if (!slot->eps[epid-1]) {
1363 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1364 return CC_EP_NOT_ENABLED_ERROR;
1365 }
1366
1367 epctx = slot->eps[epid-1];
1368
1369 if (epctx->state != EP_STOPPED) {
1370 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1371 return CC_CONTEXT_STATE_ERROR;
1372 }
1373
1374 if (epctx->nr_pstreams) {
1375 uint32_t err;
1376 sctx = xhci_find_stream(epctx, streamid, &err);
1377 if (sctx == NULL) {
1378 return err;
1379 }
1380 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1381 sctx->ring.ccs = dequeue & 1;
1382 } else {
1383 sctx = NULL;
1384 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1385 epctx->ring.ccs = dequeue & 1;
1386 }
1387
1388 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1389
1390 return CC_SUCCESS;
1391 }
1392
1393 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1394 {
1395 XHCIState *xhci = xfer->epctx->xhci;
1396 int i;
1397
1398 xfer->int_req = false;
1399 qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as);
1400 for (i = 0; i < xfer->trb_count; i++) {
1401 XHCITRB *trb = &xfer->trbs[i];
1402 dma_addr_t addr;
1403 unsigned int chunk = 0;
1404
1405 if (trb->control & TRB_TR_IOC) {
1406 xfer->int_req = true;
1407 }
1408
1409 switch (TRB_TYPE(*trb)) {
1410 case TR_DATA:
1411 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1412 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1413 goto err;
1414 }
1415 /* fallthrough */
1416 case TR_NORMAL:
1417 case TR_ISOCH:
1418 addr = xhci_mask64(trb->parameter);
1419 chunk = trb->status & 0x1ffff;
1420 if (trb->control & TRB_TR_IDT) {
1421 if (chunk > 8 || in_xfer) {
1422 DPRINTF("xhci: invalid immediate data TRB\n");
1423 goto err;
1424 }
1425 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1426 } else {
1427 qemu_sglist_add(&xfer->sgl, addr, chunk);
1428 }
1429 break;
1430 }
1431 }
1432
1433 return 0;
1434
1435 err:
1436 qemu_sglist_destroy(&xfer->sgl);
1437 xhci_die(xhci);
1438 return -1;
1439 }
1440
1441 static void xhci_xfer_unmap(XHCITransfer *xfer)
1442 {
1443 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1444 qemu_sglist_destroy(&xfer->sgl);
1445 }
1446
1447 static void xhci_xfer_report(XHCITransfer *xfer)
1448 {
1449 uint32_t edtla = 0;
1450 unsigned int left;
1451 bool reported = 0;
1452 bool shortpkt = 0;
1453 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1454 XHCIState *xhci = xfer->epctx->xhci;
1455 int i;
1456
1457 left = xfer->packet.actual_length;
1458
1459 for (i = 0; i < xfer->trb_count; i++) {
1460 XHCITRB *trb = &xfer->trbs[i];
1461 unsigned int chunk = 0;
1462
1463 switch (TRB_TYPE(*trb)) {
1464 case TR_SETUP:
1465 chunk = trb->status & 0x1ffff;
1466 if (chunk > 8) {
1467 chunk = 8;
1468 }
1469 break;
1470 case TR_DATA:
1471 case TR_NORMAL:
1472 case TR_ISOCH:
1473 chunk = trb->status & 0x1ffff;
1474 if (chunk > left) {
1475 chunk = left;
1476 if (xfer->status == CC_SUCCESS) {
1477 shortpkt = 1;
1478 }
1479 }
1480 left -= chunk;
1481 edtla += chunk;
1482 break;
1483 case TR_STATUS:
1484 reported = 0;
1485 shortpkt = 0;
1486 break;
1487 }
1488
1489 if (!reported && ((trb->control & TRB_TR_IOC) ||
1490 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1491 (xfer->status != CC_SUCCESS && left == 0))) {
1492 event.slotid = xfer->epctx->slotid;
1493 event.epid = xfer->epctx->epid;
1494 event.length = (trb->status & 0x1ffff) - chunk;
1495 event.flags = 0;
1496 event.ptr = trb->addr;
1497 if (xfer->status == CC_SUCCESS) {
1498 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1499 } else {
1500 event.ccode = xfer->status;
1501 }
1502 if (TRB_TYPE(*trb) == TR_EVDATA) {
1503 event.ptr = trb->parameter;
1504 event.flags |= TRB_EV_ED;
1505 event.length = edtla & 0xffffff;
1506 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1507 edtla = 0;
1508 }
1509 xhci_event(xhci, &event, TRB_INTR(*trb));
1510 reported = 1;
1511 if (xfer->status != CC_SUCCESS) {
1512 return;
1513 }
1514 }
1515
1516 switch (TRB_TYPE(*trb)) {
1517 case TR_SETUP:
1518 reported = 0;
1519 shortpkt = 0;
1520 break;
1521 }
1522
1523 }
1524 }
1525
1526 static void xhci_stall_ep(XHCITransfer *xfer)
1527 {
1528 XHCIEPContext *epctx = xfer->epctx;
1529 XHCIState *xhci = epctx->xhci;
1530 uint32_t err;
1531 XHCIStreamContext *sctx;
1532
1533 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1534 /* never halt isoch endpoints, 4.10.2 */
1535 return;
1536 }
1537
1538 if (epctx->nr_pstreams) {
1539 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1540 if (sctx == NULL) {
1541 return;
1542 }
1543 sctx->ring.dequeue = xfer->trbs[0].addr;
1544 sctx->ring.ccs = xfer->trbs[0].ccs;
1545 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1546 } else {
1547 epctx->ring.dequeue = xfer->trbs[0].addr;
1548 epctx->ring.ccs = xfer->trbs[0].ccs;
1549 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1550 }
1551 }
1552
1553 static int xhci_setup_packet(XHCITransfer *xfer)
1554 {
1555 USBEndpoint *ep;
1556 int dir;
1557
1558 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1559
1560 if (xfer->packet.ep) {
1561 ep = xfer->packet.ep;
1562 } else {
1563 ep = xhci_epid_to_usbep(xfer->epctx);
1564 if (!ep) {
1565 DPRINTF("xhci: slot %d has no device\n",
1566 xfer->epctx->slotid);
1567 return -1;
1568 }
1569 }
1570
1571 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1572 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1573 xfer->trbs[0].addr, false, xfer->int_req);
1574 if (usb_packet_map(&xfer->packet, &xfer->sgl)) {
1575 qemu_sglist_destroy(&xfer->sgl);
1576 return -1;
1577 }
1578 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1579 xfer->packet.pid, ep->dev->addr, ep->nr);
1580 return 0;
1581 }
1582
1583 static int xhci_try_complete_packet(XHCITransfer *xfer)
1584 {
1585 if (xfer->packet.status == USB_RET_ASYNC) {
1586 trace_usb_xhci_xfer_async(xfer);
1587 xfer->running_async = 1;
1588 xfer->running_retry = 0;
1589 xfer->complete = 0;
1590 return 0;
1591 } else if (xfer->packet.status == USB_RET_NAK) {
1592 trace_usb_xhci_xfer_nak(xfer);
1593 xfer->running_async = 0;
1594 xfer->running_retry = 1;
1595 xfer->complete = 0;
1596 return 0;
1597 } else {
1598 xfer->running_async = 0;
1599 xfer->running_retry = 0;
1600 xfer->complete = 1;
1601 xhci_xfer_unmap(xfer);
1602 }
1603
1604 if (xfer->packet.status == USB_RET_SUCCESS) {
1605 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1606 xfer->status = CC_SUCCESS;
1607 xhci_xfer_report(xfer);
1608 return 0;
1609 }
1610
1611 /* error */
1612 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1613 switch (xfer->packet.status) {
1614 case USB_RET_NODEV:
1615 case USB_RET_IOERROR:
1616 xfer->status = CC_USB_TRANSACTION_ERROR;
1617 xhci_xfer_report(xfer);
1618 xhci_stall_ep(xfer);
1619 break;
1620 case USB_RET_STALL:
1621 xfer->status = CC_STALL_ERROR;
1622 xhci_xfer_report(xfer);
1623 xhci_stall_ep(xfer);
1624 break;
1625 case USB_RET_BABBLE:
1626 xfer->status = CC_BABBLE_DETECTED;
1627 xhci_xfer_report(xfer);
1628 xhci_stall_ep(xfer);
1629 break;
1630 default:
1631 DPRINTF("%s: FIXME: status = %d\n", __func__,
1632 xfer->packet.status);
1633 FIXME("unhandled USB_RET_*");
1634 }
1635 return 0;
1636 }
1637
1638 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1639 {
1640 XHCITRB *trb_setup, *trb_status;
1641 uint8_t bmRequestType;
1642
1643 trb_setup = &xfer->trbs[0];
1644 trb_status = &xfer->trbs[xfer->trb_count-1];
1645
1646 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1647 xfer->epctx->epid, xfer->streamid);
1648
1649 /* at most one Event Data TRB allowed after STATUS */
1650 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1651 trb_status--;
1652 }
1653
1654 /* do some sanity checks */
1655 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1656 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1657 TRB_TYPE(*trb_setup));
1658 return -1;
1659 }
1660 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1661 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1662 TRB_TYPE(*trb_status));
1663 return -1;
1664 }
1665 if (!(trb_setup->control & TRB_TR_IDT)) {
1666 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1667 return -1;
1668 }
1669 if ((trb_setup->status & 0x1ffff) != 8) {
1670 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1671 (trb_setup->status & 0x1ffff));
1672 return -1;
1673 }
1674
1675 bmRequestType = trb_setup->parameter;
1676
1677 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1678 xfer->iso_xfer = false;
1679 xfer->timed_xfer = false;
1680
1681 if (xhci_setup_packet(xfer) < 0) {
1682 return -1;
1683 }
1684 xfer->packet.parameter = trb_setup->parameter;
1685
1686 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1687 xhci_try_complete_packet(xfer);
1688 return 0;
1689 }
1690
1691 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1692 XHCIEPContext *epctx, uint64_t mfindex)
1693 {
1694 uint64_t asap = ((mfindex + epctx->interval - 1) &
1695 ~(epctx->interval-1));
1696 uint64_t kick = epctx->mfindex_last + epctx->interval;
1697
1698 assert(epctx->interval != 0);
1699 xfer->mfindex_kick = MAX(asap, kick);
1700 }
1701
1702 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1703 XHCIEPContext *epctx, uint64_t mfindex)
1704 {
1705 if (xfer->trbs[0].control & TRB_TR_SIA) {
1706 uint64_t asap = ((mfindex + epctx->interval - 1) &
1707 ~(epctx->interval-1));
1708 if (asap >= epctx->mfindex_last &&
1709 asap <= epctx->mfindex_last + epctx->interval * 4) {
1710 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1711 } else {
1712 xfer->mfindex_kick = asap;
1713 }
1714 } else {
1715 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1716 & TRB_TR_FRAMEID_MASK) << 3;
1717 xfer->mfindex_kick |= mfindex & ~0x3fff;
1718 if (xfer->mfindex_kick + 0x100 < mfindex) {
1719 xfer->mfindex_kick += 0x4000;
1720 }
1721 }
1722 }
1723
1724 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1725 XHCIEPContext *epctx, uint64_t mfindex)
1726 {
1727 if (xfer->mfindex_kick > mfindex) {
1728 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1729 (xfer->mfindex_kick - mfindex) * 125000);
1730 xfer->running_retry = 1;
1731 } else {
1732 epctx->mfindex_last = xfer->mfindex_kick;
1733 timer_del(epctx->kick_timer);
1734 xfer->running_retry = 0;
1735 }
1736 }
1737
1738
1739 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1740 {
1741 uint64_t mfindex;
1742
1743 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid);
1744
1745 xfer->in_xfer = epctx->type>>2;
1746
1747 switch(epctx->type) {
1748 case ET_INTR_OUT:
1749 case ET_INTR_IN:
1750 xfer->pkts = 0;
1751 xfer->iso_xfer = false;
1752 xfer->timed_xfer = true;
1753 mfindex = xhci_mfindex_get(xhci);
1754 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1755 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1756 if (xfer->running_retry) {
1757 return -1;
1758 }
1759 break;
1760 case ET_BULK_OUT:
1761 case ET_BULK_IN:
1762 xfer->pkts = 0;
1763 xfer->iso_xfer = false;
1764 xfer->timed_xfer = false;
1765 break;
1766 case ET_ISO_OUT:
1767 case ET_ISO_IN:
1768 xfer->pkts = 1;
1769 xfer->iso_xfer = true;
1770 xfer->timed_xfer = true;
1771 mfindex = xhci_mfindex_get(xhci);
1772 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1773 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1774 if (xfer->running_retry) {
1775 return -1;
1776 }
1777 break;
1778 default:
1779 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
1780 return -1;
1781 }
1782
1783 if (xhci_setup_packet(xfer) < 0) {
1784 return -1;
1785 }
1786 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1787 xhci_try_complete_packet(xfer);
1788 return 0;
1789 }
1790
1791 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1792 {
1793 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1794 xfer->epctx->epid, xfer->streamid);
1795 return xhci_submit(xhci, xfer, epctx);
1796 }
1797
1798 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1799 unsigned int epid, unsigned int streamid)
1800 {
1801 XHCIEPContext *epctx;
1802
1803 assert(slotid >= 1 && slotid <= xhci->numslots);
1804 assert(epid >= 1 && epid <= 31);
1805
1806 if (!xhci->slots[slotid-1].enabled) {
1807 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1808 return;
1809 }
1810 epctx = xhci->slots[slotid-1].eps[epid-1];
1811 if (!epctx) {
1812 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1813 epid, slotid);
1814 return;
1815 }
1816
1817 if (epctx->kick_active) {
1818 return;
1819 }
1820 xhci_kick_epctx(epctx, streamid);
1821 }
1822
1823 static bool xhci_slot_ok(XHCIState *xhci, int slotid)
1824 {
1825 return (xhci->slots[slotid - 1].uport &&
1826 xhci->slots[slotid - 1].uport->dev &&
1827 xhci->slots[slotid - 1].uport->dev->attached);
1828 }
1829
1830 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
1831 {
1832 XHCIState *xhci = epctx->xhci;
1833 XHCIStreamContext *stctx = NULL;
1834 XHCITransfer *xfer;
1835 XHCIRing *ring;
1836 USBEndpoint *ep = NULL;
1837 uint64_t mfindex;
1838 unsigned int count = 0;
1839 int length;
1840 int i;
1841
1842 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid);
1843 assert(!epctx->kick_active);
1844
1845 /* If the device has been detached, but the guest has not noticed this
1846 yet the 2 above checks will succeed, but we must NOT continue */
1847 if (!xhci_slot_ok(xhci, epctx->slotid)) {
1848 return;
1849 }
1850
1851 if (epctx->retry) {
1852 XHCITransfer *xfer = epctx->retry;
1853
1854 trace_usb_xhci_xfer_retry(xfer);
1855 assert(xfer->running_retry);
1856 if (xfer->timed_xfer) {
1857 /* time to kick the transfer? */
1858 mfindex = xhci_mfindex_get(xhci);
1859 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1860 if (xfer->running_retry) {
1861 return;
1862 }
1863 xfer->timed_xfer = 0;
1864 xfer->running_retry = 1;
1865 }
1866 if (xfer->iso_xfer) {
1867 /* retry iso transfer */
1868 if (xhci_setup_packet(xfer) < 0) {
1869 return;
1870 }
1871 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1872 assert(xfer->packet.status != USB_RET_NAK);
1873 xhci_try_complete_packet(xfer);
1874 } else {
1875 /* retry nak'ed transfer */
1876 if (xhci_setup_packet(xfer) < 0) {
1877 return;
1878 }
1879 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1880 if (xfer->packet.status == USB_RET_NAK) {
1881 xhci_xfer_unmap(xfer);
1882 return;
1883 }
1884 xhci_try_complete_packet(xfer);
1885 }
1886 assert(!xfer->running_retry);
1887 if (xfer->complete) {
1888 /* update ring dequeue ptr */
1889 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
1890 xhci_ep_free_xfer(epctx->retry);
1891 }
1892 epctx->retry = NULL;
1893 }
1894
1895 if (epctx->state == EP_HALTED) {
1896 DPRINTF("xhci: ep halted, not running schedule\n");
1897 return;
1898 }
1899
1900
1901 if (epctx->nr_pstreams) {
1902 uint32_t err;
1903 stctx = xhci_find_stream(epctx, streamid, &err);
1904 if (stctx == NULL) {
1905 return;
1906 }
1907 ring = &stctx->ring;
1908 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
1909 } else {
1910 ring = &epctx->ring;
1911 streamid = 0;
1912 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
1913 }
1914 if (!ring->dequeue) {
1915 return;
1916 }
1917
1918 epctx->kick_active++;
1919 while (1) {
1920 length = xhci_ring_chain_length(xhci, ring);
1921 if (length <= 0) {
1922 if (epctx->type == ET_ISO_OUT || epctx->type == ET_ISO_IN) {
1923 /* 4.10.3.1 */
1924 XHCIEvent ev = { ER_TRANSFER };
1925 ev.ccode = epctx->type == ET_ISO_IN ?
1926 CC_RING_OVERRUN : CC_RING_UNDERRUN;
1927 ev.slotid = epctx->slotid;
1928 ev.epid = epctx->epid;
1929 ev.ptr = epctx->ring.dequeue;
1930 xhci_event(xhci, &ev, xhci->slots[epctx->slotid-1].intr);
1931 }
1932 break;
1933 }
1934 xfer = xhci_ep_alloc_xfer(epctx, length);
1935 if (xfer == NULL) {
1936 break;
1937 }
1938
1939 for (i = 0; i < length; i++) {
1940 TRBType type;
1941 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
1942 if (!type) {
1943 xhci_die(xhci);
1944 xhci_ep_free_xfer(xfer);
1945 epctx->kick_active--;
1946 return;
1947 }
1948 }
1949 xfer->streamid = streamid;
1950
1951 if (epctx->epid == 1) {
1952 xhci_fire_ctl_transfer(xhci, xfer);
1953 } else {
1954 xhci_fire_transfer(xhci, xfer, epctx);
1955 }
1956 if (!xhci_slot_ok(xhci, epctx->slotid)) {
1957 /* surprise removal -> stop processing */
1958 break;
1959 }
1960 if (xfer->complete) {
1961 /* update ring dequeue ptr */
1962 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
1963 xhci_ep_free_xfer(xfer);
1964 xfer = NULL;
1965 }
1966
1967 if (epctx->state == EP_HALTED) {
1968 break;
1969 }
1970 if (xfer != NULL && xfer->running_retry) {
1971 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1972 epctx->retry = xfer;
1973 xhci_xfer_unmap(xfer);
1974 break;
1975 }
1976 if (count++ > TRANSFER_LIMIT) {
1977 trace_usb_xhci_enforced_limit("transfers");
1978 break;
1979 }
1980 }
1981 epctx->kick_active--;
1982
1983 ep = xhci_epid_to_usbep(epctx);
1984 if (ep) {
1985 usb_device_flush_ep_queue(ep->dev, ep);
1986 }
1987 }
1988
1989 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1990 {
1991 trace_usb_xhci_slot_enable(slotid);
1992 assert(slotid >= 1 && slotid <= xhci->numslots);
1993 xhci->slots[slotid-1].enabled = 1;
1994 xhci->slots[slotid-1].uport = NULL;
1995 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1996
1997 return CC_SUCCESS;
1998 }
1999
2000 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2001 {
2002 int i;
2003
2004 trace_usb_xhci_slot_disable(slotid);
2005 assert(slotid >= 1 && slotid <= xhci->numslots);
2006
2007 for (i = 1; i <= 31; i++) {
2008 if (xhci->slots[slotid-1].eps[i-1]) {
2009 xhci_disable_ep(xhci, slotid, i);
2010 }
2011 }
2012
2013 xhci->slots[slotid-1].enabled = 0;
2014 xhci->slots[slotid-1].addressed = 0;
2015 xhci->slots[slotid-1].uport = NULL;
2016 xhci->slots[slotid-1].intr = 0;
2017 return CC_SUCCESS;
2018 }
2019
2020 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2021 {
2022 USBPort *uport;
2023 char path[32];
2024 int i, pos, port;
2025
2026 port = (slot_ctx[1]>>16) & 0xFF;
2027 if (port < 1 || port > xhci->numports) {
2028 return NULL;
2029 }
2030 port = xhci->ports[port-1].uport->index+1;
2031 pos = snprintf(path, sizeof(path), "%d", port);
2032 for (i = 0; i < 5; i++) {
2033 port = (slot_ctx[0] >> 4*i) & 0x0f;
2034 if (!port) {
2035 break;
2036 }
2037 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2038 }
2039
2040 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2041 if (strcmp(uport->path, path) == 0) {
2042 return uport;
2043 }
2044 }
2045 return NULL;
2046 }
2047
2048 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2049 uint64_t pictx, bool bsr)
2050 {
2051 XHCISlot *slot;
2052 USBPort *uport;
2053 USBDevice *dev;
2054 dma_addr_t ictx, octx, dcbaap;
2055 uint64_t poctx;
2056 uint32_t ictl_ctx[2];
2057 uint32_t slot_ctx[4];
2058 uint32_t ep0_ctx[5];
2059 int i;
2060 TRBCCode res;
2061
2062 assert(slotid >= 1 && slotid <= xhci->numslots);
2063
2064 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2065 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &poctx, MEMTXATTRS_UNSPECIFIED);
2066 ictx = xhci_mask64(pictx);
2067 octx = xhci_mask64(poctx);
2068
2069 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2070 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2071
2072 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2073
2074 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2075 DPRINTF("xhci: invalid input context control %08x %08x\n",
2076 ictl_ctx[0], ictl_ctx[1]);
2077 return CC_TRB_ERROR;
2078 }
2079
2080 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2081 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2082
2083 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2084 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2085
2086 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2087 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2088
2089 uport = xhci_lookup_uport(xhci, slot_ctx);
2090 if (uport == NULL) {
2091 DPRINTF("xhci: port not found\n");
2092 return CC_TRB_ERROR;
2093 }
2094 trace_usb_xhci_slot_address(slotid, uport->path);
2095
2096 dev = uport->dev;
2097 if (!dev || !dev->attached) {
2098 DPRINTF("xhci: port %s not connected\n", uport->path);
2099 return CC_USB_TRANSACTION_ERROR;
2100 }
2101
2102 for (i = 0; i < xhci->numslots; i++) {
2103 if (i == slotid-1) {
2104 continue;
2105 }
2106 if (xhci->slots[i].uport == uport) {
2107 DPRINTF("xhci: port %s already assigned to slot %d\n",
2108 uport->path, i+1);
2109 return CC_TRB_ERROR;
2110 }
2111 }
2112
2113 slot = &xhci->slots[slotid-1];
2114 slot->uport = uport;
2115 slot->ctx = octx;
2116 slot->intr = get_field(slot_ctx[2], TRB_INTR);
2117
2118 /* Make sure device is in USB_STATE_DEFAULT state */
2119 usb_device_reset(dev);
2120 if (bsr) {
2121 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2122 } else {
2123 USBPacket p;
2124 uint8_t buf[1];
2125
2126 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2127 memset(&p, 0, sizeof(p));
2128 usb_packet_addbuf(&p, buf, sizeof(buf));
2129 usb_packet_setup(&p, USB_TOKEN_OUT,
2130 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2131 0, false, false);
2132 usb_device_handle_control(dev, &p,
2133 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2134 slotid, 0, 0, NULL);
2135 assert(p.status != USB_RET_ASYNC);
2136 usb_packet_cleanup(&p);
2137 }
2138
2139 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2140
2141 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2142 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2143 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2144 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2145
2146 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2147 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2148
2149 xhci->slots[slotid-1].addressed = 1;
2150 return res;
2151 }
2152
2153
2154 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2155 uint64_t pictx, bool dc)
2156 {
2157 dma_addr_t ictx, octx;
2158 uint32_t ictl_ctx[2];
2159 uint32_t slot_ctx[4];
2160 uint32_t islot_ctx[4];
2161 uint32_t ep_ctx[5];
2162 int i;
2163 TRBCCode res;
2164
2165 trace_usb_xhci_slot_configure(slotid);
2166 assert(slotid >= 1 && slotid <= xhci->numslots);
2167
2168 ictx = xhci_mask64(pictx);
2169 octx = xhci->slots[slotid-1].ctx;
2170
2171 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2172 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2173
2174 if (dc) {
2175 for (i = 2; i <= 31; i++) {
2176 if (xhci->slots[slotid-1].eps[i-1]) {
2177 xhci_disable_ep(xhci, slotid, i);
2178 }
2179 }
2180
2181 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2182 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2183 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2184 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2185 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2186 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2187
2188 return CC_SUCCESS;
2189 }
2190
2191 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2192
2193 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2194 DPRINTF("xhci: invalid input context control %08x %08x\n",
2195 ictl_ctx[0], ictl_ctx[1]);
2196 return CC_TRB_ERROR;
2197 }
2198
2199 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2200 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2201
2202 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2203 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2204 return CC_CONTEXT_STATE_ERROR;
2205 }
2206
2207 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2208
2209 for (i = 2; i <= 31; i++) {
2210 if (ictl_ctx[0] & (1<<i)) {
2211 xhci_disable_ep(xhci, slotid, i);
2212 }
2213 if (ictl_ctx[1] & (1<<i)) {
2214 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2215 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2216 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2217 ep_ctx[3], ep_ctx[4]);
2218 xhci_disable_ep(xhci, slotid, i);
2219 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2220 if (res != CC_SUCCESS) {
2221 return res;
2222 }
2223 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2224 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2225 ep_ctx[3], ep_ctx[4]);
2226 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2227 }
2228 }
2229
2230 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2231 if (res != CC_SUCCESS) {
2232 for (i = 2; i <= 31; i++) {
2233 if (ictl_ctx[1] & (1u << i)) {
2234 xhci_disable_ep(xhci, slotid, i);
2235 }
2236 }
2237 return res;
2238 }
2239
2240 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2241 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2242 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2243 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2244 SLOT_CONTEXT_ENTRIES_SHIFT);
2245 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2246 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2247
2248 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2249
2250 return CC_SUCCESS;
2251 }
2252
2253
2254 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2255 uint64_t pictx)
2256 {
2257 dma_addr_t ictx, octx;
2258 uint32_t ictl_ctx[2];
2259 uint32_t iep0_ctx[5];
2260 uint32_t ep0_ctx[5];
2261 uint32_t islot_ctx[4];
2262 uint32_t slot_ctx[4];
2263
2264 trace_usb_xhci_slot_evaluate(slotid);
2265 assert(slotid >= 1 && slotid <= xhci->numslots);
2266
2267 ictx = xhci_mask64(pictx);
2268 octx = xhci->slots[slotid-1].ctx;
2269
2270 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2271 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2272
2273 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2274
2275 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2276 DPRINTF("xhci: invalid input context control %08x %08x\n",
2277 ictl_ctx[0], ictl_ctx[1]);
2278 return CC_TRB_ERROR;
2279 }
2280
2281 if (ictl_ctx[1] & 0x1) {
2282 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2283
2284 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2285 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2286
2287 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2288
2289 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2290 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2291 /* update interrupter target field */
2292 xhci->slots[slotid-1].intr = get_field(islot_ctx[2], TRB_INTR);
2293 set_field(&slot_ctx[2], xhci->slots[slotid-1].intr, TRB_INTR);
2294
2295 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2296 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2297
2298 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2299 }
2300
2301 if (ictl_ctx[1] & 0x2) {
2302 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2303
2304 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2305 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2306 iep0_ctx[3], iep0_ctx[4]);
2307
2308 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2309
2310 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2311 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2312
2313 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2314 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2315
2316 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2317 }
2318
2319 return CC_SUCCESS;
2320 }
2321
2322 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2323 {
2324 uint32_t slot_ctx[4];
2325 dma_addr_t octx;
2326 int i;
2327
2328 trace_usb_xhci_slot_reset(slotid);
2329 assert(slotid >= 1 && slotid <= xhci->numslots);
2330
2331 octx = xhci->slots[slotid-1].ctx;
2332
2333 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2334
2335 for (i = 2; i <= 31; i++) {
2336 if (xhci->slots[slotid-1].eps[i-1]) {
2337 xhci_disable_ep(xhci, slotid, i);
2338 }
2339 }
2340
2341 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2342 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2343 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2344 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2345 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2346 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2347
2348 return CC_SUCCESS;
2349 }
2350
2351 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2352 {
2353 unsigned int slotid;
2354 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2355 if (slotid < 1 || slotid > xhci->numslots) {
2356 DPRINTF("xhci: bad slot id %d\n", slotid);
2357 event->ccode = CC_TRB_ERROR;
2358 return 0;
2359 } else if (!xhci->slots[slotid-1].enabled) {
2360 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2361 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2362 return 0;
2363 }
2364 return slotid;
2365 }
2366
2367 /* cleanup slot state on usb device detach */
2368 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2369 {
2370 int slot, ep;
2371
2372 for (slot = 0; slot < xhci->numslots; slot++) {
2373 if (xhci->slots[slot].uport == uport) {
2374 break;
2375 }
2376 }
2377 if (slot == xhci->numslots) {
2378 return;
2379 }
2380
2381 for (ep = 0; ep < 31; ep++) {
2382 if (xhci->slots[slot].eps[ep]) {
2383 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2384 }
2385 }
2386 xhci->slots[slot].uport = NULL;
2387 }
2388
2389 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2390 {
2391 dma_addr_t ctx;
2392 uint8_t bw_ctx[xhci->numports+1];
2393
2394 DPRINTF("xhci_get_port_bandwidth()\n");
2395
2396 ctx = xhci_mask64(pctx);
2397
2398 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2399
2400 /* TODO: actually implement real values here */
2401 bw_ctx[0] = 0;
2402 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2403 dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx),
2404 MEMTXATTRS_UNSPECIFIED);
2405
2406 return CC_SUCCESS;
2407 }
2408
2409 static uint32_t rotl(uint32_t v, unsigned count)
2410 {
2411 count &= 31;
2412 return (v << count) | (v >> (32 - count));
2413 }
2414
2415
2416 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2417 {
2418 uint32_t val;
2419 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2420 val += rotl(lo + 0x49434878, hi & 0x1F);
2421 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2422 return ~val;
2423 }
2424
2425 static void xhci_process_commands(XHCIState *xhci)
2426 {
2427 XHCITRB trb;
2428 TRBType type;
2429 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2430 dma_addr_t addr;
2431 unsigned int i, slotid = 0, count = 0;
2432
2433 DPRINTF("xhci_process_commands()\n");
2434 if (!xhci_running(xhci)) {
2435 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2436 return;
2437 }
2438
2439 xhci->crcr_low |= CRCR_CRR;
2440
2441 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2442 event.ptr = addr;
2443 switch (type) {
2444 case CR_ENABLE_SLOT:
2445 for (i = 0; i < xhci->numslots; i++) {
2446 if (!xhci->slots[i].enabled) {
2447 break;
2448 }
2449 }
2450 if (i >= xhci->numslots) {
2451 DPRINTF("xhci: no device slots available\n");
2452 event.ccode = CC_NO_SLOTS_ERROR;
2453 } else {
2454 slotid = i+1;
2455 event.ccode = xhci_enable_slot(xhci, slotid);
2456 }
2457 break;
2458 case CR_DISABLE_SLOT:
2459 slotid = xhci_get_slot(xhci, &event, &trb);
2460 if (slotid) {
2461 event.ccode = xhci_disable_slot(xhci, slotid);
2462 }
2463 break;
2464 case CR_ADDRESS_DEVICE:
2465 slotid = xhci_get_slot(xhci, &event, &trb);
2466 if (slotid) {
2467 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2468 trb.control & TRB_CR_BSR);
2469 }
2470 break;
2471 case CR_CONFIGURE_ENDPOINT:
2472 slotid = xhci_get_slot(xhci, &event, &trb);
2473 if (slotid) {
2474 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2475 trb.control & TRB_CR_DC);
2476 }
2477 break;
2478 case CR_EVALUATE_CONTEXT:
2479 slotid = xhci_get_slot(xhci, &event, &trb);
2480 if (slotid) {
2481 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2482 }
2483 break;
2484 case CR_STOP_ENDPOINT:
2485 slotid = xhci_get_slot(xhci, &event, &trb);
2486 if (slotid) {
2487 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2488 & TRB_CR_EPID_MASK;
2489 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2490 }
2491 break;
2492 case CR_RESET_ENDPOINT:
2493 slotid = xhci_get_slot(xhci, &event, &trb);
2494 if (slotid) {
2495 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2496 & TRB_CR_EPID_MASK;
2497 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2498 }
2499 break;
2500 case CR_SET_TR_DEQUEUE:
2501 slotid = xhci_get_slot(xhci, &event, &trb);
2502 if (slotid) {
2503 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2504 & TRB_CR_EPID_MASK;
2505 unsigned int streamid = (trb.status >> 16) & 0xffff;
2506 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2507 epid, streamid,
2508 trb.parameter);
2509 }
2510 break;
2511 case CR_RESET_DEVICE:
2512 slotid = xhci_get_slot(xhci, &event, &trb);
2513 if (slotid) {
2514 event.ccode = xhci_reset_slot(xhci, slotid);
2515 }
2516 break;
2517 case CR_GET_PORT_BANDWIDTH:
2518 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2519 break;
2520 case CR_NOOP:
2521 event.ccode = CC_SUCCESS;
2522 break;
2523 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2524 if (xhci->nec_quirks) {
2525 event.type = 48; /* NEC reply */
2526 event.length = 0x3025;
2527 } else {
2528 event.ccode = CC_TRB_ERROR;
2529 }
2530 break;
2531 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2532 if (xhci->nec_quirks) {
2533 uint32_t chi = trb.parameter >> 32;
2534 uint32_t clo = trb.parameter;
2535 uint32_t val = xhci_nec_challenge(chi, clo);
2536 event.length = val & 0xFFFF;
2537 event.epid = val >> 16;
2538 slotid = val >> 24;
2539 event.type = 48; /* NEC reply */
2540 } else {
2541 event.ccode = CC_TRB_ERROR;
2542 }
2543 break;
2544 default:
2545 trace_usb_xhci_unimplemented("command", type);
2546 event.ccode = CC_TRB_ERROR;
2547 break;
2548 }
2549 event.slotid = slotid;
2550 xhci_event(xhci, &event, 0);
2551
2552 if (count++ > COMMAND_LIMIT) {
2553 trace_usb_xhci_enforced_limit("commands");
2554 return;
2555 }
2556 }
2557 }
2558
2559 static bool xhci_port_have_device(XHCIPort *port)
2560 {
2561 if (!port->uport->dev || !port->uport->dev->attached) {
2562 return false; /* no device present */
2563 }
2564 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2565 return false; /* speed mismatch */
2566 }
2567 return true;
2568 }
2569
2570 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2571 {
2572 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2573 port->portnr << 24 };
2574
2575 if ((port->portsc & bits) == bits) {
2576 return;
2577 }
2578 trace_usb_xhci_port_notify(port->portnr, bits);
2579 port->portsc |= bits;
2580 if (!xhci_running(port->xhci)) {
2581 return;
2582 }
2583 xhci_event(port->xhci, &ev, 0);
2584 }
2585
2586 static void xhci_port_update(XHCIPort *port, int is_detach)
2587 {
2588 uint32_t pls = PLS_RX_DETECT;
2589
2590 assert(port);
2591 port->portsc = PORTSC_PP;
2592 if (!is_detach && xhci_port_have_device(port)) {
2593 port->portsc |= PORTSC_CCS;
2594 switch (port->uport->dev->speed) {
2595 case USB_SPEED_LOW:
2596 port->portsc |= PORTSC_SPEED_LOW;
2597 pls = PLS_POLLING;
2598 break;
2599 case USB_SPEED_FULL:
2600 port->portsc |= PORTSC_SPEED_FULL;
2601 pls = PLS_POLLING;
2602 break;
2603 case USB_SPEED_HIGH:
2604 port->portsc |= PORTSC_SPEED_HIGH;
2605 pls = PLS_POLLING;
2606 break;
2607 case USB_SPEED_SUPER:
2608 port->portsc |= PORTSC_SPEED_SUPER;
2609 port->portsc |= PORTSC_PED;
2610 pls = PLS_U0;
2611 break;
2612 }
2613 }
2614 set_field(&port->portsc, pls, PORTSC_PLS);
2615 trace_usb_xhci_port_link(port->portnr, pls);
2616 xhci_port_notify(port, PORTSC_CSC);
2617 }
2618
2619 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2620 {
2621 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2622
2623 if (!xhci_port_have_device(port)) {
2624 return;
2625 }
2626
2627 usb_device_reset(port->uport->dev);
2628
2629 switch (port->uport->dev->speed) {
2630 case USB_SPEED_SUPER:
2631 if (warm_reset) {
2632 port->portsc |= PORTSC_WRC;
2633 }
2634 /* fall through */
2635 case USB_SPEED_LOW:
2636 case USB_SPEED_FULL:
2637 case USB_SPEED_HIGH:
2638 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2639 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2640 port->portsc |= PORTSC_PED;
2641 break;
2642 }
2643
2644 port->portsc &= ~PORTSC_PR;
2645 xhci_port_notify(port, PORTSC_PRC);
2646 }
2647
2648 static void xhci_reset(DeviceState *dev)
2649 {
2650 XHCIState *xhci = XHCI(dev);
2651 int i;
2652
2653 trace_usb_xhci_reset();
2654 if (!(xhci->usbsts & USBSTS_HCH)) {
2655 DPRINTF("xhci: reset while running!\n");
2656 }
2657
2658 xhci->usbcmd = 0;
2659 xhci->usbsts = USBSTS_HCH;
2660 xhci->dnctrl = 0;
2661 xhci->crcr_low = 0;
2662 xhci->crcr_high = 0;
2663 xhci->dcbaap_low = 0;
2664 xhci->dcbaap_high = 0;
2665 xhci->config = 0;
2666
2667 for (i = 0; i < xhci->numslots; i++) {
2668 xhci_disable_slot(xhci, i+1);
2669 }
2670
2671 for (i = 0; i < xhci->numports; i++) {
2672 xhci_port_update(xhci->ports + i, 0);
2673 }
2674
2675 for (i = 0; i < xhci->numintrs; i++) {
2676 xhci->intr[i].iman = 0;
2677 xhci->intr[i].imod = 0;
2678 xhci->intr[i].erstsz = 0;
2679 xhci->intr[i].erstba_low = 0;
2680 xhci->intr[i].erstba_high = 0;
2681 xhci->intr[i].erdp_low = 0;
2682 xhci->intr[i].erdp_high = 0;
2683
2684 xhci->intr[i].er_ep_idx = 0;
2685 xhci->intr[i].er_pcs = 1;
2686 xhci->intr[i].ev_buffer_put = 0;
2687 xhci->intr[i].ev_buffer_get = 0;
2688 }
2689
2690 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2691 xhci_mfwrap_update(xhci);
2692 }
2693
2694 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2695 {
2696 XHCIState *xhci = ptr;
2697 uint32_t ret;
2698
2699 switch (reg) {
2700 case 0x00: /* HCIVERSION, CAPLENGTH */
2701 ret = 0x01000000 | LEN_CAP;
2702 break;
2703 case 0x04: /* HCSPARAMS 1 */
2704 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2705 | (xhci->numintrs<<8) | xhci->numslots;
2706 break;
2707 case 0x08: /* HCSPARAMS 2 */
2708 ret = 0x0000000f;
2709 break;
2710 case 0x0c: /* HCSPARAMS 3 */
2711 ret = 0x00000000;
2712 break;
2713 case 0x10: /* HCCPARAMS */
2714 if (sizeof(dma_addr_t) == 4) {
2715 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2716 } else {
2717 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2718 }
2719 break;
2720 case 0x14: /* DBOFF */
2721 ret = OFF_DOORBELL;
2722 break;
2723 case 0x18: /* RTSOFF */
2724 ret = OFF_RUNTIME;
2725 break;
2726
2727 /* extended capabilities */
2728 case 0x20: /* Supported Protocol:00 */
2729 ret = 0x02000402; /* USB 2.0 */
2730 break;
2731 case 0x24: /* Supported Protocol:04 */
2732 ret = 0x20425355; /* "USB " */
2733 break;
2734 case 0x28: /* Supported Protocol:08 */
2735 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2736 ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
2737 } else {
2738 ret = (xhci->numports_2<<8) | 1;
2739 }
2740 break;
2741 case 0x2c: /* Supported Protocol:0c */
2742 ret = 0x00000000; /* reserved */
2743 break;
2744 case 0x30: /* Supported Protocol:00 */
2745 ret = 0x03000002; /* USB 3.0 */
2746 break;
2747 case 0x34: /* Supported Protocol:04 */
2748 ret = 0x20425355; /* "USB " */
2749 break;
2750 case 0x38: /* Supported Protocol:08 */
2751 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2752 ret = (xhci->numports_3<<8) | 1;
2753 } else {
2754 ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
2755 }
2756 break;
2757 case 0x3c: /* Supported Protocol:0c */
2758 ret = 0x00000000; /* reserved */
2759 break;
2760 default:
2761 trace_usb_xhci_unimplemented("cap read", reg);
2762 ret = 0;
2763 }
2764
2765 trace_usb_xhci_cap_read(reg, ret);
2766 return ret;
2767 }
2768
2769 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2770 {
2771 XHCIPort *port = ptr;
2772 uint32_t ret;
2773
2774 switch (reg) {
2775 case 0x00: /* PORTSC */
2776 ret = port->portsc;
2777 break;
2778 case 0x04: /* PORTPMSC */
2779 case 0x08: /* PORTLI */
2780 ret = 0;
2781 break;
2782 case 0x0c: /* reserved */
2783 default:
2784 trace_usb_xhci_unimplemented("port read", reg);
2785 ret = 0;
2786 }
2787
2788 trace_usb_xhci_port_read(port->portnr, reg, ret);
2789 return ret;
2790 }
2791
2792 static void xhci_port_write(void *ptr, hwaddr reg,
2793 uint64_t val, unsigned size)
2794 {
2795 XHCIPort *port = ptr;
2796 uint32_t portsc, notify;
2797
2798 trace_usb_xhci_port_write(port->portnr, reg, val);
2799
2800 switch (reg) {
2801 case 0x00: /* PORTSC */
2802 /* write-1-to-start bits */
2803 if (val & PORTSC_WPR) {
2804 xhci_port_reset(port, true);
2805 break;
2806 }
2807 if (val & PORTSC_PR) {
2808 xhci_port_reset(port, false);
2809 break;
2810 }
2811
2812 portsc = port->portsc;
2813 notify = 0;
2814 /* write-1-to-clear bits*/
2815 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2816 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2817 if (val & PORTSC_LWS) {
2818 /* overwrite PLS only when LWS=1 */
2819 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2820 uint32_t new_pls = get_field(val, PORTSC_PLS);
2821 switch (new_pls) {
2822 case PLS_U0:
2823 if (old_pls != PLS_U0) {
2824 set_field(&portsc, new_pls, PORTSC_PLS);
2825 trace_usb_xhci_port_link(port->portnr, new_pls);
2826 notify = PORTSC_PLC;
2827 }
2828 break;
2829 case PLS_U3:
2830 if (old_pls < PLS_U3) {
2831 set_field(&portsc, new_pls, PORTSC_PLS);
2832 trace_usb_xhci_port_link(port->portnr, new_pls);
2833 }
2834 break;
2835 case PLS_RESUME:
2836 /* windows does this for some reason, don't spam stderr */
2837 break;
2838 default:
2839 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2840 __func__, old_pls, new_pls);
2841 break;
2842 }
2843 }
2844 /* read/write bits */
2845 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2846 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2847 port->portsc = portsc;
2848 if (notify) {
2849 xhci_port_notify(port, notify);
2850 }
2851 break;
2852 case 0x04: /* PORTPMSC */
2853 case 0x08: /* PORTLI */
2854 default:
2855 trace_usb_xhci_unimplemented("port write", reg);
2856 }
2857 }
2858
2859 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
2860 {
2861 XHCIState *xhci = ptr;
2862 uint32_t ret;
2863
2864 switch (reg) {
2865 case 0x00: /* USBCMD */
2866 ret = xhci->usbcmd;
2867 break;
2868 case 0x04: /* USBSTS */
2869 ret = xhci->usbsts;
2870 break;
2871 case 0x08: /* PAGESIZE */
2872 ret = 1; /* 4KiB */
2873 break;
2874 case 0x14: /* DNCTRL */
2875 ret = xhci->dnctrl;
2876 break;
2877 case 0x18: /* CRCR low */
2878 ret = xhci->crcr_low & ~0xe;
2879 break;
2880 case 0x1c: /* CRCR high */
2881 ret = xhci->crcr_high;
2882 break;
2883 case 0x30: /* DCBAAP low */
2884 ret = xhci->dcbaap_low;
2885 break;
2886 case 0x34: /* DCBAAP high */
2887 ret = xhci->dcbaap_high;
2888 break;
2889 case 0x38: /* CONFIG */
2890 ret = xhci->config;
2891 break;
2892 default:
2893 trace_usb_xhci_unimplemented("oper read", reg);
2894 ret = 0;
2895 }
2896
2897 trace_usb_xhci_oper_read(reg, ret);
2898 return ret;
2899 }
2900
2901 static void xhci_oper_write(void *ptr, hwaddr reg,
2902 uint64_t val, unsigned size)
2903 {
2904 XHCIState *xhci = XHCI(ptr);
2905
2906 trace_usb_xhci_oper_write(reg, val);
2907
2908 switch (reg) {
2909 case 0x00: /* USBCMD */
2910 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2911 xhci_run(xhci);
2912 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2913 xhci_stop(xhci);
2914 }
2915 if (val & USBCMD_CSS) {
2916 /* save state */
2917 xhci->usbsts &= ~USBSTS_SRE;
2918 }
2919 if (val & USBCMD_CRS) {
2920 /* restore state */
2921 xhci->usbsts |= USBSTS_SRE;
2922 }
2923 xhci->usbcmd = val & 0xc0f;
2924 xhci_mfwrap_update(xhci);
2925 if (val & USBCMD_HCRST) {
2926 xhci_reset(DEVICE(xhci));
2927 }
2928 xhci_intr_update(xhci, 0);
2929 break;
2930
2931 case 0x04: /* USBSTS */
2932 /* these bits are write-1-to-clear */
2933 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2934 xhci_intr_update(xhci, 0);
2935 break;
2936
2937 case 0x14: /* DNCTRL */
2938 xhci->dnctrl = val & 0xffff;
2939 break;
2940 case 0x18: /* CRCR low */
2941 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2942 break;
2943 case 0x1c: /* CRCR high */
2944 xhci->crcr_high = val;
2945 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2946 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2947 xhci->crcr_low &= ~CRCR_CRR;
2948 xhci_event(xhci, &event, 0);
2949 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2950 } else {
2951 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2952 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2953 }
2954 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2955 break;
2956 case 0x30: /* DCBAAP low */
2957 xhci->dcbaap_low = val & 0xffffffc0;
2958 break;
2959 case 0x34: /* DCBAAP high */
2960 xhci->dcbaap_high = val;
2961 break;
2962 case 0x38: /* CONFIG */
2963 xhci->config = val & 0xff;
2964 break;
2965 default:
2966 trace_usb_xhci_unimplemented("oper write", reg);
2967 }
2968 }
2969
2970 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
2971 unsigned size)
2972 {
2973 XHCIState *xhci = ptr;
2974 uint32_t ret = 0;
2975
2976 if (reg < 0x20) {
2977 switch (reg) {
2978 case 0x00: /* MFINDEX */
2979 ret = xhci_mfindex_get(xhci) & 0x3fff;
2980 break;
2981 default:
2982 trace_usb_xhci_unimplemented("runtime read", reg);
2983 break;
2984 }
2985 } else {
2986 int v = (reg - 0x20) / 0x20;
2987 XHCIInterrupter *intr = &xhci->intr[v];
2988 switch (reg & 0x1f) {
2989 case 0x00: /* IMAN */
2990 ret = intr->iman;
2991 break;
2992 case 0x04: /* IMOD */
2993 ret = intr->imod;
2994 break;
2995 case 0x08: /* ERSTSZ */
2996 ret = intr->erstsz;
2997 break;
2998 case 0x10: /* ERSTBA low */
2999 ret = intr->erstba_low;
3000 break;
3001 case 0x14: /* ERSTBA high */
3002 ret = intr->erstba_high;
3003 break;
3004 case 0x18: /* ERDP low */
3005 ret = intr->erdp_low;
3006 break;
3007 case 0x1c: /* ERDP high */
3008 ret = intr->erdp_high;
3009 break;
3010 }
3011 }
3012
3013 trace_usb_xhci_runtime_read(reg, ret);
3014 return ret;
3015 }
3016
3017 static void xhci_runtime_write(void *ptr, hwaddr reg,
3018 uint64_t val, unsigned size)
3019 {
3020 XHCIState *xhci = ptr;
3021 XHCIInterrupter *intr;
3022 int v;
3023
3024 trace_usb_xhci_runtime_write(reg, val);
3025
3026 if (reg < 0x20) {
3027 trace_usb_xhci_unimplemented("runtime write", reg);
3028 return;
3029 }
3030 v = (reg - 0x20) / 0x20;
3031 intr = &xhci->intr[v];
3032
3033 switch (reg & 0x1f) {
3034 case 0x00: /* IMAN */
3035 if (val & IMAN_IP) {
3036 intr->iman &= ~IMAN_IP;
3037 }
3038 intr->iman &= ~IMAN_IE;
3039 intr->iman |= val & IMAN_IE;
3040 xhci_intr_update(xhci, v);
3041 break;
3042 case 0x04: /* IMOD */
3043 intr->imod = val;
3044 break;
3045 case 0x08: /* ERSTSZ */
3046 intr->erstsz = val & 0xffff;
3047 break;
3048 case 0x10: /* ERSTBA low */
3049 if (xhci->nec_quirks) {
3050 /* NEC driver bug: it doesn't align this to 64 bytes */
3051 intr->erstba_low = val & 0xfffffff0;
3052 } else {
3053 intr->erstba_low = val & 0xffffffc0;
3054 }
3055 break;
3056 case 0x14: /* ERSTBA high */
3057 intr->erstba_high = val;
3058 xhci_er_reset(xhci, v);
3059 break;
3060 case 0x18: /* ERDP low */
3061 if (val & ERDP_EHB) {
3062 intr->erdp_low &= ~ERDP_EHB;
3063 }
3064 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3065 if (val & ERDP_EHB) {
3066 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
3067 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE;
3068 if (erdp >= intr->er_start &&
3069 erdp < (intr->er_start + TRB_SIZE * intr->er_size) &&
3070 dp_idx != intr->er_ep_idx) {
3071 xhci_intr_raise(xhci, v);
3072 }
3073 }
3074 break;
3075 case 0x1c: /* ERDP high */
3076 intr->erdp_high = val;
3077 break;
3078 default:
3079 trace_usb_xhci_unimplemented("oper write", reg);
3080 }
3081 }
3082
3083 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3084 unsigned size)
3085 {
3086 /* doorbells always read as 0 */
3087 trace_usb_xhci_doorbell_read(reg, 0);
3088 return 0;
3089 }
3090
3091 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3092 uint64_t val, unsigned size)
3093 {
3094 XHCIState *xhci = ptr;
3095 unsigned int epid, streamid;
3096
3097 trace_usb_xhci_doorbell_write(reg, val);
3098
3099 if (!xhci_running(xhci)) {
3100 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3101 return;
3102 }
3103
3104 reg >>= 2;
3105
3106 if (reg == 0) {
3107 if (val == 0) {
3108 xhci_process_commands(xhci);
3109 } else {
3110 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3111 (uint32_t)val);
3112 }
3113 } else {
3114 epid = val & 0xff;
3115 streamid = (val >> 16) & 0xffff;
3116 if (reg > xhci->numslots) {
3117 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3118 } else if (epid == 0 || epid > 31) {
3119 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3120 (int)reg, (uint32_t)val);
3121 } else {
3122 xhci_kick_ep(xhci, reg, epid, streamid);
3123 }
3124 }
3125 }
3126
3127 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3128 unsigned width)
3129 {
3130 /* nothing */
3131 }
3132
3133 static const MemoryRegionOps xhci_cap_ops = {
3134 .read = xhci_cap_read,
3135 .write = xhci_cap_write,
3136 .valid.min_access_size = 1,
3137 .valid.max_access_size = 4,
3138 .impl.min_access_size = 4,
3139 .impl.max_access_size = 4,
3140 .endianness = DEVICE_LITTLE_ENDIAN,
3141 };
3142
3143 static const MemoryRegionOps xhci_oper_ops = {
3144 .read = xhci_oper_read,
3145 .write = xhci_oper_write,
3146 .valid.min_access_size = 4,
3147 .valid.max_access_size = sizeof(dma_addr_t),
3148 .endianness = DEVICE_LITTLE_ENDIAN,
3149 };
3150
3151 static const MemoryRegionOps xhci_port_ops = {
3152 .read = xhci_port_read,
3153 .write = xhci_port_write,
3154 .valid.min_access_size = 4,
3155 .valid.max_access_size = 4,
3156 .endianness = DEVICE_LITTLE_ENDIAN,
3157 };
3158
3159 static const MemoryRegionOps xhci_runtime_ops = {
3160 .read = xhci_runtime_read,
3161 .write = xhci_runtime_write,
3162 .valid.min_access_size = 4,
3163 .valid.max_access_size = sizeof(dma_addr_t),
3164 .endianness = DEVICE_LITTLE_ENDIAN,
3165 };
3166
3167 static const MemoryRegionOps xhci_doorbell_ops = {
3168 .read = xhci_doorbell_read,
3169 .write = xhci_doorbell_write,
3170 .valid.min_access_size = 4,
3171 .valid.max_access_size = 4,
3172 .endianness = DEVICE_LITTLE_ENDIAN,
3173 };
3174
3175 static void xhci_attach(USBPort *usbport)
3176 {
3177 XHCIState *xhci = usbport->opaque;
3178 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3179
3180 xhci_port_update(port, 0);
3181 }
3182
3183 static void xhci_detach(USBPort *usbport)
3184 {
3185 XHCIState *xhci = usbport->opaque;
3186 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3187
3188 xhci_detach_slot(xhci, usbport);
3189 xhci_port_update(port, 1);
3190 }
3191
3192 static void xhci_wakeup(USBPort *usbport)
3193 {
3194 XHCIState *xhci = usbport->opaque;
3195 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3196
3197 assert(port);
3198 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3199 return;
3200 }
3201 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3202 xhci_port_notify(port, PORTSC_PLC);
3203 }
3204
3205 static void xhci_complete(USBPort *port, USBPacket *packet)
3206 {
3207 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3208
3209 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3210 xhci_ep_nuke_one_xfer(xfer, 0);
3211 return;
3212 }
3213 xhci_try_complete_packet(xfer);
3214 xhci_kick_epctx(xfer->epctx, xfer->streamid);
3215 if (xfer->complete) {
3216 xhci_ep_free_xfer(xfer);
3217 }
3218 }
3219
3220 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3221 {
3222 USBBus *bus = usb_bus_from_device(child);
3223 XHCIState *xhci = container_of(bus, XHCIState, bus);
3224
3225 xhci_detach_slot(xhci, child->port);
3226 }
3227
3228 static USBPortOps xhci_uport_ops = {
3229 .attach = xhci_attach,
3230 .detach = xhci_detach,
3231 .wakeup = xhci_wakeup,
3232 .complete = xhci_complete,
3233 .child_detach = xhci_child_detach,
3234 };
3235
3236 static int xhci_find_epid(USBEndpoint *ep)
3237 {
3238 if (ep->nr == 0) {
3239 return 1;
3240 }
3241 if (ep->pid == USB_TOKEN_IN) {
3242 return ep->nr * 2 + 1;
3243 } else {
3244 return ep->nr * 2;
3245 }
3246 }
3247
3248 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx)
3249 {
3250 USBPort *uport;
3251 uint32_t token;
3252
3253 if (!epctx) {
3254 return NULL;
3255 }
3256 uport = epctx->xhci->slots[epctx->slotid - 1].uport;
3257 if (!uport || !uport->dev) {
3258 return NULL;
3259 }
3260 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT;
3261 return usb_ep_get(uport->dev, token, epctx->epid >> 1);
3262 }
3263
3264 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3265 unsigned int stream)
3266 {
3267 XHCIState *xhci = container_of(bus, XHCIState, bus);
3268 int slotid;
3269
3270 DPRINTF("%s\n", __func__);
3271 slotid = ep->dev->addr;
3272 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3273 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3274 return;
3275 }
3276 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3277 }
3278
3279 static USBBusOps xhci_bus_ops = {
3280 .wakeup_endpoint = xhci_wakeup_endpoint,
3281 };
3282
3283 static void usb_xhci_init(XHCIState *xhci)
3284 {
3285 XHCIPort *port;
3286 unsigned int i, usbports, speedmask;
3287
3288 xhci->usbsts = USBSTS_HCH;
3289
3290 if (xhci->numports_2 > XHCI_MAXPORTS_2) {
3291 xhci->numports_2 = XHCI_MAXPORTS_2;
3292 }
3293 if (xhci->numports_3 > XHCI_MAXPORTS_3) {
3294 xhci->numports_3 = XHCI_MAXPORTS_3;
3295 }
3296 usbports = MAX(xhci->numports_2, xhci->numports_3);
3297 xhci->numports = xhci->numports_2 + xhci->numports_3;
3298
3299 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque);
3300
3301 for (i = 0; i < usbports; i++) {
3302 speedmask = 0;
3303 if (i < xhci->numports_2) {
3304 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3305 port = &xhci->ports[i + xhci->numports_3];
3306 port->portnr = i + 1 + xhci->numports_3;
3307 } else {
3308 port = &xhci->ports[i];
3309 port->portnr = i + 1;
3310 }
3311 port->uport = &xhci->uports[i];
3312 port->speedmask =
3313 USB_SPEED_MASK_LOW |
3314 USB_SPEED_MASK_FULL |
3315 USB_SPEED_MASK_HIGH;
3316 assert(i < XHCI_MAXPORTS);
3317 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3318 speedmask |= port->speedmask;
3319 }
3320 if (i < xhci->numports_3) {
3321 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3322 port = &xhci->ports[i];
3323 port->portnr = i + 1;
3324 } else {
3325 port = &xhci->ports[i + xhci->numports_2];
3326 port->portnr = i + 1 + xhci->numports_2;
3327 }
3328 port->uport = &xhci->uports[i];
3329 port->speedmask = USB_SPEED_MASK_SUPER;
3330 assert(i < XHCI_MAXPORTS);
3331 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3332 speedmask |= port->speedmask;
3333 }
3334 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3335 &xhci_uport_ops, speedmask);
3336 }
3337 }
3338
3339 static void usb_xhci_realize(DeviceState *dev, Error **errp)
3340 {
3341 int i;
3342
3343 XHCIState *xhci = XHCI(dev);
3344
3345 if (xhci->numintrs > XHCI_MAXINTRS) {
3346 xhci->numintrs = XHCI_MAXINTRS;
3347 }
3348 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3349 xhci->numintrs++;
3350 }
3351 if (xhci->numintrs < 1) {
3352 xhci->numintrs = 1;
3353 }
3354 if (xhci->numslots > XHCI_MAXSLOTS) {
3355 xhci->numslots = XHCI_MAXSLOTS;
3356 }
3357 if (xhci->numslots < 1) {
3358 xhci->numslots = 1;
3359 }
3360 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3361 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3362 } else {
3363 xhci->max_pstreams_mask = 0;
3364 }
3365
3366 usb_xhci_init(xhci);
3367 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3368
3369 memory_region_init(&xhci->mem, OBJECT(dev), "xhci", XHCI_LEN_REGS);
3370 memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci,
3371 "capabilities", LEN_CAP);
3372 memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci,
3373 "operational", 0x400);
3374 memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops,
3375 xhci, "runtime", LEN_RUNTIME);
3376 memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops,
3377 xhci, "doorbell", LEN_DOORBELL);
3378
3379 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3380 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3381 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3382 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3383
3384 for (i = 0; i < xhci->numports; i++) {
3385 XHCIPort *port = &xhci->ports[i];
3386 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3387 port->xhci = xhci;
3388 memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port,
3389 port->name, 0x10);
3390 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3391 }
3392 }
3393
3394 static void usb_xhci_unrealize(DeviceState *dev)
3395 {
3396 int i;
3397 XHCIState *xhci = XHCI(dev);
3398
3399 trace_usb_xhci_exit();
3400
3401 for (i = 0; i < xhci->numslots; i++) {
3402 xhci_disable_slot(xhci, i + 1);
3403 }
3404
3405 if (xhci->mfwrap_timer) {
3406 timer_free(xhci->mfwrap_timer);
3407 xhci->mfwrap_timer = NULL;
3408 }
3409
3410 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3411 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3412 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3413 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3414
3415 for (i = 0; i < xhci->numports; i++) {
3416 XHCIPort *port = &xhci->ports[i];
3417 memory_region_del_subregion(&xhci->mem, &port->mem);
3418 }
3419
3420 usb_bus_release(&xhci->bus);
3421 }
3422
3423 static int usb_xhci_post_load(void *opaque, int version_id)
3424 {
3425 XHCIState *xhci = opaque;
3426 XHCISlot *slot;
3427 XHCIEPContext *epctx;
3428 dma_addr_t dcbaap, pctx;
3429 uint32_t slot_ctx[4];
3430 uint32_t ep_ctx[5];
3431 int slotid, epid, state;
3432 uint64_t addr;
3433
3434 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3435
3436 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3437 slot = &xhci->slots[slotid-1];
3438 if (!slot->addressed) {
3439 continue;
3440 }
3441 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &addr, MEMTXATTRS_UNSPECIFIED);
3442 slot->ctx = xhci_mask64(addr);
3443
3444 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3445 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3446 if (!slot->uport) {
3447 /* should not happen, but may trigger on guest bugs */
3448 slot->enabled = 0;
3449 slot->addressed = 0;
3450 continue;
3451 }
3452 assert(slot->uport && slot->uport->dev);
3453
3454 for (epid = 1; epid <= 31; epid++) {
3455 pctx = slot->ctx + 32 * epid;
3456 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3457 state = ep_ctx[0] & EP_STATE_MASK;
3458 if (state == EP_DISABLED) {
3459 continue;
3460 }
3461 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3462 slot->eps[epid-1] = epctx;
3463 xhci_init_epctx(epctx, pctx, ep_ctx);
3464 epctx->state = state;
3465 if (state == EP_RUNNING) {
3466 /* kick endpoint after vmload is finished */
3467 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3468 }
3469 }
3470 }
3471 return 0;
3472 }
3473
3474 static const VMStateDescription vmstate_xhci_ring = {
3475 .name = "xhci-ring",
3476 .version_id = 1,
3477 .fields = (VMStateField[]) {
3478 VMSTATE_UINT64(dequeue, XHCIRing),
3479 VMSTATE_BOOL(ccs, XHCIRing),
3480 VMSTATE_END_OF_LIST()
3481 }
3482 };
3483
3484 static const VMStateDescription vmstate_xhci_port = {
3485 .name = "xhci-port",
3486 .version_id = 1,
3487 .fields = (VMStateField[]) {
3488 VMSTATE_UINT32(portsc, XHCIPort),
3489 VMSTATE_END_OF_LIST()
3490 }
3491 };
3492
3493 static const VMStateDescription vmstate_xhci_slot = {
3494 .name = "xhci-slot",
3495 .version_id = 1,
3496 .fields = (VMStateField[]) {
3497 VMSTATE_BOOL(enabled, XHCISlot),
3498 VMSTATE_BOOL(addressed, XHCISlot),
3499 VMSTATE_END_OF_LIST()
3500 }
3501 };
3502
3503 static const VMStateDescription vmstate_xhci_event = {
3504 .name = "xhci-event",
3505 .version_id = 1,
3506 .fields = (VMStateField[]) {
3507 VMSTATE_UINT32(type, XHCIEvent),
3508 VMSTATE_UINT32(ccode, XHCIEvent),
3509 VMSTATE_UINT64(ptr, XHCIEvent),
3510 VMSTATE_UINT32(length, XHCIEvent),
3511 VMSTATE_UINT32(flags, XHCIEvent),
3512 VMSTATE_UINT8(slotid, XHCIEvent),
3513 VMSTATE_UINT8(epid, XHCIEvent),
3514 VMSTATE_END_OF_LIST()
3515 }
3516 };
3517
3518 static bool xhci_er_full(void *opaque, int version_id)
3519 {
3520 return false;
3521 }
3522
3523 static const VMStateDescription vmstate_xhci_intr = {
3524 .name = "xhci-intr",
3525 .version_id = 1,
3526 .fields = (VMStateField[]) {
3527 /* registers */
3528 VMSTATE_UINT32(iman, XHCIInterrupter),
3529 VMSTATE_UINT32(imod, XHCIInterrupter),
3530 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3531 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3532 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3533 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3534 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3535
3536 /* state */
3537 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3538 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3539 VMSTATE_UINT64(er_start, XHCIInterrupter),
3540 VMSTATE_UINT32(er_size, XHCIInterrupter),
3541 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3542
3543 /* event queue (used if ring is full) */
3544 VMSTATE_BOOL(er_full_unused, XHCIInterrupter),
3545 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3546 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3547 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3548 xhci_er_full, 1,
3549 vmstate_xhci_event, XHCIEvent),
3550
3551 VMSTATE_END_OF_LIST()
3552 }
3553 };
3554
3555 const VMStateDescription vmstate_xhci = {
3556 .name = "xhci-core",
3557 .version_id = 1,
3558 .post_load = usb_xhci_post_load,
3559 .fields = (VMStateField[]) {
3560 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3561 vmstate_xhci_port, XHCIPort),
3562 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3563 vmstate_xhci_slot, XHCISlot),
3564 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3565 vmstate_xhci_intr, XHCIInterrupter),
3566
3567 /* Operational Registers */
3568 VMSTATE_UINT32(usbcmd, XHCIState),
3569 VMSTATE_UINT32(usbsts, XHCIState),
3570 VMSTATE_UINT32(dnctrl, XHCIState),
3571 VMSTATE_UINT32(crcr_low, XHCIState),
3572 VMSTATE_UINT32(crcr_high, XHCIState),
3573 VMSTATE_UINT32(dcbaap_low, XHCIState),
3574 VMSTATE_UINT32(dcbaap_high, XHCIState),
3575 VMSTATE_UINT32(config, XHCIState),
3576
3577 /* Runtime Registers & state */
3578 VMSTATE_INT64(mfindex_start, XHCIState),
3579 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3580 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3581
3582 VMSTATE_END_OF_LIST()
3583 }
3584 };
3585
3586 static Property xhci_properties[] = {
3587 DEFINE_PROP_BIT("streams", XHCIState, flags,
3588 XHCI_FLAG_ENABLE_STREAMS, true),
3589 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3590 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3591 DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE,
3592 DeviceState *),
3593 DEFINE_PROP_END_OF_LIST(),
3594 };
3595
3596 static void xhci_class_init(ObjectClass *klass, void *data)
3597 {
3598 DeviceClass *dc = DEVICE_CLASS(klass);
3599
3600 dc->realize = usb_xhci_realize;
3601 dc->unrealize = usb_xhci_unrealize;
3602 dc->reset = xhci_reset;
3603 device_class_set_props(dc, xhci_properties);
3604 dc->user_creatable = false;
3605 }
3606
3607 static const TypeInfo xhci_info = {
3608 .name = TYPE_XHCI,
3609 .parent = TYPE_DEVICE,
3610 .instance_size = sizeof(XHCIState),
3611 .class_init = xhci_class_init,
3612 };
3613
3614 static void xhci_register_types(void)
3615 {
3616 type_register_static(&xhci_info);
3617 }
3618
3619 type_init(xhci_register_types)