xhci: set timer to retry xfers
[qemu.git] / hw / usb / hcd-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu/timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
27 #include "trace.h"
28
29 //#define DEBUG_XHCI
30 //#define DEBUG_DATA
31
32 #ifdef DEBUG_XHCI
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34 #else
35 #define DPRINTF(...) do {} while (0)
36 #endif
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
39
40 #define MAXPORTS_2 15
41 #define MAXPORTS_3 15
42
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
44 #define MAXSLOTS 64
45 #define MAXINTRS 16
46
47 #define TD_QUEUE 24
48
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53 #define ER_FULL_HACK
54
55 #define LEN_CAP 0x40
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
59
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
67
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
70 #endif
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
73 #endif
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
76 #endif
77
78 /* bit definitions */
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
88
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
98
99
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
129
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
134
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
137
138 #define ERDP_EHB (1<<3)
139
140 #define TRB_SIZE 16
141 typedef struct XHCITRB {
142 uint64_t parameter;
143 uint32_t status;
144 uint32_t control;
145 dma_addr_t addr;
146 bool ccs;
147 } XHCITRB;
148
149 enum {
150 PLS_U0 = 0,
151 PLS_U1 = 1,
152 PLS_U2 = 2,
153 PLS_U3 = 3,
154 PLS_DISABLED = 4,
155 PLS_RX_DETECT = 5,
156 PLS_INACTIVE = 6,
157 PLS_POLLING = 7,
158 PLS_RECOVERY = 8,
159 PLS_HOT_RESET = 9,
160 PLS_COMPILANCE_MODE = 10,
161 PLS_TEST_MODE = 11,
162 PLS_RESUME = 15,
163 };
164
165 typedef enum TRBType {
166 TRB_RESERVED = 0,
167 TR_NORMAL,
168 TR_SETUP,
169 TR_DATA,
170 TR_STATUS,
171 TR_ISOCH,
172 TR_LINK,
173 TR_EVDATA,
174 TR_NOOP,
175 CR_ENABLE_SLOT,
176 CR_DISABLE_SLOT,
177 CR_ADDRESS_DEVICE,
178 CR_CONFIGURE_ENDPOINT,
179 CR_EVALUATE_CONTEXT,
180 CR_RESET_ENDPOINT,
181 CR_STOP_ENDPOINT,
182 CR_SET_TR_DEQUEUE,
183 CR_RESET_DEVICE,
184 CR_FORCE_EVENT,
185 CR_NEGOTIATE_BW,
186 CR_SET_LATENCY_TOLERANCE,
187 CR_GET_PORT_BANDWIDTH,
188 CR_FORCE_HEADER,
189 CR_NOOP,
190 ER_TRANSFER = 32,
191 ER_COMMAND_COMPLETE,
192 ER_PORT_STATUS_CHANGE,
193 ER_BANDWIDTH_REQUEST,
194 ER_DOORBELL,
195 ER_HOST_CONTROLLER,
196 ER_DEVICE_NOTIFICATION,
197 ER_MFINDEX_WRAP,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
202 } TRBType;
203
204 #define CR_LINK TR_LINK
205
206 typedef enum TRBCCode {
207 CC_INVALID = 0,
208 CC_SUCCESS,
209 CC_DATA_BUFFER_ERROR,
210 CC_BABBLE_DETECTED,
211 CC_USB_TRANSACTION_ERROR,
212 CC_TRB_ERROR,
213 CC_STALL_ERROR,
214 CC_RESOURCE_ERROR,
215 CC_BANDWIDTH_ERROR,
216 CC_NO_SLOTS_ERROR,
217 CC_INVALID_STREAM_TYPE_ERROR,
218 CC_SLOT_NOT_ENABLED_ERROR,
219 CC_EP_NOT_ENABLED_ERROR,
220 CC_SHORT_PACKET,
221 CC_RING_UNDERRUN,
222 CC_RING_OVERRUN,
223 CC_VF_ER_FULL,
224 CC_PARAMETER_ERROR,
225 CC_BANDWIDTH_OVERRUN,
226 CC_CONTEXT_STATE_ERROR,
227 CC_NO_PING_RESPONSE_ERROR,
228 CC_EVENT_RING_FULL_ERROR,
229 CC_INCOMPATIBLE_DEVICE_ERROR,
230 CC_MISSED_SERVICE_ERROR,
231 CC_COMMAND_RING_STOPPED,
232 CC_COMMAND_ABORTED,
233 CC_STOPPED,
234 CC_STOPPED_LENGTH_INVALID,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
236 CC_ISOCH_BUFFER_OVERRUN = 31,
237 CC_EVENT_LOST_ERROR,
238 CC_UNDEFINED_ERROR,
239 CC_INVALID_STREAM_ID_ERROR,
240 CC_SECONDARY_BANDWIDTH_ERROR,
241 CC_SPLIT_TRANSACTION_ERROR
242 } TRBCCode;
243
244 #define TRB_C (1<<0)
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
248
249 #define TRB_EV_ED (1<<2)
250
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
265
266 #define TRB_TR_DIR (1<<16)
267
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
272
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
275
276 #define TRB_LK_TC (1<<1)
277
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
281
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
284
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
291
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
299
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
302
303 typedef struct XHCIState XHCIState;
304 typedef struct XHCIStreamContext XHCIStreamContext;
305 typedef struct XHCIEPContext XHCIEPContext;
306
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
309
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
314 *data = val; \
315 } while (0)
316
317 typedef enum EPType {
318 ET_INVALID = 0,
319 ET_ISO_OUT,
320 ET_BULK_OUT,
321 ET_INTR_OUT,
322 ET_CONTROL,
323 ET_ISO_IN,
324 ET_BULK_IN,
325 ET_INTR_IN,
326 } EPType;
327
328 typedef struct XHCIRing {
329 dma_addr_t dequeue;
330 bool ccs;
331 } XHCIRing;
332
333 typedef struct XHCIPort {
334 XHCIState *xhci;
335 uint32_t portsc;
336 uint32_t portnr;
337 USBPort *uport;
338 uint32_t speedmask;
339 char name[16];
340 MemoryRegion mem;
341 } XHCIPort;
342
343 typedef struct XHCITransfer {
344 XHCIState *xhci;
345 USBPacket packet;
346 QEMUSGList sgl;
347 bool running_async;
348 bool running_retry;
349 bool complete;
350 bool int_req;
351 unsigned int iso_pkts;
352 unsigned int slotid;
353 unsigned int epid;
354 unsigned int streamid;
355 bool in_xfer;
356 bool iso_xfer;
357 bool timed_xfer;
358
359 unsigned int trb_count;
360 unsigned int trb_alloced;
361 XHCITRB *trbs;
362
363 TRBCCode status;
364
365 unsigned int pkts;
366 unsigned int pktsize;
367 unsigned int cur_pkt;
368
369 uint64_t mfindex_kick;
370 } XHCITransfer;
371
372 struct XHCIStreamContext {
373 dma_addr_t pctx;
374 unsigned int sct;
375 XHCIRing ring;
376 };
377
378 struct XHCIEPContext {
379 XHCIState *xhci;
380 unsigned int slotid;
381 unsigned int epid;
382
383 XHCIRing ring;
384 unsigned int next_xfer;
385 unsigned int comp_xfer;
386 XHCITransfer transfers[TD_QUEUE];
387 XHCITransfer *retry;
388 EPType type;
389 dma_addr_t pctx;
390 unsigned int max_psize;
391 uint32_t state;
392
393 /* streams */
394 unsigned int max_pstreams;
395 bool lsa;
396 unsigned int nr_pstreams;
397 XHCIStreamContext *pstreams;
398
399 /* iso xfer scheduling */
400 unsigned int interval;
401 int64_t mfindex_last;
402 QEMUTimer *kick_timer;
403 };
404
405 typedef struct XHCISlot {
406 bool enabled;
407 bool addressed;
408 dma_addr_t ctx;
409 USBPort *uport;
410 XHCIEPContext * eps[31];
411 } XHCISlot;
412
413 typedef struct XHCIEvent {
414 TRBType type;
415 TRBCCode ccode;
416 uint64_t ptr;
417 uint32_t length;
418 uint32_t flags;
419 uint8_t slotid;
420 uint8_t epid;
421 } XHCIEvent;
422
423 typedef struct XHCIInterrupter {
424 uint32_t iman;
425 uint32_t imod;
426 uint32_t erstsz;
427 uint32_t erstba_low;
428 uint32_t erstba_high;
429 uint32_t erdp_low;
430 uint32_t erdp_high;
431
432 bool msix_used, er_pcs, er_full;
433
434 dma_addr_t er_start;
435 uint32_t er_size;
436 unsigned int er_ep_idx;
437
438 XHCIEvent ev_buffer[EV_QUEUE];
439 unsigned int ev_buffer_put;
440 unsigned int ev_buffer_get;
441
442 } XHCIInterrupter;
443
444 struct XHCIState {
445 /*< private >*/
446 PCIDevice parent_obj;
447 /*< public >*/
448
449 USBBus bus;
450 MemoryRegion mem;
451 MemoryRegion mem_cap;
452 MemoryRegion mem_oper;
453 MemoryRegion mem_runtime;
454 MemoryRegion mem_doorbell;
455
456 /* properties */
457 uint32_t numports_2;
458 uint32_t numports_3;
459 uint32_t numintrs;
460 uint32_t numslots;
461 uint32_t flags;
462 uint32_t max_pstreams_mask;
463
464 /* Operational Registers */
465 uint32_t usbcmd;
466 uint32_t usbsts;
467 uint32_t dnctrl;
468 uint32_t crcr_low;
469 uint32_t crcr_high;
470 uint32_t dcbaap_low;
471 uint32_t dcbaap_high;
472 uint32_t config;
473
474 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
475 XHCIPort ports[MAXPORTS];
476 XHCISlot slots[MAXSLOTS];
477 uint32_t numports;
478
479 /* Runtime Registers */
480 int64_t mfindex_start;
481 QEMUTimer *mfwrap_timer;
482 XHCIInterrupter intr[MAXINTRS];
483
484 XHCIRing cmd_ring;
485 };
486
487 #define TYPE_XHCI "nec-usb-xhci"
488
489 #define XHCI(obj) \
490 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
491
492 typedef struct XHCIEvRingSeg {
493 uint32_t addr_low;
494 uint32_t addr_high;
495 uint32_t size;
496 uint32_t rsvd;
497 } XHCIEvRingSeg;
498
499 enum xhci_flags {
500 XHCI_FLAG_USE_MSI = 1,
501 XHCI_FLAG_USE_MSI_X,
502 XHCI_FLAG_SS_FIRST,
503 XHCI_FLAG_FORCE_PCIE_ENDCAP,
504 XHCI_FLAG_ENABLE_STREAMS,
505 };
506
507 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
508 unsigned int epid, unsigned int streamid);
509 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
510 unsigned int epid);
511 static void xhci_xfer_report(XHCITransfer *xfer);
512 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
513 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
514 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
515 unsigned int slotid, unsigned int epid);
516
517 static const char *TRBType_names[] = {
518 [TRB_RESERVED] = "TRB_RESERVED",
519 [TR_NORMAL] = "TR_NORMAL",
520 [TR_SETUP] = "TR_SETUP",
521 [TR_DATA] = "TR_DATA",
522 [TR_STATUS] = "TR_STATUS",
523 [TR_ISOCH] = "TR_ISOCH",
524 [TR_LINK] = "TR_LINK",
525 [TR_EVDATA] = "TR_EVDATA",
526 [TR_NOOP] = "TR_NOOP",
527 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
528 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
529 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
530 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
531 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
532 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
533 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
534 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
535 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
536 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
537 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
538 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
539 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
540 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
541 [CR_NOOP] = "CR_NOOP",
542 [ER_TRANSFER] = "ER_TRANSFER",
543 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
544 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
545 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
546 [ER_DOORBELL] = "ER_DOORBELL",
547 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
548 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
549 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
550 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
551 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
552 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
553 };
554
555 static const char *TRBCCode_names[] = {
556 [CC_INVALID] = "CC_INVALID",
557 [CC_SUCCESS] = "CC_SUCCESS",
558 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
559 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
560 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
561 [CC_TRB_ERROR] = "CC_TRB_ERROR",
562 [CC_STALL_ERROR] = "CC_STALL_ERROR",
563 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
564 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
565 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
566 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
567 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
568 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
569 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
570 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
571 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
572 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
573 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
574 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
575 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
576 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
577 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
578 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
579 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
580 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
581 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
582 [CC_STOPPED] = "CC_STOPPED",
583 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
584 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
585 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
586 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
587 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
588 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
589 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
590 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
591 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
592 };
593
594 static const char *ep_state_names[] = {
595 [EP_DISABLED] = "disabled",
596 [EP_RUNNING] = "running",
597 [EP_HALTED] = "halted",
598 [EP_STOPPED] = "stopped",
599 [EP_ERROR] = "error",
600 };
601
602 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
603 {
604 if (index >= llen || list[index] == NULL) {
605 return "???";
606 }
607 return list[index];
608 }
609
610 static const char *trb_name(XHCITRB *trb)
611 {
612 return lookup_name(TRB_TYPE(*trb), TRBType_names,
613 ARRAY_SIZE(TRBType_names));
614 }
615
616 static const char *event_name(XHCIEvent *event)
617 {
618 return lookup_name(event->ccode, TRBCCode_names,
619 ARRAY_SIZE(TRBCCode_names));
620 }
621
622 static const char *ep_state_name(uint32_t state)
623 {
624 return lookup_name(state, ep_state_names,
625 ARRAY_SIZE(ep_state_names));
626 }
627
628 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
629 {
630 return xhci->flags & (1 << bit);
631 }
632
633 static uint64_t xhci_mfindex_get(XHCIState *xhci)
634 {
635 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
636 return (now - xhci->mfindex_start) / 125000;
637 }
638
639 static void xhci_mfwrap_update(XHCIState *xhci)
640 {
641 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
642 uint32_t mfindex, left;
643 int64_t now;
644
645 if ((xhci->usbcmd & bits) == bits) {
646 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
647 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
648 left = 0x4000 - mfindex;
649 timer_mod(xhci->mfwrap_timer, now + left * 125000);
650 } else {
651 timer_del(xhci->mfwrap_timer);
652 }
653 }
654
655 static void xhci_mfwrap_timer(void *opaque)
656 {
657 XHCIState *xhci = opaque;
658 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
659
660 xhci_event(xhci, &wrap, 0);
661 xhci_mfwrap_update(xhci);
662 }
663
664 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
665 {
666 if (sizeof(dma_addr_t) == 4) {
667 return low;
668 } else {
669 return low | (((dma_addr_t)high << 16) << 16);
670 }
671 }
672
673 static inline dma_addr_t xhci_mask64(uint64_t addr)
674 {
675 if (sizeof(dma_addr_t) == 4) {
676 return addr & 0xffffffff;
677 } else {
678 return addr;
679 }
680 }
681
682 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
683 uint32_t *buf, size_t len)
684 {
685 int i;
686
687 assert((len % sizeof(uint32_t)) == 0);
688
689 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
690
691 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
692 buf[i] = le32_to_cpu(buf[i]);
693 }
694 }
695
696 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
697 uint32_t *buf, size_t len)
698 {
699 int i;
700 uint32_t tmp[len / sizeof(uint32_t)];
701
702 assert((len % sizeof(uint32_t)) == 0);
703
704 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
705 tmp[i] = cpu_to_le32(buf[i]);
706 }
707 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
708 }
709
710 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
711 {
712 int index;
713
714 if (!uport->dev) {
715 return NULL;
716 }
717 switch (uport->dev->speed) {
718 case USB_SPEED_LOW:
719 case USB_SPEED_FULL:
720 case USB_SPEED_HIGH:
721 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
722 index = uport->index + xhci->numports_3;
723 } else {
724 index = uport->index;
725 }
726 break;
727 case USB_SPEED_SUPER:
728 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
729 index = uport->index;
730 } else {
731 index = uport->index + xhci->numports_2;
732 }
733 break;
734 default:
735 return NULL;
736 }
737 return &xhci->ports[index];
738 }
739
740 static void xhci_intx_update(XHCIState *xhci)
741 {
742 PCIDevice *pci_dev = PCI_DEVICE(xhci);
743 int level = 0;
744
745 if (msix_enabled(pci_dev) ||
746 msi_enabled(pci_dev)) {
747 return;
748 }
749
750 if (xhci->intr[0].iman & IMAN_IP &&
751 xhci->intr[0].iman & IMAN_IE &&
752 xhci->usbcmd & USBCMD_INTE) {
753 level = 1;
754 }
755
756 trace_usb_xhci_irq_intx(level);
757 pci_set_irq(pci_dev, level);
758 }
759
760 static void xhci_msix_update(XHCIState *xhci, int v)
761 {
762 PCIDevice *pci_dev = PCI_DEVICE(xhci);
763 bool enabled;
764
765 if (!msix_enabled(pci_dev)) {
766 return;
767 }
768
769 enabled = xhci->intr[v].iman & IMAN_IE;
770 if (enabled == xhci->intr[v].msix_used) {
771 return;
772 }
773
774 if (enabled) {
775 trace_usb_xhci_irq_msix_use(v);
776 msix_vector_use(pci_dev, v);
777 xhci->intr[v].msix_used = true;
778 } else {
779 trace_usb_xhci_irq_msix_unuse(v);
780 msix_vector_unuse(pci_dev, v);
781 xhci->intr[v].msix_used = false;
782 }
783 }
784
785 static void xhci_intr_raise(XHCIState *xhci, int v)
786 {
787 PCIDevice *pci_dev = PCI_DEVICE(xhci);
788
789 xhci->intr[v].erdp_low |= ERDP_EHB;
790 xhci->intr[v].iman |= IMAN_IP;
791 xhci->usbsts |= USBSTS_EINT;
792
793 if (!(xhci->intr[v].iman & IMAN_IE)) {
794 return;
795 }
796
797 if (!(xhci->usbcmd & USBCMD_INTE)) {
798 return;
799 }
800
801 if (msix_enabled(pci_dev)) {
802 trace_usb_xhci_irq_msix(v);
803 msix_notify(pci_dev, v);
804 return;
805 }
806
807 if (msi_enabled(pci_dev)) {
808 trace_usb_xhci_irq_msi(v);
809 msi_notify(pci_dev, v);
810 return;
811 }
812
813 if (v == 0) {
814 trace_usb_xhci_irq_intx(1);
815 pci_irq_assert(pci_dev);
816 }
817 }
818
819 static inline int xhci_running(XHCIState *xhci)
820 {
821 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
822 }
823
824 static void xhci_die(XHCIState *xhci)
825 {
826 xhci->usbsts |= USBSTS_HCE;
827 DPRINTF("xhci: asserted controller error\n");
828 }
829
830 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
831 {
832 PCIDevice *pci_dev = PCI_DEVICE(xhci);
833 XHCIInterrupter *intr = &xhci->intr[v];
834 XHCITRB ev_trb;
835 dma_addr_t addr;
836
837 ev_trb.parameter = cpu_to_le64(event->ptr);
838 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
839 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
840 event->flags | (event->type << TRB_TYPE_SHIFT);
841 if (intr->er_pcs) {
842 ev_trb.control |= TRB_C;
843 }
844 ev_trb.control = cpu_to_le32(ev_trb.control);
845
846 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
847 event_name(event), ev_trb.parameter,
848 ev_trb.status, ev_trb.control);
849
850 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
851 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
852
853 intr->er_ep_idx++;
854 if (intr->er_ep_idx >= intr->er_size) {
855 intr->er_ep_idx = 0;
856 intr->er_pcs = !intr->er_pcs;
857 }
858 }
859
860 static void xhci_events_update(XHCIState *xhci, int v)
861 {
862 XHCIInterrupter *intr = &xhci->intr[v];
863 dma_addr_t erdp;
864 unsigned int dp_idx;
865 bool do_irq = 0;
866
867 if (xhci->usbsts & USBSTS_HCH) {
868 return;
869 }
870
871 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
872 if (erdp < intr->er_start ||
873 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
874 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
875 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
876 v, intr->er_start, intr->er_size);
877 xhci_die(xhci);
878 return;
879 }
880 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
881 assert(dp_idx < intr->er_size);
882
883 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
884 * deadlocks when the ER is full. Hack it by holding off events until
885 * the driver decides to free at least half of the ring */
886 if (intr->er_full) {
887 int er_free = dp_idx - intr->er_ep_idx;
888 if (er_free <= 0) {
889 er_free += intr->er_size;
890 }
891 if (er_free < (intr->er_size/2)) {
892 DPRINTF("xhci_events_update(): event ring still "
893 "more than half full (hack)\n");
894 return;
895 }
896 }
897
898 while (intr->ev_buffer_put != intr->ev_buffer_get) {
899 assert(intr->er_full);
900 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
901 DPRINTF("xhci_events_update(): event ring full again\n");
902 #ifndef ER_FULL_HACK
903 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
904 xhci_write_event(xhci, &full, v);
905 #endif
906 do_irq = 1;
907 break;
908 }
909 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
910 xhci_write_event(xhci, event, v);
911 intr->ev_buffer_get++;
912 do_irq = 1;
913 if (intr->ev_buffer_get == EV_QUEUE) {
914 intr->ev_buffer_get = 0;
915 }
916 }
917
918 if (do_irq) {
919 xhci_intr_raise(xhci, v);
920 }
921
922 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
923 DPRINTF("xhci_events_update(): event ring no longer full\n");
924 intr->er_full = 0;
925 }
926 }
927
928 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
929 {
930 XHCIInterrupter *intr;
931 dma_addr_t erdp;
932 unsigned int dp_idx;
933
934 if (v >= xhci->numintrs) {
935 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
936 return;
937 }
938 intr = &xhci->intr[v];
939
940 if (intr->er_full) {
941 DPRINTF("xhci_event(): ER full, queueing\n");
942 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
943 DPRINTF("xhci: event queue full, dropping event!\n");
944 return;
945 }
946 intr->ev_buffer[intr->ev_buffer_put++] = *event;
947 if (intr->ev_buffer_put == EV_QUEUE) {
948 intr->ev_buffer_put = 0;
949 }
950 return;
951 }
952
953 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
954 if (erdp < intr->er_start ||
955 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
956 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
957 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
958 v, intr->er_start, intr->er_size);
959 xhci_die(xhci);
960 return;
961 }
962
963 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
964 assert(dp_idx < intr->er_size);
965
966 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
967 DPRINTF("xhci_event(): ER full, queueing\n");
968 #ifndef ER_FULL_HACK
969 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
970 xhci_write_event(xhci, &full);
971 #endif
972 intr->er_full = 1;
973 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
974 DPRINTF("xhci: event queue full, dropping event!\n");
975 return;
976 }
977 intr->ev_buffer[intr->ev_buffer_put++] = *event;
978 if (intr->ev_buffer_put == EV_QUEUE) {
979 intr->ev_buffer_put = 0;
980 }
981 } else {
982 xhci_write_event(xhci, event, v);
983 }
984
985 xhci_intr_raise(xhci, v);
986 }
987
988 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
989 dma_addr_t base)
990 {
991 ring->dequeue = base;
992 ring->ccs = 1;
993 }
994
995 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
996 dma_addr_t *addr)
997 {
998 PCIDevice *pci_dev = PCI_DEVICE(xhci);
999
1000 while (1) {
1001 TRBType type;
1002 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
1003 trb->addr = ring->dequeue;
1004 trb->ccs = ring->ccs;
1005 le64_to_cpus(&trb->parameter);
1006 le32_to_cpus(&trb->status);
1007 le32_to_cpus(&trb->control);
1008
1009 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
1010 trb->parameter, trb->status, trb->control);
1011
1012 if ((trb->control & TRB_C) != ring->ccs) {
1013 return 0;
1014 }
1015
1016 type = TRB_TYPE(*trb);
1017
1018 if (type != TR_LINK) {
1019 if (addr) {
1020 *addr = ring->dequeue;
1021 }
1022 ring->dequeue += TRB_SIZE;
1023 return type;
1024 } else {
1025 ring->dequeue = xhci_mask64(trb->parameter);
1026 if (trb->control & TRB_LK_TC) {
1027 ring->ccs = !ring->ccs;
1028 }
1029 }
1030 }
1031 }
1032
1033 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1034 {
1035 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1036 XHCITRB trb;
1037 int length = 0;
1038 dma_addr_t dequeue = ring->dequeue;
1039 bool ccs = ring->ccs;
1040 /* hack to bundle together the two/three TDs that make a setup transfer */
1041 bool control_td_set = 0;
1042
1043 while (1) {
1044 TRBType type;
1045 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
1046 le64_to_cpus(&trb.parameter);
1047 le32_to_cpus(&trb.status);
1048 le32_to_cpus(&trb.control);
1049
1050 if ((trb.control & TRB_C) != ccs) {
1051 return -length;
1052 }
1053
1054 type = TRB_TYPE(trb);
1055
1056 if (type == TR_LINK) {
1057 dequeue = xhci_mask64(trb.parameter);
1058 if (trb.control & TRB_LK_TC) {
1059 ccs = !ccs;
1060 }
1061 continue;
1062 }
1063
1064 length += 1;
1065 dequeue += TRB_SIZE;
1066
1067 if (type == TR_SETUP) {
1068 control_td_set = 1;
1069 } else if (type == TR_STATUS) {
1070 control_td_set = 0;
1071 }
1072
1073 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1074 return length;
1075 }
1076 }
1077 }
1078
1079 static void xhci_er_reset(XHCIState *xhci, int v)
1080 {
1081 XHCIInterrupter *intr = &xhci->intr[v];
1082 XHCIEvRingSeg seg;
1083
1084 if (intr->erstsz == 0) {
1085 /* disabled */
1086 intr->er_start = 0;
1087 intr->er_size = 0;
1088 return;
1089 }
1090 /* cache the (sole) event ring segment location */
1091 if (intr->erstsz != 1) {
1092 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1093 xhci_die(xhci);
1094 return;
1095 }
1096 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1097 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
1098 le32_to_cpus(&seg.addr_low);
1099 le32_to_cpus(&seg.addr_high);
1100 le32_to_cpus(&seg.size);
1101 if (seg.size < 16 || seg.size > 4096) {
1102 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
1103 xhci_die(xhci);
1104 return;
1105 }
1106 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1107 intr->er_size = seg.size;
1108
1109 intr->er_ep_idx = 0;
1110 intr->er_pcs = 1;
1111 intr->er_full = 0;
1112
1113 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1114 v, intr->er_start, intr->er_size);
1115 }
1116
1117 static void xhci_run(XHCIState *xhci)
1118 {
1119 trace_usb_xhci_run();
1120 xhci->usbsts &= ~USBSTS_HCH;
1121 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1122 }
1123
1124 static void xhci_stop(XHCIState *xhci)
1125 {
1126 trace_usb_xhci_stop();
1127 xhci->usbsts |= USBSTS_HCH;
1128 xhci->crcr_low &= ~CRCR_CRR;
1129 }
1130
1131 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1132 dma_addr_t base)
1133 {
1134 XHCIStreamContext *stctx;
1135 unsigned int i;
1136
1137 stctx = g_new0(XHCIStreamContext, count);
1138 for (i = 0; i < count; i++) {
1139 stctx[i].pctx = base + i * 16;
1140 stctx[i].sct = -1;
1141 }
1142 return stctx;
1143 }
1144
1145 static void xhci_reset_streams(XHCIEPContext *epctx)
1146 {
1147 unsigned int i;
1148
1149 for (i = 0; i < epctx->nr_pstreams; i++) {
1150 epctx->pstreams[i].sct = -1;
1151 }
1152 }
1153
1154 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1155 {
1156 assert(epctx->pstreams == NULL);
1157 epctx->nr_pstreams = 2 << epctx->max_pstreams;
1158 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1159 }
1160
1161 static void xhci_free_streams(XHCIEPContext *epctx)
1162 {
1163 assert(epctx->pstreams != NULL);
1164
1165 g_free(epctx->pstreams);
1166 epctx->pstreams = NULL;
1167 epctx->nr_pstreams = 0;
1168 }
1169
1170 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
1171 unsigned int slotid,
1172 uint32_t epmask,
1173 XHCIEPContext **epctxs,
1174 USBEndpoint **eps)
1175 {
1176 XHCISlot *slot;
1177 XHCIEPContext *epctx;
1178 USBEndpoint *ep;
1179 int i, j;
1180
1181 assert(slotid >= 1 && slotid <= xhci->numslots);
1182
1183 slot = &xhci->slots[slotid - 1];
1184
1185 for (i = 2, j = 0; i <= 31; i++) {
1186 if (!(epmask & (1u << i))) {
1187 continue;
1188 }
1189
1190 epctx = slot->eps[i - 1];
1191 ep = xhci_epid_to_usbep(xhci, slotid, i);
1192 if (!epctx || !epctx->nr_pstreams || !ep) {
1193 continue;
1194 }
1195
1196 if (epctxs) {
1197 epctxs[j] = epctx;
1198 }
1199 eps[j++] = ep;
1200 }
1201 return j;
1202 }
1203
1204 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
1205 uint32_t epmask)
1206 {
1207 USBEndpoint *eps[30];
1208 int nr_eps;
1209
1210 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
1211 if (nr_eps) {
1212 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
1213 }
1214 }
1215
1216 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
1217 uint32_t epmask)
1218 {
1219 XHCIEPContext *epctxs[30];
1220 USBEndpoint *eps[30];
1221 int i, r, nr_eps, req_nr_streams, dev_max_streams;
1222
1223 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
1224 eps);
1225 if (nr_eps == 0) {
1226 return CC_SUCCESS;
1227 }
1228
1229 req_nr_streams = epctxs[0]->nr_pstreams;
1230 dev_max_streams = eps[0]->max_streams;
1231
1232 for (i = 1; i < nr_eps; i++) {
1233 /*
1234 * HdG: I don't expect these to ever trigger, but if they do we need
1235 * to come up with another solution, ie group identical endpoints
1236 * together and make an usb_device_alloc_streams call per group.
1237 */
1238 if (epctxs[i]->nr_pstreams != req_nr_streams) {
1239 FIXME("guest streams config not identical for all eps");
1240 return CC_RESOURCE_ERROR;
1241 }
1242 if (eps[i]->max_streams != dev_max_streams) {
1243 FIXME("device streams config not identical for all eps");
1244 return CC_RESOURCE_ERROR;
1245 }
1246 }
1247
1248 /*
1249 * max-streams in both the device descriptor and in the controller is a
1250 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1251 * streams the guest will ask for 5 rounded up to the next power of 2 which
1252 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1253 *
1254 * For redirected devices however this is an issue, as there we must ask
1255 * the real xhci controller to alloc streams, and the host driver for the
1256 * real xhci controller will likely disallow allocating more streams then
1257 * the device can handle.
1258 *
1259 * So we limit the requested nr_streams to the maximum number the device
1260 * can handle.
1261 */
1262 if (req_nr_streams > dev_max_streams) {
1263 req_nr_streams = dev_max_streams;
1264 }
1265
1266 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
1267 if (r != 0) {
1268 DPRINTF("xhci: alloc streams failed\n");
1269 return CC_RESOURCE_ERROR;
1270 }
1271
1272 return CC_SUCCESS;
1273 }
1274
1275 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1276 unsigned int streamid,
1277 uint32_t *cc_error)
1278 {
1279 XHCIStreamContext *sctx;
1280 dma_addr_t base;
1281 uint32_t ctx[2], sct;
1282
1283 assert(streamid != 0);
1284 if (epctx->lsa) {
1285 if (streamid >= epctx->nr_pstreams) {
1286 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1287 return NULL;
1288 }
1289 sctx = epctx->pstreams + streamid;
1290 } else {
1291 FIXME("secondary streams not implemented yet");
1292 }
1293
1294 if (sctx->sct == -1) {
1295 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1296 sct = (ctx[0] >> 1) & 0x07;
1297 if (epctx->lsa && sct != 1) {
1298 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1299 return NULL;
1300 }
1301 sctx->sct = sct;
1302 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1303 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1304 }
1305 return sctx;
1306 }
1307
1308 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1309 XHCIStreamContext *sctx, uint32_t state)
1310 {
1311 XHCIRing *ring = NULL;
1312 uint32_t ctx[5];
1313 uint32_t ctx2[2];
1314
1315 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1316 ctx[0] &= ~EP_STATE_MASK;
1317 ctx[0] |= state;
1318
1319 /* update ring dequeue ptr */
1320 if (epctx->nr_pstreams) {
1321 if (sctx != NULL) {
1322 ring = &sctx->ring;
1323 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1324 ctx2[0] &= 0xe;
1325 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1326 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1327 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1328 }
1329 } else {
1330 ring = &epctx->ring;
1331 }
1332 if (ring) {
1333 ctx[2] = ring->dequeue | ring->ccs;
1334 ctx[3] = (ring->dequeue >> 16) >> 16;
1335
1336 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1337 epctx->pctx, state, ctx[3], ctx[2]);
1338 }
1339
1340 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1341 if (epctx->state != state) {
1342 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1343 ep_state_name(epctx->state),
1344 ep_state_name(state));
1345 }
1346 epctx->state = state;
1347 }
1348
1349 static void xhci_ep_kick_timer(void *opaque)
1350 {
1351 XHCIEPContext *epctx = opaque;
1352 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
1353 }
1354
1355 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1356 unsigned int slotid,
1357 unsigned int epid)
1358 {
1359 XHCIEPContext *epctx;
1360 int i;
1361
1362 epctx = g_new0(XHCIEPContext, 1);
1363 epctx->xhci = xhci;
1364 epctx->slotid = slotid;
1365 epctx->epid = epid;
1366
1367 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1368 epctx->transfers[i].xhci = xhci;
1369 epctx->transfers[i].slotid = slotid;
1370 epctx->transfers[i].epid = epid;
1371 usb_packet_init(&epctx->transfers[i].packet);
1372 }
1373 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1374
1375 return epctx;
1376 }
1377
1378 static void xhci_init_epctx(XHCIEPContext *epctx,
1379 dma_addr_t pctx, uint32_t *ctx)
1380 {
1381 dma_addr_t dequeue;
1382
1383 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1384
1385 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1386 epctx->pctx = pctx;
1387 epctx->max_psize = ctx[1]>>16;
1388 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1389 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1390 epctx->lsa = (ctx[0] >> 15) & 1;
1391 if (epctx->max_pstreams) {
1392 xhci_alloc_streams(epctx, dequeue);
1393 } else {
1394 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1395 epctx->ring.ccs = ctx[2] & 1;
1396 }
1397
1398 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1399 }
1400
1401 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1402 unsigned int epid, dma_addr_t pctx,
1403 uint32_t *ctx)
1404 {
1405 XHCISlot *slot;
1406 XHCIEPContext *epctx;
1407
1408 trace_usb_xhci_ep_enable(slotid, epid);
1409 assert(slotid >= 1 && slotid <= xhci->numslots);
1410 assert(epid >= 1 && epid <= 31);
1411
1412 slot = &xhci->slots[slotid-1];
1413 if (slot->eps[epid-1]) {
1414 xhci_disable_ep(xhci, slotid, epid);
1415 }
1416
1417 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1418 slot->eps[epid-1] = epctx;
1419 xhci_init_epctx(epctx, pctx, ctx);
1420
1421 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1422 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1423
1424 epctx->mfindex_last = 0;
1425
1426 epctx->state = EP_RUNNING;
1427 ctx[0] &= ~EP_STATE_MASK;
1428 ctx[0] |= EP_RUNNING;
1429
1430 return CC_SUCCESS;
1431 }
1432
1433 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1434 {
1435 int killed = 0;
1436
1437 if (report && (t->running_async || t->running_retry)) {
1438 t->status = report;
1439 xhci_xfer_report(t);
1440 }
1441
1442 if (t->running_async) {
1443 usb_cancel_packet(&t->packet);
1444 t->running_async = 0;
1445 killed = 1;
1446 }
1447 if (t->running_retry) {
1448 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1449 if (epctx) {
1450 epctx->retry = NULL;
1451 timer_del(epctx->kick_timer);
1452 }
1453 t->running_retry = 0;
1454 killed = 1;
1455 }
1456 if (t->trbs) {
1457 g_free(t->trbs);
1458 }
1459
1460 t->trbs = NULL;
1461 t->trb_count = t->trb_alloced = 0;
1462
1463 return killed;
1464 }
1465
1466 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1467 unsigned int epid, TRBCCode report)
1468 {
1469 XHCISlot *slot;
1470 XHCIEPContext *epctx;
1471 int i, xferi, killed = 0;
1472 USBEndpoint *ep = NULL;
1473 assert(slotid >= 1 && slotid <= xhci->numslots);
1474 assert(epid >= 1 && epid <= 31);
1475
1476 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1477
1478 slot = &xhci->slots[slotid-1];
1479
1480 if (!slot->eps[epid-1]) {
1481 return 0;
1482 }
1483
1484 epctx = slot->eps[epid-1];
1485
1486 xferi = epctx->next_xfer;
1487 for (i = 0; i < TD_QUEUE; i++) {
1488 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report);
1489 if (killed) {
1490 report = 0; /* Only report once */
1491 }
1492 epctx->transfers[xferi].packet.ep = NULL;
1493 xferi = (xferi + 1) % TD_QUEUE;
1494 }
1495
1496 ep = xhci_epid_to_usbep(xhci, slotid, epid);
1497 if (ep) {
1498 usb_device_ep_stopped(ep->dev, ep);
1499 }
1500 return killed;
1501 }
1502
1503 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1504 unsigned int epid)
1505 {
1506 XHCISlot *slot;
1507 XHCIEPContext *epctx;
1508 int i;
1509
1510 trace_usb_xhci_ep_disable(slotid, epid);
1511 assert(slotid >= 1 && slotid <= xhci->numslots);
1512 assert(epid >= 1 && epid <= 31);
1513
1514 slot = &xhci->slots[slotid-1];
1515
1516 if (!slot->eps[epid-1]) {
1517 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1518 return CC_SUCCESS;
1519 }
1520
1521 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1522
1523 epctx = slot->eps[epid-1];
1524
1525 if (epctx->nr_pstreams) {
1526 xhci_free_streams(epctx);
1527 }
1528
1529 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1530 usb_packet_cleanup(&epctx->transfers[i].packet);
1531 }
1532
1533 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1534
1535 timer_free(epctx->kick_timer);
1536 g_free(epctx);
1537 slot->eps[epid-1] = NULL;
1538
1539 return CC_SUCCESS;
1540 }
1541
1542 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1543 unsigned int epid)
1544 {
1545 XHCISlot *slot;
1546 XHCIEPContext *epctx;
1547
1548 trace_usb_xhci_ep_stop(slotid, epid);
1549 assert(slotid >= 1 && slotid <= xhci->numslots);
1550
1551 if (epid < 1 || epid > 31) {
1552 DPRINTF("xhci: bad ep %d\n", epid);
1553 return CC_TRB_ERROR;
1554 }
1555
1556 slot = &xhci->slots[slotid-1];
1557
1558 if (!slot->eps[epid-1]) {
1559 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1560 return CC_EP_NOT_ENABLED_ERROR;
1561 }
1562
1563 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1564 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1565 "data might be lost\n");
1566 }
1567
1568 epctx = slot->eps[epid-1];
1569
1570 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1571
1572 if (epctx->nr_pstreams) {
1573 xhci_reset_streams(epctx);
1574 }
1575
1576 return CC_SUCCESS;
1577 }
1578
1579 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1580 unsigned int epid)
1581 {
1582 XHCISlot *slot;
1583 XHCIEPContext *epctx;
1584
1585 trace_usb_xhci_ep_reset(slotid, epid);
1586 assert(slotid >= 1 && slotid <= xhci->numslots);
1587
1588 if (epid < 1 || epid > 31) {
1589 DPRINTF("xhci: bad ep %d\n", epid);
1590 return CC_TRB_ERROR;
1591 }
1592
1593 slot = &xhci->slots[slotid-1];
1594
1595 if (!slot->eps[epid-1]) {
1596 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1597 return CC_EP_NOT_ENABLED_ERROR;
1598 }
1599
1600 epctx = slot->eps[epid-1];
1601
1602 if (epctx->state != EP_HALTED) {
1603 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1604 epid, epctx->state);
1605 return CC_CONTEXT_STATE_ERROR;
1606 }
1607
1608 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1609 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1610 "data might be lost\n");
1611 }
1612
1613 if (!xhci->slots[slotid-1].uport ||
1614 !xhci->slots[slotid-1].uport->dev ||
1615 !xhci->slots[slotid-1].uport->dev->attached) {
1616 return CC_USB_TRANSACTION_ERROR;
1617 }
1618
1619 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1620
1621 if (epctx->nr_pstreams) {
1622 xhci_reset_streams(epctx);
1623 }
1624
1625 return CC_SUCCESS;
1626 }
1627
1628 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1629 unsigned int epid, unsigned int streamid,
1630 uint64_t pdequeue)
1631 {
1632 XHCISlot *slot;
1633 XHCIEPContext *epctx;
1634 XHCIStreamContext *sctx;
1635 dma_addr_t dequeue;
1636
1637 assert(slotid >= 1 && slotid <= xhci->numslots);
1638
1639 if (epid < 1 || epid > 31) {
1640 DPRINTF("xhci: bad ep %d\n", epid);
1641 return CC_TRB_ERROR;
1642 }
1643
1644 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1645 dequeue = xhci_mask64(pdequeue);
1646
1647 slot = &xhci->slots[slotid-1];
1648
1649 if (!slot->eps[epid-1]) {
1650 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1651 return CC_EP_NOT_ENABLED_ERROR;
1652 }
1653
1654 epctx = slot->eps[epid-1];
1655
1656 if (epctx->state != EP_STOPPED) {
1657 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1658 return CC_CONTEXT_STATE_ERROR;
1659 }
1660
1661 if (epctx->nr_pstreams) {
1662 uint32_t err;
1663 sctx = xhci_find_stream(epctx, streamid, &err);
1664 if (sctx == NULL) {
1665 return err;
1666 }
1667 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1668 sctx->ring.ccs = dequeue & 1;
1669 } else {
1670 sctx = NULL;
1671 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1672 epctx->ring.ccs = dequeue & 1;
1673 }
1674
1675 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1676
1677 return CC_SUCCESS;
1678 }
1679
1680 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1681 {
1682 XHCIState *xhci = xfer->xhci;
1683 int i;
1684
1685 xfer->int_req = false;
1686 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
1687 for (i = 0; i < xfer->trb_count; i++) {
1688 XHCITRB *trb = &xfer->trbs[i];
1689 dma_addr_t addr;
1690 unsigned int chunk = 0;
1691
1692 if (trb->control & TRB_TR_IOC) {
1693 xfer->int_req = true;
1694 }
1695
1696 switch (TRB_TYPE(*trb)) {
1697 case TR_DATA:
1698 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1699 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1700 goto err;
1701 }
1702 /* fallthrough */
1703 case TR_NORMAL:
1704 case TR_ISOCH:
1705 addr = xhci_mask64(trb->parameter);
1706 chunk = trb->status & 0x1ffff;
1707 if (trb->control & TRB_TR_IDT) {
1708 if (chunk > 8 || in_xfer) {
1709 DPRINTF("xhci: invalid immediate data TRB\n");
1710 goto err;
1711 }
1712 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1713 } else {
1714 qemu_sglist_add(&xfer->sgl, addr, chunk);
1715 }
1716 break;
1717 }
1718 }
1719
1720 return 0;
1721
1722 err:
1723 qemu_sglist_destroy(&xfer->sgl);
1724 xhci_die(xhci);
1725 return -1;
1726 }
1727
1728 static void xhci_xfer_unmap(XHCITransfer *xfer)
1729 {
1730 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1731 qemu_sglist_destroy(&xfer->sgl);
1732 }
1733
1734 static void xhci_xfer_report(XHCITransfer *xfer)
1735 {
1736 uint32_t edtla = 0;
1737 unsigned int left;
1738 bool reported = 0;
1739 bool shortpkt = 0;
1740 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1741 XHCIState *xhci = xfer->xhci;
1742 int i;
1743
1744 left = xfer->packet.actual_length;
1745
1746 for (i = 0; i < xfer->trb_count; i++) {
1747 XHCITRB *trb = &xfer->trbs[i];
1748 unsigned int chunk = 0;
1749
1750 switch (TRB_TYPE(*trb)) {
1751 case TR_DATA:
1752 case TR_NORMAL:
1753 case TR_ISOCH:
1754 chunk = trb->status & 0x1ffff;
1755 if (chunk > left) {
1756 chunk = left;
1757 if (xfer->status == CC_SUCCESS) {
1758 shortpkt = 1;
1759 }
1760 }
1761 left -= chunk;
1762 edtla += chunk;
1763 break;
1764 case TR_STATUS:
1765 reported = 0;
1766 shortpkt = 0;
1767 break;
1768 }
1769
1770 /*
1771 * XHCI 1.1, 4.11.3.1 Transfer Event TRB -- "each Transfer TRB
1772 * encountered with its IOC flag set to '1' shall generate a Transfer
1773 * Event."
1774 *
1775 * Otherwise, longer transfers can have multiple data TRBs (for scatter
1776 * gather). Short transfers and errors should be reported once per
1777 * transfer only.
1778 */
1779 if ((trb->control & TRB_TR_IOC) ||
1780 (!reported && ((shortpkt && (trb->control & TRB_TR_ISP)) ||
1781 (xfer->status != CC_SUCCESS && left == 0)))) {
1782 event.slotid = xfer->slotid;
1783 event.epid = xfer->epid;
1784 event.length = (trb->status & 0x1ffff) - chunk;
1785 event.flags = 0;
1786 event.ptr = trb->addr;
1787 if (xfer->status == CC_SUCCESS) {
1788 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1789 } else {
1790 event.ccode = xfer->status;
1791 }
1792 if (TRB_TYPE(*trb) == TR_EVDATA) {
1793 event.ptr = trb->parameter;
1794 event.flags |= TRB_EV_ED;
1795 event.length = edtla & 0xffffff;
1796 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1797 edtla = 0;
1798 }
1799 xhci_event(xhci, &event, TRB_INTR(*trb));
1800 reported = 1;
1801 if (xfer->status != CC_SUCCESS) {
1802 return;
1803 }
1804 }
1805 }
1806 }
1807
1808 static void xhci_stall_ep(XHCITransfer *xfer)
1809 {
1810 XHCIState *xhci = xfer->xhci;
1811 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1812 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1813 uint32_t err;
1814 XHCIStreamContext *sctx;
1815
1816 if (epctx->nr_pstreams) {
1817 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1818 if (sctx == NULL) {
1819 return;
1820 }
1821 sctx->ring.dequeue = xfer->trbs[0].addr;
1822 sctx->ring.ccs = xfer->trbs[0].ccs;
1823 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1824 } else {
1825 epctx->ring.dequeue = xfer->trbs[0].addr;
1826 epctx->ring.ccs = xfer->trbs[0].ccs;
1827 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1828 }
1829 }
1830
1831 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1832 XHCIEPContext *epctx);
1833
1834 static int xhci_setup_packet(XHCITransfer *xfer)
1835 {
1836 XHCIState *xhci = xfer->xhci;
1837 USBEndpoint *ep;
1838 int dir;
1839
1840 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1841
1842 if (xfer->packet.ep) {
1843 ep = xfer->packet.ep;
1844 } else {
1845 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid);
1846 if (!ep) {
1847 DPRINTF("xhci: slot %d has no device\n",
1848 xfer->slotid);
1849 return -1;
1850 }
1851 }
1852
1853 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1854 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1855 xfer->trbs[0].addr, false, xfer->int_req);
1856 usb_packet_map(&xfer->packet, &xfer->sgl);
1857 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1858 xfer->packet.pid, ep->dev->addr, ep->nr);
1859 return 0;
1860 }
1861
1862 static int xhci_complete_packet(XHCITransfer *xfer)
1863 {
1864 if (xfer->packet.status == USB_RET_ASYNC) {
1865 trace_usb_xhci_xfer_async(xfer);
1866 xfer->running_async = 1;
1867 xfer->running_retry = 0;
1868 xfer->complete = 0;
1869 return 0;
1870 } else if (xfer->packet.status == USB_RET_NAK) {
1871 trace_usb_xhci_xfer_nak(xfer);
1872 xfer->running_async = 0;
1873 xfer->running_retry = 1;
1874 xfer->complete = 0;
1875 return 0;
1876 } else {
1877 xfer->running_async = 0;
1878 xfer->running_retry = 0;
1879 xfer->complete = 1;
1880 xhci_xfer_unmap(xfer);
1881 }
1882
1883 if (xfer->packet.status == USB_RET_SUCCESS) {
1884 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1885 xfer->status = CC_SUCCESS;
1886 xhci_xfer_report(xfer);
1887 return 0;
1888 }
1889
1890 /* error */
1891 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1892 switch (xfer->packet.status) {
1893 case USB_RET_NODEV:
1894 case USB_RET_IOERROR:
1895 xfer->status = CC_USB_TRANSACTION_ERROR;
1896 xhci_xfer_report(xfer);
1897 xhci_stall_ep(xfer);
1898 break;
1899 case USB_RET_STALL:
1900 xfer->status = CC_STALL_ERROR;
1901 xhci_xfer_report(xfer);
1902 xhci_stall_ep(xfer);
1903 break;
1904 case USB_RET_BABBLE:
1905 xfer->status = CC_BABBLE_DETECTED;
1906 xhci_xfer_report(xfer);
1907 xhci_stall_ep(xfer);
1908 break;
1909 default:
1910 DPRINTF("%s: FIXME: status = %d\n", __func__,
1911 xfer->packet.status);
1912 FIXME("unhandled USB_RET_*");
1913 }
1914 return 0;
1915 }
1916
1917 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1918 {
1919 XHCITRB *trb_setup, *trb_status;
1920 uint8_t bmRequestType;
1921
1922 trb_setup = &xfer->trbs[0];
1923 trb_status = &xfer->trbs[xfer->trb_count-1];
1924
1925 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1926
1927 /* at most one Event Data TRB allowed after STATUS */
1928 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1929 trb_status--;
1930 }
1931
1932 /* do some sanity checks */
1933 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1934 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1935 TRB_TYPE(*trb_setup));
1936 return -1;
1937 }
1938 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1939 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1940 TRB_TYPE(*trb_status));
1941 return -1;
1942 }
1943 if (!(trb_setup->control & TRB_TR_IDT)) {
1944 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1945 return -1;
1946 }
1947 if ((trb_setup->status & 0x1ffff) != 8) {
1948 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1949 (trb_setup->status & 0x1ffff));
1950 return -1;
1951 }
1952
1953 bmRequestType = trb_setup->parameter;
1954
1955 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1956 xfer->iso_xfer = false;
1957 xfer->timed_xfer = false;
1958
1959 if (xhci_setup_packet(xfer) < 0) {
1960 return -1;
1961 }
1962 xfer->packet.parameter = trb_setup->parameter;
1963
1964 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1965
1966 xhci_complete_packet(xfer);
1967 if (!xfer->running_async && !xfer->running_retry) {
1968 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
1969 }
1970 return 0;
1971 }
1972
1973 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1974 XHCIEPContext *epctx, uint64_t mfindex)
1975 {
1976 uint64_t asap = ((mfindex + epctx->interval - 1) &
1977 ~(epctx->interval-1));
1978 uint64_t kick = epctx->mfindex_last + epctx->interval;
1979
1980 assert(epctx->interval != 0);
1981 xfer->mfindex_kick = MAX(asap, kick);
1982 }
1983
1984 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1985 XHCIEPContext *epctx, uint64_t mfindex)
1986 {
1987 if (xfer->trbs[0].control & TRB_TR_SIA) {
1988 uint64_t asap = ((mfindex + epctx->interval - 1) &
1989 ~(epctx->interval-1));
1990 if (asap >= epctx->mfindex_last &&
1991 asap <= epctx->mfindex_last + epctx->interval * 4) {
1992 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1993 } else {
1994 xfer->mfindex_kick = asap;
1995 }
1996 } else {
1997 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1998 & TRB_TR_FRAMEID_MASK) << 3;
1999 xfer->mfindex_kick |= mfindex & ~0x3fff;
2000 if (xfer->mfindex_kick + 0x100 < mfindex) {
2001 xfer->mfindex_kick += 0x4000;
2002 }
2003 }
2004 }
2005
2006 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
2007 XHCIEPContext *epctx, uint64_t mfindex)
2008 {
2009 if (xfer->mfindex_kick > mfindex) {
2010 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2011 (xfer->mfindex_kick - mfindex) * 125000);
2012 xfer->running_retry = 1;
2013 } else {
2014 epctx->mfindex_last = xfer->mfindex_kick;
2015 timer_del(epctx->kick_timer);
2016 xfer->running_retry = 0;
2017 }
2018 }
2019
2020
2021 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2022 {
2023 uint64_t mfindex;
2024
2025 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
2026
2027 xfer->in_xfer = epctx->type>>2;
2028
2029 switch(epctx->type) {
2030 case ET_INTR_OUT:
2031 case ET_INTR_IN:
2032 xfer->pkts = 0;
2033 xfer->iso_xfer = false;
2034 xfer->timed_xfer = true;
2035 mfindex = xhci_mfindex_get(xhci);
2036 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
2037 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2038 if (xfer->running_retry) {
2039 return -1;
2040 }
2041 break;
2042 case ET_BULK_OUT:
2043 case ET_BULK_IN:
2044 xfer->pkts = 0;
2045 xfer->iso_xfer = false;
2046 xfer->timed_xfer = false;
2047 break;
2048 case ET_ISO_OUT:
2049 case ET_ISO_IN:
2050 xfer->pkts = 1;
2051 xfer->iso_xfer = true;
2052 xfer->timed_xfer = true;
2053 mfindex = xhci_mfindex_get(xhci);
2054 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
2055 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2056 if (xfer->running_retry) {
2057 return -1;
2058 }
2059 break;
2060 default:
2061 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
2062 return -1;
2063 }
2064
2065 if (xhci_setup_packet(xfer) < 0) {
2066 return -1;
2067 }
2068 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2069
2070 xhci_complete_packet(xfer);
2071 if (!xfer->running_async && !xfer->running_retry) {
2072 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
2073 }
2074 return 0;
2075 }
2076
2077 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2078 {
2079 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
2080 return xhci_submit(xhci, xfer, epctx);
2081 }
2082
2083 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
2084 unsigned int epid, unsigned int streamid)
2085 {
2086 XHCIStreamContext *stctx;
2087 XHCIEPContext *epctx;
2088 XHCIRing *ring;
2089 USBEndpoint *ep = NULL;
2090 uint64_t mfindex;
2091 int length;
2092 int i;
2093
2094 trace_usb_xhci_ep_kick(slotid, epid, streamid);
2095 assert(slotid >= 1 && slotid <= xhci->numslots);
2096 assert(epid >= 1 && epid <= 31);
2097
2098 if (!xhci->slots[slotid-1].enabled) {
2099 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
2100 return;
2101 }
2102 epctx = xhci->slots[slotid-1].eps[epid-1];
2103 if (!epctx) {
2104 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2105 epid, slotid);
2106 return;
2107 }
2108
2109 /* If the device has been detached, but the guest has not noticed this
2110 yet the 2 above checks will succeed, but we must NOT continue */
2111 if (!xhci->slots[slotid - 1].uport ||
2112 !xhci->slots[slotid - 1].uport->dev ||
2113 !xhci->slots[slotid - 1].uport->dev->attached) {
2114 return;
2115 }
2116
2117 if (epctx->retry) {
2118 XHCITransfer *xfer = epctx->retry;
2119
2120 trace_usb_xhci_xfer_retry(xfer);
2121 assert(xfer->running_retry);
2122 if (xfer->timed_xfer) {
2123 /* time to kick the transfer? */
2124 mfindex = xhci_mfindex_get(xhci);
2125 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2126 if (xfer->running_retry) {
2127 return;
2128 }
2129 xfer->timed_xfer = 0;
2130 xfer->running_retry = 1;
2131 }
2132 if (xfer->iso_xfer) {
2133 /* retry iso transfer */
2134 if (xhci_setup_packet(xfer) < 0) {
2135 return;
2136 }
2137 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2138 assert(xfer->packet.status != USB_RET_NAK);
2139 xhci_complete_packet(xfer);
2140 } else {
2141 /* retry nak'ed transfer */
2142 if (xhci_setup_packet(xfer) < 0) {
2143 return;
2144 }
2145 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2146 if (xfer->packet.status == USB_RET_NAK) {
2147 return;
2148 }
2149 xhci_complete_packet(xfer);
2150 }
2151 assert(!xfer->running_retry);
2152 epctx->retry = NULL;
2153 }
2154
2155 if (epctx->state == EP_HALTED) {
2156 DPRINTF("xhci: ep halted, not running schedule\n");
2157 return;
2158 }
2159
2160
2161 if (epctx->nr_pstreams) {
2162 uint32_t err;
2163 stctx = xhci_find_stream(epctx, streamid, &err);
2164 if (stctx == NULL) {
2165 return;
2166 }
2167 ring = &stctx->ring;
2168 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
2169 } else {
2170 ring = &epctx->ring;
2171 streamid = 0;
2172 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
2173 }
2174 assert(ring->dequeue != 0);
2175
2176 while (1) {
2177 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
2178 if (xfer->running_async || xfer->running_retry) {
2179 break;
2180 }
2181 length = xhci_ring_chain_length(xhci, ring);
2182 if (length < 0) {
2183 break;
2184 } else if (length == 0) {
2185 break;
2186 }
2187 if (xfer->trbs && xfer->trb_alloced < length) {
2188 xfer->trb_count = 0;
2189 xfer->trb_alloced = 0;
2190 g_free(xfer->trbs);
2191 xfer->trbs = NULL;
2192 }
2193 if (!xfer->trbs) {
2194 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
2195 xfer->trb_alloced = length;
2196 }
2197 xfer->trb_count = length;
2198
2199 for (i = 0; i < length; i++) {
2200 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL));
2201 }
2202 xfer->streamid = streamid;
2203
2204 if (epid == 1) {
2205 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
2206 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2207 ep = xfer->packet.ep;
2208 } else {
2209 DPRINTF("xhci: error firing CTL transfer\n");
2210 }
2211 } else {
2212 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
2213 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2214 } else {
2215 if (!xfer->timed_xfer) {
2216 DPRINTF("xhci: error firing data transfer\n");
2217 }
2218 }
2219 }
2220
2221 if (epctx->state == EP_HALTED) {
2222 break;
2223 }
2224 if (xfer->running_retry) {
2225 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2226 epctx->retry = xfer;
2227 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2228 epctx->interval * 125000);
2229 break;
2230 }
2231 }
2232
2233 ep = xhci_epid_to_usbep(xhci, slotid, epid);
2234 if (ep) {
2235 usb_device_flush_ep_queue(ep->dev, ep);
2236 }
2237 }
2238
2239 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2240 {
2241 trace_usb_xhci_slot_enable(slotid);
2242 assert(slotid >= 1 && slotid <= xhci->numslots);
2243 xhci->slots[slotid-1].enabled = 1;
2244 xhci->slots[slotid-1].uport = NULL;
2245 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2246
2247 return CC_SUCCESS;
2248 }
2249
2250 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2251 {
2252 int i;
2253
2254 trace_usb_xhci_slot_disable(slotid);
2255 assert(slotid >= 1 && slotid <= xhci->numslots);
2256
2257 for (i = 1; i <= 31; i++) {
2258 if (xhci->slots[slotid-1].eps[i-1]) {
2259 xhci_disable_ep(xhci, slotid, i);
2260 }
2261 }
2262
2263 xhci->slots[slotid-1].enabled = 0;
2264 xhci->slots[slotid-1].addressed = 0;
2265 xhci->slots[slotid-1].uport = NULL;
2266 return CC_SUCCESS;
2267 }
2268
2269 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2270 {
2271 USBPort *uport;
2272 char path[32];
2273 int i, pos, port;
2274
2275 port = (slot_ctx[1]>>16) & 0xFF;
2276 if (port < 1 || port > xhci->numports) {
2277 return NULL;
2278 }
2279 port = xhci->ports[port-1].uport->index+1;
2280 pos = snprintf(path, sizeof(path), "%d", port);
2281 for (i = 0; i < 5; i++) {
2282 port = (slot_ctx[0] >> 4*i) & 0x0f;
2283 if (!port) {
2284 break;
2285 }
2286 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2287 }
2288
2289 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2290 if (strcmp(uport->path, path) == 0) {
2291 return uport;
2292 }
2293 }
2294 return NULL;
2295 }
2296
2297 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2298 uint64_t pictx, bool bsr)
2299 {
2300 XHCISlot *slot;
2301 USBPort *uport;
2302 USBDevice *dev;
2303 dma_addr_t ictx, octx, dcbaap;
2304 uint64_t poctx;
2305 uint32_t ictl_ctx[2];
2306 uint32_t slot_ctx[4];
2307 uint32_t ep0_ctx[5];
2308 int i;
2309 TRBCCode res;
2310
2311 assert(slotid >= 1 && slotid <= xhci->numslots);
2312
2313 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2314 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
2315 ictx = xhci_mask64(pictx);
2316 octx = xhci_mask64(poctx);
2317
2318 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2319 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2320
2321 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2322
2323 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2324 DPRINTF("xhci: invalid input context control %08x %08x\n",
2325 ictl_ctx[0], ictl_ctx[1]);
2326 return CC_TRB_ERROR;
2327 }
2328
2329 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2330 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2331
2332 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2333 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2334
2335 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2336 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2337
2338 uport = xhci_lookup_uport(xhci, slot_ctx);
2339 if (uport == NULL) {
2340 DPRINTF("xhci: port not found\n");
2341 return CC_TRB_ERROR;
2342 }
2343 trace_usb_xhci_slot_address(slotid, uport->path);
2344
2345 dev = uport->dev;
2346 if (!dev || !dev->attached) {
2347 DPRINTF("xhci: port %s not connected\n", uport->path);
2348 return CC_USB_TRANSACTION_ERROR;
2349 }
2350
2351 for (i = 0; i < xhci->numslots; i++) {
2352 if (i == slotid-1) {
2353 continue;
2354 }
2355 if (xhci->slots[i].uport == uport) {
2356 DPRINTF("xhci: port %s already assigned to slot %d\n",
2357 uport->path, i+1);
2358 return CC_TRB_ERROR;
2359 }
2360 }
2361
2362 slot = &xhci->slots[slotid-1];
2363 slot->uport = uport;
2364 slot->ctx = octx;
2365
2366 if (bsr) {
2367 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2368 } else {
2369 USBPacket p;
2370 uint8_t buf[1];
2371
2372 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2373 usb_device_reset(dev);
2374 memset(&p, 0, sizeof(p));
2375 usb_packet_addbuf(&p, buf, sizeof(buf));
2376 usb_packet_setup(&p, USB_TOKEN_OUT,
2377 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2378 0, false, false);
2379 usb_device_handle_control(dev, &p,
2380 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2381 slotid, 0, 0, NULL);
2382 assert(p.status != USB_RET_ASYNC);
2383 }
2384
2385 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2386
2387 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2388 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2389 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2390 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2391
2392 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2393 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2394
2395 xhci->slots[slotid-1].addressed = 1;
2396 return res;
2397 }
2398
2399
2400 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2401 uint64_t pictx, bool dc)
2402 {
2403 dma_addr_t ictx, octx;
2404 uint32_t ictl_ctx[2];
2405 uint32_t slot_ctx[4];
2406 uint32_t islot_ctx[4];
2407 uint32_t ep_ctx[5];
2408 int i;
2409 TRBCCode res;
2410
2411 trace_usb_xhci_slot_configure(slotid);
2412 assert(slotid >= 1 && slotid <= xhci->numslots);
2413
2414 ictx = xhci_mask64(pictx);
2415 octx = xhci->slots[slotid-1].ctx;
2416
2417 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2418 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2419
2420 if (dc) {
2421 for (i = 2; i <= 31; i++) {
2422 if (xhci->slots[slotid-1].eps[i-1]) {
2423 xhci_disable_ep(xhci, slotid, i);
2424 }
2425 }
2426
2427 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2428 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2429 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2430 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2431 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2432 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2433
2434 return CC_SUCCESS;
2435 }
2436
2437 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2438
2439 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2440 DPRINTF("xhci: invalid input context control %08x %08x\n",
2441 ictl_ctx[0], ictl_ctx[1]);
2442 return CC_TRB_ERROR;
2443 }
2444
2445 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2446 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2447
2448 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2449 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2450 return CC_CONTEXT_STATE_ERROR;
2451 }
2452
2453 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2454
2455 for (i = 2; i <= 31; i++) {
2456 if (ictl_ctx[0] & (1<<i)) {
2457 xhci_disable_ep(xhci, slotid, i);
2458 }
2459 if (ictl_ctx[1] & (1<<i)) {
2460 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2461 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2462 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2463 ep_ctx[3], ep_ctx[4]);
2464 xhci_disable_ep(xhci, slotid, i);
2465 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2466 if (res != CC_SUCCESS) {
2467 return res;
2468 }
2469 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2470 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2471 ep_ctx[3], ep_ctx[4]);
2472 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2473 }
2474 }
2475
2476 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2477 if (res != CC_SUCCESS) {
2478 for (i = 2; i <= 31; i++) {
2479 if (ictl_ctx[1] & (1u << i)) {
2480 xhci_disable_ep(xhci, slotid, i);
2481 }
2482 }
2483 return res;
2484 }
2485
2486 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2487 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2488 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2489 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2490 SLOT_CONTEXT_ENTRIES_SHIFT);
2491 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2492 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2493
2494 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2495
2496 return CC_SUCCESS;
2497 }
2498
2499
2500 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2501 uint64_t pictx)
2502 {
2503 dma_addr_t ictx, octx;
2504 uint32_t ictl_ctx[2];
2505 uint32_t iep0_ctx[5];
2506 uint32_t ep0_ctx[5];
2507 uint32_t islot_ctx[4];
2508 uint32_t slot_ctx[4];
2509
2510 trace_usb_xhci_slot_evaluate(slotid);
2511 assert(slotid >= 1 && slotid <= xhci->numslots);
2512
2513 ictx = xhci_mask64(pictx);
2514 octx = xhci->slots[slotid-1].ctx;
2515
2516 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2517 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2518
2519 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2520
2521 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2522 DPRINTF("xhci: invalid input context control %08x %08x\n",
2523 ictl_ctx[0], ictl_ctx[1]);
2524 return CC_TRB_ERROR;
2525 }
2526
2527 if (ictl_ctx[1] & 0x1) {
2528 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2529
2530 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2531 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2532
2533 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2534
2535 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2536 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2537 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2538 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2539
2540 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2541 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2542
2543 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2544 }
2545
2546 if (ictl_ctx[1] & 0x2) {
2547 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2548
2549 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2550 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2551 iep0_ctx[3], iep0_ctx[4]);
2552
2553 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2554
2555 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2556 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2557
2558 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2559 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2560
2561 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2562 }
2563
2564 return CC_SUCCESS;
2565 }
2566
2567 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2568 {
2569 uint32_t slot_ctx[4];
2570 dma_addr_t octx;
2571 int i;
2572
2573 trace_usb_xhci_slot_reset(slotid);
2574 assert(slotid >= 1 && slotid <= xhci->numslots);
2575
2576 octx = xhci->slots[slotid-1].ctx;
2577
2578 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2579
2580 for (i = 2; i <= 31; i++) {
2581 if (xhci->slots[slotid-1].eps[i-1]) {
2582 xhci_disable_ep(xhci, slotid, i);
2583 }
2584 }
2585
2586 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2587 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2588 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2589 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2590 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2591 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2592
2593 return CC_SUCCESS;
2594 }
2595
2596 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2597 {
2598 unsigned int slotid;
2599 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2600 if (slotid < 1 || slotid > xhci->numslots) {
2601 DPRINTF("xhci: bad slot id %d\n", slotid);
2602 event->ccode = CC_TRB_ERROR;
2603 return 0;
2604 } else if (!xhci->slots[slotid-1].enabled) {
2605 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2606 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2607 return 0;
2608 }
2609 return slotid;
2610 }
2611
2612 /* cleanup slot state on usb device detach */
2613 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2614 {
2615 int slot, ep;
2616
2617 for (slot = 0; slot < xhci->numslots; slot++) {
2618 if (xhci->slots[slot].uport == uport) {
2619 break;
2620 }
2621 }
2622 if (slot == xhci->numslots) {
2623 return;
2624 }
2625
2626 for (ep = 0; ep < 31; ep++) {
2627 if (xhci->slots[slot].eps[ep]) {
2628 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2629 }
2630 }
2631 xhci->slots[slot].uport = NULL;
2632 }
2633
2634 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2635 {
2636 dma_addr_t ctx;
2637 uint8_t bw_ctx[xhci->numports+1];
2638
2639 DPRINTF("xhci_get_port_bandwidth()\n");
2640
2641 ctx = xhci_mask64(pctx);
2642
2643 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2644
2645 /* TODO: actually implement real values here */
2646 bw_ctx[0] = 0;
2647 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2648 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
2649
2650 return CC_SUCCESS;
2651 }
2652
2653 static uint32_t rotl(uint32_t v, unsigned count)
2654 {
2655 count &= 31;
2656 return (v << count) | (v >> (32 - count));
2657 }
2658
2659
2660 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2661 {
2662 uint32_t val;
2663 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2664 val += rotl(lo + 0x49434878, hi & 0x1F);
2665 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2666 return ~val;
2667 }
2668
2669 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2670 {
2671 PCIDevice *pci_dev = PCI_DEVICE(xhci);
2672 uint32_t buf[8];
2673 uint32_t obuf[8];
2674 dma_addr_t paddr = xhci_mask64(addr);
2675
2676 pci_dma_read(pci_dev, paddr, &buf, 32);
2677
2678 memcpy(obuf, buf, sizeof(obuf));
2679
2680 if ((buf[0] & 0xff) == 2) {
2681 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2682 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2683 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2684 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2685 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2686 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2687 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2688 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2689 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2690 }
2691
2692 pci_dma_write(pci_dev, paddr, &obuf, 32);
2693 }
2694
2695 static void xhci_process_commands(XHCIState *xhci)
2696 {
2697 XHCITRB trb;
2698 TRBType type;
2699 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2700 dma_addr_t addr;
2701 unsigned int i, slotid = 0;
2702
2703 DPRINTF("xhci_process_commands()\n");
2704 if (!xhci_running(xhci)) {
2705 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2706 return;
2707 }
2708
2709 xhci->crcr_low |= CRCR_CRR;
2710
2711 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2712 event.ptr = addr;
2713 switch (type) {
2714 case CR_ENABLE_SLOT:
2715 for (i = 0; i < xhci->numslots; i++) {
2716 if (!xhci->slots[i].enabled) {
2717 break;
2718 }
2719 }
2720 if (i >= xhci->numslots) {
2721 DPRINTF("xhci: no device slots available\n");
2722 event.ccode = CC_NO_SLOTS_ERROR;
2723 } else {
2724 slotid = i+1;
2725 event.ccode = xhci_enable_slot(xhci, slotid);
2726 }
2727 break;
2728 case CR_DISABLE_SLOT:
2729 slotid = xhci_get_slot(xhci, &event, &trb);
2730 if (slotid) {
2731 event.ccode = xhci_disable_slot(xhci, slotid);
2732 }
2733 break;
2734 case CR_ADDRESS_DEVICE:
2735 slotid = xhci_get_slot(xhci, &event, &trb);
2736 if (slotid) {
2737 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2738 trb.control & TRB_CR_BSR);
2739 }
2740 break;
2741 case CR_CONFIGURE_ENDPOINT:
2742 slotid = xhci_get_slot(xhci, &event, &trb);
2743 if (slotid) {
2744 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2745 trb.control & TRB_CR_DC);
2746 }
2747 break;
2748 case CR_EVALUATE_CONTEXT:
2749 slotid = xhci_get_slot(xhci, &event, &trb);
2750 if (slotid) {
2751 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2752 }
2753 break;
2754 case CR_STOP_ENDPOINT:
2755 slotid = xhci_get_slot(xhci, &event, &trb);
2756 if (slotid) {
2757 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2758 & TRB_CR_EPID_MASK;
2759 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2760 }
2761 break;
2762 case CR_RESET_ENDPOINT:
2763 slotid = xhci_get_slot(xhci, &event, &trb);
2764 if (slotid) {
2765 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2766 & TRB_CR_EPID_MASK;
2767 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2768 }
2769 break;
2770 case CR_SET_TR_DEQUEUE:
2771 slotid = xhci_get_slot(xhci, &event, &trb);
2772 if (slotid) {
2773 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2774 & TRB_CR_EPID_MASK;
2775 unsigned int streamid = (trb.status >> 16) & 0xffff;
2776 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2777 epid, streamid,
2778 trb.parameter);
2779 }
2780 break;
2781 case CR_RESET_DEVICE:
2782 slotid = xhci_get_slot(xhci, &event, &trb);
2783 if (slotid) {
2784 event.ccode = xhci_reset_slot(xhci, slotid);
2785 }
2786 break;
2787 case CR_GET_PORT_BANDWIDTH:
2788 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2789 break;
2790 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2791 xhci_via_challenge(xhci, trb.parameter);
2792 break;
2793 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2794 event.type = 48; /* NEC reply */
2795 event.length = 0x3025;
2796 break;
2797 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2798 {
2799 uint32_t chi = trb.parameter >> 32;
2800 uint32_t clo = trb.parameter;
2801 uint32_t val = xhci_nec_challenge(chi, clo);
2802 event.length = val & 0xFFFF;
2803 event.epid = val >> 16;
2804 slotid = val >> 24;
2805 event.type = 48; /* NEC reply */
2806 }
2807 break;
2808 default:
2809 trace_usb_xhci_unimplemented("command", type);
2810 event.ccode = CC_TRB_ERROR;
2811 break;
2812 }
2813 event.slotid = slotid;
2814 xhci_event(xhci, &event, 0);
2815 }
2816 }
2817
2818 static bool xhci_port_have_device(XHCIPort *port)
2819 {
2820 if (!port->uport->dev || !port->uport->dev->attached) {
2821 return false; /* no device present */
2822 }
2823 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2824 return false; /* speed mismatch */
2825 }
2826 return true;
2827 }
2828
2829 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2830 {
2831 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2832 port->portnr << 24 };
2833
2834 if ((port->portsc & bits) == bits) {
2835 return;
2836 }
2837 trace_usb_xhci_port_notify(port->portnr, bits);
2838 port->portsc |= bits;
2839 if (!xhci_running(port->xhci)) {
2840 return;
2841 }
2842 xhci_event(port->xhci, &ev, 0);
2843 }
2844
2845 static void xhci_port_update(XHCIPort *port, int is_detach)
2846 {
2847 uint32_t pls = PLS_RX_DETECT;
2848
2849 port->portsc = PORTSC_PP;
2850 if (!is_detach && xhci_port_have_device(port)) {
2851 port->portsc |= PORTSC_CCS;
2852 switch (port->uport->dev->speed) {
2853 case USB_SPEED_LOW:
2854 port->portsc |= PORTSC_SPEED_LOW;
2855 pls = PLS_POLLING;
2856 break;
2857 case USB_SPEED_FULL:
2858 port->portsc |= PORTSC_SPEED_FULL;
2859 pls = PLS_POLLING;
2860 break;
2861 case USB_SPEED_HIGH:
2862 port->portsc |= PORTSC_SPEED_HIGH;
2863 pls = PLS_POLLING;
2864 break;
2865 case USB_SPEED_SUPER:
2866 port->portsc |= PORTSC_SPEED_SUPER;
2867 port->portsc |= PORTSC_PED;
2868 pls = PLS_U0;
2869 break;
2870 }
2871 }
2872 set_field(&port->portsc, pls, PORTSC_PLS);
2873 trace_usb_xhci_port_link(port->portnr, pls);
2874 xhci_port_notify(port, PORTSC_CSC);
2875 }
2876
2877 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2878 {
2879 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2880
2881 if (!xhci_port_have_device(port)) {
2882 return;
2883 }
2884
2885 usb_device_reset(port->uport->dev);
2886
2887 switch (port->uport->dev->speed) {
2888 case USB_SPEED_SUPER:
2889 if (warm_reset) {
2890 port->portsc |= PORTSC_WRC;
2891 }
2892 /* fall through */
2893 case USB_SPEED_LOW:
2894 case USB_SPEED_FULL:
2895 case USB_SPEED_HIGH:
2896 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2897 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2898 port->portsc |= PORTSC_PED;
2899 break;
2900 }
2901
2902 port->portsc &= ~PORTSC_PR;
2903 xhci_port_notify(port, PORTSC_PRC);
2904 }
2905
2906 static void xhci_reset(DeviceState *dev)
2907 {
2908 XHCIState *xhci = XHCI(dev);
2909 int i;
2910
2911 trace_usb_xhci_reset();
2912 if (!(xhci->usbsts & USBSTS_HCH)) {
2913 DPRINTF("xhci: reset while running!\n");
2914 }
2915
2916 xhci->usbcmd = 0;
2917 xhci->usbsts = USBSTS_HCH;
2918 xhci->dnctrl = 0;
2919 xhci->crcr_low = 0;
2920 xhci->crcr_high = 0;
2921 xhci->dcbaap_low = 0;
2922 xhci->dcbaap_high = 0;
2923 xhci->config = 0;
2924
2925 for (i = 0; i < xhci->numslots; i++) {
2926 xhci_disable_slot(xhci, i+1);
2927 }
2928
2929 for (i = 0; i < xhci->numports; i++) {
2930 xhci_port_update(xhci->ports + i, 0);
2931 }
2932
2933 for (i = 0; i < xhci->numintrs; i++) {
2934 xhci->intr[i].iman = 0;
2935 xhci->intr[i].imod = 0;
2936 xhci->intr[i].erstsz = 0;
2937 xhci->intr[i].erstba_low = 0;
2938 xhci->intr[i].erstba_high = 0;
2939 xhci->intr[i].erdp_low = 0;
2940 xhci->intr[i].erdp_high = 0;
2941 xhci->intr[i].msix_used = 0;
2942
2943 xhci->intr[i].er_ep_idx = 0;
2944 xhci->intr[i].er_pcs = 1;
2945 xhci->intr[i].er_full = 0;
2946 xhci->intr[i].ev_buffer_put = 0;
2947 xhci->intr[i].ev_buffer_get = 0;
2948 }
2949
2950 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2951 xhci_mfwrap_update(xhci);
2952 }
2953
2954 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2955 {
2956 XHCIState *xhci = ptr;
2957 uint32_t ret;
2958
2959 switch (reg) {
2960 case 0x00: /* HCIVERSION, CAPLENGTH */
2961 ret = 0x01000000 | LEN_CAP;
2962 break;
2963 case 0x04: /* HCSPARAMS 1 */
2964 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2965 | (xhci->numintrs<<8) | xhci->numslots;
2966 break;
2967 case 0x08: /* HCSPARAMS 2 */
2968 ret = 0x0000000f;
2969 break;
2970 case 0x0c: /* HCSPARAMS 3 */
2971 ret = 0x00000000;
2972 break;
2973 case 0x10: /* HCCPARAMS */
2974 if (sizeof(dma_addr_t) == 4) {
2975 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2976 } else {
2977 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2978 }
2979 break;
2980 case 0x14: /* DBOFF */
2981 ret = OFF_DOORBELL;
2982 break;
2983 case 0x18: /* RTSOFF */
2984 ret = OFF_RUNTIME;
2985 break;
2986
2987 /* extended capabilities */
2988 case 0x20: /* Supported Protocol:00 */
2989 ret = 0x02000402; /* USB 2.0 */
2990 break;
2991 case 0x24: /* Supported Protocol:04 */
2992 ret = 0x20425355; /* "USB " */
2993 break;
2994 case 0x28: /* Supported Protocol:08 */
2995 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2996 ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
2997 } else {
2998 ret = (xhci->numports_2<<8) | 1;
2999 }
3000 break;
3001 case 0x2c: /* Supported Protocol:0c */
3002 ret = 0x00000000; /* reserved */
3003 break;
3004 case 0x30: /* Supported Protocol:00 */
3005 ret = 0x03000002; /* USB 3.0 */
3006 break;
3007 case 0x34: /* Supported Protocol:04 */
3008 ret = 0x20425355; /* "USB " */
3009 break;
3010 case 0x38: /* Supported Protocol:08 */
3011 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3012 ret = (xhci->numports_3<<8) | 1;
3013 } else {
3014 ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
3015 }
3016 break;
3017 case 0x3c: /* Supported Protocol:0c */
3018 ret = 0x00000000; /* reserved */
3019 break;
3020 default:
3021 trace_usb_xhci_unimplemented("cap read", reg);
3022 ret = 0;
3023 }
3024
3025 trace_usb_xhci_cap_read(reg, ret);
3026 return ret;
3027 }
3028
3029 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
3030 {
3031 XHCIPort *port = ptr;
3032 uint32_t ret;
3033
3034 switch (reg) {
3035 case 0x00: /* PORTSC */
3036 ret = port->portsc;
3037 break;
3038 case 0x04: /* PORTPMSC */
3039 case 0x08: /* PORTLI */
3040 ret = 0;
3041 break;
3042 case 0x0c: /* reserved */
3043 default:
3044 trace_usb_xhci_unimplemented("port read", reg);
3045 ret = 0;
3046 }
3047
3048 trace_usb_xhci_port_read(port->portnr, reg, ret);
3049 return ret;
3050 }
3051
3052 static void xhci_port_write(void *ptr, hwaddr reg,
3053 uint64_t val, unsigned size)
3054 {
3055 XHCIPort *port = ptr;
3056 uint32_t portsc, notify;
3057
3058 trace_usb_xhci_port_write(port->portnr, reg, val);
3059
3060 switch (reg) {
3061 case 0x00: /* PORTSC */
3062 /* write-1-to-start bits */
3063 if (val & PORTSC_WPR) {
3064 xhci_port_reset(port, true);
3065 break;
3066 }
3067 if (val & PORTSC_PR) {
3068 xhci_port_reset(port, false);
3069 break;
3070 }
3071
3072 portsc = port->portsc;
3073 notify = 0;
3074 /* write-1-to-clear bits*/
3075 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
3076 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
3077 if (val & PORTSC_LWS) {
3078 /* overwrite PLS only when LWS=1 */
3079 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
3080 uint32_t new_pls = get_field(val, PORTSC_PLS);
3081 switch (new_pls) {
3082 case PLS_U0:
3083 if (old_pls != PLS_U0) {
3084 set_field(&portsc, new_pls, PORTSC_PLS);
3085 trace_usb_xhci_port_link(port->portnr, new_pls);
3086 notify = PORTSC_PLC;
3087 }
3088 break;
3089 case PLS_U3:
3090 if (old_pls < PLS_U3) {
3091 set_field(&portsc, new_pls, PORTSC_PLS);
3092 trace_usb_xhci_port_link(port->portnr, new_pls);
3093 }
3094 break;
3095 case PLS_RESUME:
3096 /* windows does this for some reason, don't spam stderr */
3097 break;
3098 default:
3099 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
3100 __func__, old_pls, new_pls);
3101 break;
3102 }
3103 }
3104 /* read/write bits */
3105 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
3106 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
3107 port->portsc = portsc;
3108 if (notify) {
3109 xhci_port_notify(port, notify);
3110 }
3111 break;
3112 case 0x04: /* PORTPMSC */
3113 case 0x08: /* PORTLI */
3114 default:
3115 trace_usb_xhci_unimplemented("port write", reg);
3116 }
3117 }
3118
3119 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
3120 {
3121 XHCIState *xhci = ptr;
3122 uint32_t ret;
3123
3124 switch (reg) {
3125 case 0x00: /* USBCMD */
3126 ret = xhci->usbcmd;
3127 break;
3128 case 0x04: /* USBSTS */
3129 ret = xhci->usbsts;
3130 break;
3131 case 0x08: /* PAGESIZE */
3132 ret = 1; /* 4KiB */
3133 break;
3134 case 0x14: /* DNCTRL */
3135 ret = xhci->dnctrl;
3136 break;
3137 case 0x18: /* CRCR low */
3138 ret = xhci->crcr_low & ~0xe;
3139 break;
3140 case 0x1c: /* CRCR high */
3141 ret = xhci->crcr_high;
3142 break;
3143 case 0x30: /* DCBAAP low */
3144 ret = xhci->dcbaap_low;
3145 break;
3146 case 0x34: /* DCBAAP high */
3147 ret = xhci->dcbaap_high;
3148 break;
3149 case 0x38: /* CONFIG */
3150 ret = xhci->config;
3151 break;
3152 default:
3153 trace_usb_xhci_unimplemented("oper read", reg);
3154 ret = 0;
3155 }
3156
3157 trace_usb_xhci_oper_read(reg, ret);
3158 return ret;
3159 }
3160
3161 static void xhci_oper_write(void *ptr, hwaddr reg,
3162 uint64_t val, unsigned size)
3163 {
3164 XHCIState *xhci = ptr;
3165 DeviceState *d = DEVICE(ptr);
3166
3167 trace_usb_xhci_oper_write(reg, val);
3168
3169 switch (reg) {
3170 case 0x00: /* USBCMD */
3171 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
3172 xhci_run(xhci);
3173 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
3174 xhci_stop(xhci);
3175 }
3176 if (val & USBCMD_CSS) {
3177 /* save state */
3178 xhci->usbsts &= ~USBSTS_SRE;
3179 }
3180 if (val & USBCMD_CRS) {
3181 /* restore state */
3182 xhci->usbsts |= USBSTS_SRE;
3183 }
3184 xhci->usbcmd = val & 0xc0f;
3185 xhci_mfwrap_update(xhci);
3186 if (val & USBCMD_HCRST) {
3187 xhci_reset(d);
3188 }
3189 xhci_intx_update(xhci);
3190 break;
3191
3192 case 0x04: /* USBSTS */
3193 /* these bits are write-1-to-clear */
3194 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
3195 xhci_intx_update(xhci);
3196 break;
3197
3198 case 0x14: /* DNCTRL */
3199 xhci->dnctrl = val & 0xffff;
3200 break;
3201 case 0x18: /* CRCR low */
3202 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3203 break;
3204 case 0x1c: /* CRCR high */
3205 xhci->crcr_high = val;
3206 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3207 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3208 xhci->crcr_low &= ~CRCR_CRR;
3209 xhci_event(xhci, &event, 0);
3210 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3211 } else {
3212 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3213 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3214 }
3215 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3216 break;
3217 case 0x30: /* DCBAAP low */
3218 xhci->dcbaap_low = val & 0xffffffc0;
3219 break;
3220 case 0x34: /* DCBAAP high */
3221 xhci->dcbaap_high = val;
3222 break;
3223 case 0x38: /* CONFIG */
3224 xhci->config = val & 0xff;
3225 break;
3226 default:
3227 trace_usb_xhci_unimplemented("oper write", reg);
3228 }
3229 }
3230
3231 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3232 unsigned size)
3233 {
3234 XHCIState *xhci = ptr;
3235 uint32_t ret = 0;
3236
3237 if (reg < 0x20) {
3238 switch (reg) {
3239 case 0x00: /* MFINDEX */
3240 ret = xhci_mfindex_get(xhci) & 0x3fff;
3241 break;
3242 default:
3243 trace_usb_xhci_unimplemented("runtime read", reg);
3244 break;
3245 }
3246 } else {
3247 int v = (reg - 0x20) / 0x20;
3248 XHCIInterrupter *intr = &xhci->intr[v];
3249 switch (reg & 0x1f) {
3250 case 0x00: /* IMAN */
3251 ret = intr->iman;
3252 break;
3253 case 0x04: /* IMOD */
3254 ret = intr->imod;
3255 break;
3256 case 0x08: /* ERSTSZ */
3257 ret = intr->erstsz;
3258 break;
3259 case 0x10: /* ERSTBA low */
3260 ret = intr->erstba_low;
3261 break;
3262 case 0x14: /* ERSTBA high */
3263 ret = intr->erstba_high;
3264 break;
3265 case 0x18: /* ERDP low */
3266 ret = intr->erdp_low;
3267 break;
3268 case 0x1c: /* ERDP high */
3269 ret = intr->erdp_high;
3270 break;
3271 }
3272 }
3273
3274 trace_usb_xhci_runtime_read(reg, ret);
3275 return ret;
3276 }
3277
3278 static void xhci_runtime_write(void *ptr, hwaddr reg,