2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/timer.h"
24 #include "qemu/module.h"
25 #include "qemu/queue.h"
26 #include "migration/vmstate.h"
27 #include "hw/qdev-properties.h"
29 #include "qapi/error.h"
37 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
39 #define DPRINTF(...) do {} while (0)
41 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
42 __func__, __LINE__, _msg); abort(); } while (0)
44 #define TRB_LINK_LIMIT 32
45 #define COMMAND_LIMIT 256
46 #define TRANSFER_LIMIT 256
49 #define LEN_OPER (0x400 + 0x10 * XHCI_MAXPORTS)
50 #define LEN_RUNTIME ((XHCI_MAXINTRS + 1) * 0x20)
51 #define LEN_DOORBELL ((XHCI_MAXSLOTS + 1) * 0x20)
53 #define OFF_OPER LEN_CAP
54 #define OFF_RUNTIME 0x1000
55 #define OFF_DOORBELL 0x2000
57 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
58 #error Increase OFF_RUNTIME
60 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
61 #error Increase OFF_DOORBELL
63 #if (OFF_DOORBELL + LEN_DOORBELL) > XHCI_LEN_REGS
64 # error Increase XHCI_LEN_REGS
68 #define USBCMD_RS (1<<0)
69 #define USBCMD_HCRST (1<<1)
70 #define USBCMD_INTE (1<<2)
71 #define USBCMD_HSEE (1<<3)
72 #define USBCMD_LHCRST (1<<7)
73 #define USBCMD_CSS (1<<8)
74 #define USBCMD_CRS (1<<9)
75 #define USBCMD_EWE (1<<10)
76 #define USBCMD_EU3S (1<<11)
78 #define USBSTS_HCH (1<<0)
79 #define USBSTS_HSE (1<<2)
80 #define USBSTS_EINT (1<<3)
81 #define USBSTS_PCD (1<<4)
82 #define USBSTS_SSS (1<<8)
83 #define USBSTS_RSS (1<<9)
84 #define USBSTS_SRE (1<<10)
85 #define USBSTS_CNR (1<<11)
86 #define USBSTS_HCE (1<<12)
89 #define PORTSC_CCS (1<<0)
90 #define PORTSC_PED (1<<1)
91 #define PORTSC_OCA (1<<3)
92 #define PORTSC_PR (1<<4)
93 #define PORTSC_PLS_SHIFT 5
94 #define PORTSC_PLS_MASK 0xf
95 #define PORTSC_PP (1<<9)
96 #define PORTSC_SPEED_SHIFT 10
97 #define PORTSC_SPEED_MASK 0xf
98 #define PORTSC_SPEED_FULL (1<<10)
99 #define PORTSC_SPEED_LOW (2<<10)
100 #define PORTSC_SPEED_HIGH (3<<10)
101 #define PORTSC_SPEED_SUPER (4<<10)
102 #define PORTSC_PIC_SHIFT 14
103 #define PORTSC_PIC_MASK 0x3
104 #define PORTSC_LWS (1<<16)
105 #define PORTSC_CSC (1<<17)
106 #define PORTSC_PEC (1<<18)
107 #define PORTSC_WRC (1<<19)
108 #define PORTSC_OCC (1<<20)
109 #define PORTSC_PRC (1<<21)
110 #define PORTSC_PLC (1<<22)
111 #define PORTSC_CEC (1<<23)
112 #define PORTSC_CAS (1<<24)
113 #define PORTSC_WCE (1<<25)
114 #define PORTSC_WDE (1<<26)
115 #define PORTSC_WOE (1<<27)
116 #define PORTSC_DR (1<<30)
117 #define PORTSC_WPR (1<<31)
119 #define CRCR_RCS (1<<0)
120 #define CRCR_CS (1<<1)
121 #define CRCR_CA (1<<2)
122 #define CRCR_CRR (1<<3)
124 #define IMAN_IP (1<<0)
125 #define IMAN_IE (1<<1)
127 #define ERDP_EHB (1<<3)
130 typedef struct XHCITRB
{
149 PLS_COMPILANCE_MODE
= 10,
154 #define CR_LINK TR_LINK
157 #define TRB_TYPE_SHIFT 10
158 #define TRB_TYPE_MASK 0x3f
159 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
161 #define TRB_EV_ED (1<<2)
163 #define TRB_TR_ENT (1<<1)
164 #define TRB_TR_ISP (1<<2)
165 #define TRB_TR_NS (1<<3)
166 #define TRB_TR_CH (1<<4)
167 #define TRB_TR_IOC (1<<5)
168 #define TRB_TR_IDT (1<<6)
169 #define TRB_TR_TBC_SHIFT 7
170 #define TRB_TR_TBC_MASK 0x3
171 #define TRB_TR_BEI (1<<9)
172 #define TRB_TR_TLBPC_SHIFT 16
173 #define TRB_TR_TLBPC_MASK 0xf
174 #define TRB_TR_FRAMEID_SHIFT 20
175 #define TRB_TR_FRAMEID_MASK 0x7ff
176 #define TRB_TR_SIA (1<<31)
178 #define TRB_TR_DIR (1<<16)
180 #define TRB_CR_SLOTID_SHIFT 24
181 #define TRB_CR_SLOTID_MASK 0xff
182 #define TRB_CR_EPID_SHIFT 16
183 #define TRB_CR_EPID_MASK 0x1f
185 #define TRB_CR_BSR (1<<9)
186 #define TRB_CR_DC (1<<9)
188 #define TRB_LK_TC (1<<1)
190 #define TRB_INTR_SHIFT 22
191 #define TRB_INTR_MASK 0x3ff
192 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
194 #define EP_TYPE_MASK 0x7
195 #define EP_TYPE_SHIFT 3
197 #define EP_STATE_MASK 0x7
198 #define EP_DISABLED (0<<0)
199 #define EP_RUNNING (1<<0)
200 #define EP_HALTED (2<<0)
201 #define EP_STOPPED (3<<0)
202 #define EP_ERROR (4<<0)
204 #define SLOT_STATE_MASK 0x1f
205 #define SLOT_STATE_SHIFT 27
206 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
207 #define SLOT_ENABLED 0
208 #define SLOT_DEFAULT 1
209 #define SLOT_ADDRESSED 2
210 #define SLOT_CONFIGURED 3
212 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
213 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
215 #define get_field(data, field) \
216 (((data) >> field##_SHIFT) & field##_MASK)
218 #define set_field(data, newval, field) do { \
219 uint32_t val = *data; \
220 val &= ~(field##_MASK << field##_SHIFT); \
221 val |= ((newval) & field##_MASK) << field##_SHIFT; \
225 typedef enum EPType
{
236 typedef struct XHCITransfer
{
237 XHCIEPContext
*epctx
;
244 unsigned int iso_pkts
;
245 unsigned int streamid
;
250 unsigned int trb_count
;
256 unsigned int pktsize
;
257 unsigned int cur_pkt
;
259 uint64_t mfindex_kick
;
261 QTAILQ_ENTRY(XHCITransfer
) next
;
264 struct XHCIStreamContext
{
270 struct XHCIEPContext
{
277 QTAILQ_HEAD(, XHCITransfer
) transfers
;
281 unsigned int max_psize
;
283 uint32_t kick_active
;
286 unsigned int max_pstreams
;
288 unsigned int nr_pstreams
;
289 XHCIStreamContext
*pstreams
;
291 /* iso xfer scheduling */
292 unsigned int interval
;
293 int64_t mfindex_last
;
294 QEMUTimer
*kick_timer
;
297 typedef struct XHCIEvRingSeg
{
304 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
305 unsigned int epid
, unsigned int streamid
);
306 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
);
307 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
309 static void xhci_xfer_report(XHCITransfer
*xfer
);
310 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
311 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
312 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
);
314 static const char *TRBType_names
[] = {
315 [TRB_RESERVED
] = "TRB_RESERVED",
316 [TR_NORMAL
] = "TR_NORMAL",
317 [TR_SETUP
] = "TR_SETUP",
318 [TR_DATA
] = "TR_DATA",
319 [TR_STATUS
] = "TR_STATUS",
320 [TR_ISOCH
] = "TR_ISOCH",
321 [TR_LINK
] = "TR_LINK",
322 [TR_EVDATA
] = "TR_EVDATA",
323 [TR_NOOP
] = "TR_NOOP",
324 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
325 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
326 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
327 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
328 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
329 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
330 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
331 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
332 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
333 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
334 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
335 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
336 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
337 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
338 [CR_NOOP
] = "CR_NOOP",
339 [ER_TRANSFER
] = "ER_TRANSFER",
340 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
341 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
342 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
343 [ER_DOORBELL
] = "ER_DOORBELL",
344 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
345 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
346 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
347 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
348 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
351 static const char *TRBCCode_names
[] = {
352 [CC_INVALID
] = "CC_INVALID",
353 [CC_SUCCESS
] = "CC_SUCCESS",
354 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
355 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
356 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
357 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
358 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
359 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
360 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
361 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
362 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
363 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
364 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
365 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
366 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
367 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
368 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
369 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
370 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
371 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
372 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
373 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
374 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
375 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
376 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
377 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
378 [CC_STOPPED
] = "CC_STOPPED",
379 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
380 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
381 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
382 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
383 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
384 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
385 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
386 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
387 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
390 static const char *ep_state_names
[] = {
391 [EP_DISABLED
] = "disabled",
392 [EP_RUNNING
] = "running",
393 [EP_HALTED
] = "halted",
394 [EP_STOPPED
] = "stopped",
395 [EP_ERROR
] = "error",
398 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
400 if (index
>= llen
|| list
[index
] == NULL
) {
406 static const char *trb_name(XHCITRB
*trb
)
408 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
409 ARRAY_SIZE(TRBType_names
));
412 static const char *event_name(XHCIEvent
*event
)
414 return lookup_name(event
->ccode
, TRBCCode_names
,
415 ARRAY_SIZE(TRBCCode_names
));
418 static const char *ep_state_name(uint32_t state
)
420 return lookup_name(state
, ep_state_names
,
421 ARRAY_SIZE(ep_state_names
));
424 bool xhci_get_flag(XHCIState
*xhci
, enum xhci_flags bit
)
426 return xhci
->flags
& (1 << bit
);
429 void xhci_set_flag(XHCIState
*xhci
, enum xhci_flags bit
)
431 xhci
->flags
|= (1 << bit
);
434 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
436 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
437 return (now
- xhci
->mfindex_start
) / 125000;
440 static void xhci_mfwrap_update(XHCIState
*xhci
)
442 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
443 uint32_t mfindex
, left
;
446 if ((xhci
->usbcmd
& bits
) == bits
) {
447 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
448 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
449 left
= 0x4000 - mfindex
;
450 timer_mod(xhci
->mfwrap_timer
, now
+ left
* 125000);
452 timer_del(xhci
->mfwrap_timer
);
456 static void xhci_mfwrap_timer(void *opaque
)
458 XHCIState
*xhci
= opaque
;
459 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
461 xhci_event(xhci
, &wrap
, 0);
462 xhci_mfwrap_update(xhci
);
465 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
467 if (sizeof(dma_addr_t
) == 4) {
470 return low
| (((dma_addr_t
)high
<< 16) << 16);
474 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
476 if (sizeof(dma_addr_t
) == 4) {
477 return addr
& 0xffffffff;
483 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
484 uint32_t *buf
, size_t len
)
488 assert((len
% sizeof(uint32_t)) == 0);
490 dma_memory_read(xhci
->as
, addr
, buf
, len
);
492 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
493 buf
[i
] = le32_to_cpu(buf
[i
]);
497 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
498 uint32_t *buf
, size_t len
)
502 uint32_t n
= len
/ sizeof(uint32_t);
504 assert((len
% sizeof(uint32_t)) == 0);
505 assert(n
<= ARRAY_SIZE(tmp
));
507 for (i
= 0; i
< n
; i
++) {
508 tmp
[i
] = cpu_to_le32(buf
[i
]);
510 dma_memory_write(xhci
->as
, addr
, tmp
, len
);
513 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
520 switch (uport
->dev
->speed
) {
524 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
525 index
= uport
->index
+ xhci
->numports_3
;
527 index
= uport
->index
;
530 case USB_SPEED_SUPER
:
531 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
532 index
= uport
->index
;
534 index
= uport
->index
+ xhci
->numports_2
;
540 return &xhci
->ports
[index
];
543 static void xhci_intr_update(XHCIState
*xhci
, int v
)
548 if (xhci
->intr
[0].iman
& IMAN_IP
&&
549 xhci
->intr
[0].iman
& IMAN_IE
&&
550 xhci
->usbcmd
& USBCMD_INTE
) {
553 if (xhci
->intr_raise
) {
554 xhci
->intr_raise(xhci
, 0, level
);
557 if (xhci
->intr_update
) {
558 xhci
->intr_update(xhci
, v
,
559 xhci
->intr
[v
].iman
& IMAN_IE
);
563 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
565 bool pending
= (xhci
->intr
[v
].erdp_low
& ERDP_EHB
);
567 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
568 xhci
->intr
[v
].iman
|= IMAN_IP
;
569 xhci
->usbsts
|= USBSTS_EINT
;
574 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
578 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
581 if (xhci
->intr_raise
) {
582 xhci
->intr_raise(xhci
, v
, true);
586 static inline int xhci_running(XHCIState
*xhci
)
588 return !(xhci
->usbsts
& USBSTS_HCH
);
591 static void xhci_die(XHCIState
*xhci
)
593 xhci
->usbsts
|= USBSTS_HCE
;
594 DPRINTF("xhci: asserted controller error\n");
597 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
599 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
603 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
604 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
605 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
606 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
608 ev_trb
.control
|= TRB_C
;
610 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
612 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
613 event_name(event
), ev_trb
.parameter
,
614 ev_trb
.status
, ev_trb
.control
);
616 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
617 dma_memory_write(xhci
->as
, addr
, &ev_trb
, TRB_SIZE
);
620 if (intr
->er_ep_idx
>= intr
->er_size
) {
622 intr
->er_pcs
= !intr
->er_pcs
;
626 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
628 XHCIInterrupter
*intr
;
632 if (v
>= xhci
->numintrs
) {
633 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
636 intr
= &xhci
->intr
[v
];
638 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
639 if (erdp
< intr
->er_start
||
640 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
641 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
642 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
643 v
, intr
->er_start
, intr
->er_size
);
648 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
649 assert(dp_idx
< intr
->er_size
);
651 if ((intr
->er_ep_idx
+ 2) % intr
->er_size
== dp_idx
) {
652 DPRINTF("xhci: ER %d full, send ring full error\n", v
);
653 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
654 xhci_write_event(xhci
, &full
, v
);
655 } else if ((intr
->er_ep_idx
+ 1) % intr
->er_size
== dp_idx
) {
656 DPRINTF("xhci: ER %d full, drop event\n", v
);
658 xhci_write_event(xhci
, event
, v
);
661 xhci_intr_raise(xhci
, v
);
664 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
667 ring
->dequeue
= base
;
671 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
674 uint32_t link_cnt
= 0;
678 dma_memory_read(xhci
->as
, ring
->dequeue
, trb
, TRB_SIZE
);
679 trb
->addr
= ring
->dequeue
;
680 trb
->ccs
= ring
->ccs
;
681 le64_to_cpus(&trb
->parameter
);
682 le32_to_cpus(&trb
->status
);
683 le32_to_cpus(&trb
->control
);
685 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
686 trb
->parameter
, trb
->status
, trb
->control
);
688 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
692 type
= TRB_TYPE(*trb
);
694 if (type
!= TR_LINK
) {
696 *addr
= ring
->dequeue
;
698 ring
->dequeue
+= TRB_SIZE
;
701 if (++link_cnt
> TRB_LINK_LIMIT
) {
702 trace_usb_xhci_enforced_limit("trb-link");
705 ring
->dequeue
= xhci_mask64(trb
->parameter
);
706 if (trb
->control
& TRB_LK_TC
) {
707 ring
->ccs
= !ring
->ccs
;
713 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
717 dma_addr_t dequeue
= ring
->dequeue
;
718 bool ccs
= ring
->ccs
;
719 /* hack to bundle together the two/three TDs that make a setup transfer */
720 bool control_td_set
= 0;
721 uint32_t link_cnt
= 0;
725 dma_memory_read(xhci
->as
, dequeue
, &trb
, TRB_SIZE
);
726 le64_to_cpus(&trb
.parameter
);
727 le32_to_cpus(&trb
.status
);
728 le32_to_cpus(&trb
.control
);
730 if ((trb
.control
& TRB_C
) != ccs
) {
734 type
= TRB_TYPE(trb
);
736 if (type
== TR_LINK
) {
737 if (++link_cnt
> TRB_LINK_LIMIT
) {
740 dequeue
= xhci_mask64(trb
.parameter
);
741 if (trb
.control
& TRB_LK_TC
) {
750 if (type
== TR_SETUP
) {
752 } else if (type
== TR_STATUS
) {
756 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
762 static void xhci_er_reset(XHCIState
*xhci
, int v
)
764 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
766 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
768 if (intr
->erstsz
== 0 || erstba
== 0) {
774 /* cache the (sole) event ring segment location */
775 if (intr
->erstsz
!= 1) {
776 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
780 dma_memory_read(xhci
->as
, erstba
, &seg
, sizeof(seg
));
781 le32_to_cpus(&seg
.addr_low
);
782 le32_to_cpus(&seg
.addr_high
);
783 le32_to_cpus(&seg
.size
);
784 if (seg
.size
< 16 || seg
.size
> 4096) {
785 DPRINTF("xhci: invalid value for segment size: %d\n", seg
.size
);
789 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
790 intr
->er_size
= seg
.size
;
795 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
796 v
, intr
->er_start
, intr
->er_size
);
799 static void xhci_run(XHCIState
*xhci
)
801 trace_usb_xhci_run();
802 xhci
->usbsts
&= ~USBSTS_HCH
;
803 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
806 static void xhci_stop(XHCIState
*xhci
)
808 trace_usb_xhci_stop();
809 xhci
->usbsts
|= USBSTS_HCH
;
810 xhci
->crcr_low
&= ~CRCR_CRR
;
813 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
816 XHCIStreamContext
*stctx
;
819 stctx
= g_new0(XHCIStreamContext
, count
);
820 for (i
= 0; i
< count
; i
++) {
821 stctx
[i
].pctx
= base
+ i
* 16;
827 static void xhci_reset_streams(XHCIEPContext
*epctx
)
831 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
832 epctx
->pstreams
[i
].sct
= -1;
836 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
838 assert(epctx
->pstreams
== NULL
);
839 epctx
->nr_pstreams
= 2 << epctx
->max_pstreams
;
840 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
843 static void xhci_free_streams(XHCIEPContext
*epctx
)
845 assert(epctx
->pstreams
!= NULL
);
847 g_free(epctx
->pstreams
);
848 epctx
->pstreams
= NULL
;
849 epctx
->nr_pstreams
= 0;
852 static int xhci_epmask_to_eps_with_streams(XHCIState
*xhci
,
855 XHCIEPContext
**epctxs
,
859 XHCIEPContext
*epctx
;
863 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
865 slot
= &xhci
->slots
[slotid
- 1];
867 for (i
= 2, j
= 0; i
<= 31; i
++) {
868 if (!(epmask
& (1u << i
))) {
872 epctx
= slot
->eps
[i
- 1];
873 ep
= xhci_epid_to_usbep(epctx
);
874 if (!epctx
|| !epctx
->nr_pstreams
|| !ep
) {
886 static void xhci_free_device_streams(XHCIState
*xhci
, unsigned int slotid
,
889 USBEndpoint
*eps
[30];
892 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, NULL
, eps
);
894 usb_device_free_streams(eps
[0]->dev
, eps
, nr_eps
);
898 static TRBCCode
xhci_alloc_device_streams(XHCIState
*xhci
, unsigned int slotid
,
901 XHCIEPContext
*epctxs
[30];
902 USBEndpoint
*eps
[30];
903 int i
, r
, nr_eps
, req_nr_streams
, dev_max_streams
;
905 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, epctxs
,
911 req_nr_streams
= epctxs
[0]->nr_pstreams
;
912 dev_max_streams
= eps
[0]->max_streams
;
914 for (i
= 1; i
< nr_eps
; i
++) {
916 * HdG: I don't expect these to ever trigger, but if they do we need
917 * to come up with another solution, ie group identical endpoints
918 * together and make an usb_device_alloc_streams call per group.
920 if (epctxs
[i
]->nr_pstreams
!= req_nr_streams
) {
921 FIXME("guest streams config not identical for all eps");
922 return CC_RESOURCE_ERROR
;
924 if (eps
[i
]->max_streams
!= dev_max_streams
) {
925 FIXME("device streams config not identical for all eps");
926 return CC_RESOURCE_ERROR
;
931 * max-streams in both the device descriptor and in the controller is a
932 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
933 * streams the guest will ask for 5 rounded up to the next power of 2 which
934 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
936 * For redirected devices however this is an issue, as there we must ask
937 * the real xhci controller to alloc streams, and the host driver for the
938 * real xhci controller will likely disallow allocating more streams then
939 * the device can handle.
941 * So we limit the requested nr_streams to the maximum number the device
944 if (req_nr_streams
> dev_max_streams
) {
945 req_nr_streams
= dev_max_streams
;
948 r
= usb_device_alloc_streams(eps
[0]->dev
, eps
, nr_eps
, req_nr_streams
);
950 DPRINTF("xhci: alloc streams failed\n");
951 return CC_RESOURCE_ERROR
;
957 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
958 unsigned int streamid
,
961 XHCIStreamContext
*sctx
;
963 uint32_t ctx
[2], sct
;
965 assert(streamid
!= 0);
967 if (streamid
>= epctx
->nr_pstreams
) {
968 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
971 sctx
= epctx
->pstreams
+ streamid
;
973 FIXME("secondary streams not implemented yet");
976 if (sctx
->sct
== -1) {
977 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
978 sct
= (ctx
[0] >> 1) & 0x07;
979 if (epctx
->lsa
&& sct
!= 1) {
980 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
984 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
985 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
990 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
991 XHCIStreamContext
*sctx
, uint32_t state
)
993 XHCIRing
*ring
= NULL
;
997 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
998 ctx
[0] &= ~EP_STATE_MASK
;
1001 /* update ring dequeue ptr */
1002 if (epctx
->nr_pstreams
) {
1005 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1007 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1008 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1009 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1012 ring
= &epctx
->ring
;
1015 ctx
[2] = ring
->dequeue
| ring
->ccs
;
1016 ctx
[3] = (ring
->dequeue
>> 16) >> 16;
1018 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1019 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1022 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1023 if (epctx
->state
!= state
) {
1024 trace_usb_xhci_ep_state(epctx
->slotid
, epctx
->epid
,
1025 ep_state_name(epctx
->state
),
1026 ep_state_name(state
));
1028 epctx
->state
= state
;
1031 static void xhci_ep_kick_timer(void *opaque
)
1033 XHCIEPContext
*epctx
= opaque
;
1034 xhci_kick_epctx(epctx
, 0);
1037 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1038 unsigned int slotid
,
1041 XHCIEPContext
*epctx
;
1043 epctx
= g_new0(XHCIEPContext
, 1);
1045 epctx
->slotid
= slotid
;
1048 QTAILQ_INIT(&epctx
->transfers
);
1049 epctx
->kick_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_ep_kick_timer
, epctx
);
1054 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1055 dma_addr_t pctx
, uint32_t *ctx
)
1059 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1061 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1063 epctx
->max_psize
= ctx
[1]>>16;
1064 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1065 epctx
->max_pstreams
= (ctx
[0] >> 10) & epctx
->xhci
->max_pstreams_mask
;
1066 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1067 if (epctx
->max_pstreams
) {
1068 xhci_alloc_streams(epctx
, dequeue
);
1070 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1071 epctx
->ring
.ccs
= ctx
[2] & 1;
1074 epctx
->interval
= 1 << ((ctx
[0] >> 16) & 0xff);
1077 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1078 unsigned int epid
, dma_addr_t pctx
,
1082 XHCIEPContext
*epctx
;
1084 trace_usb_xhci_ep_enable(slotid
, epid
);
1085 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1086 assert(epid
>= 1 && epid
<= 31);
1088 slot
= &xhci
->slots
[slotid
-1];
1089 if (slot
->eps
[epid
-1]) {
1090 xhci_disable_ep(xhci
, slotid
, epid
);
1093 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1094 slot
->eps
[epid
-1] = epctx
;
1095 xhci_init_epctx(epctx
, pctx
, ctx
);
1097 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1098 "size is %d\n", epid
/2, epid
%2, epctx
->type
, epctx
->max_psize
);
1100 epctx
->mfindex_last
= 0;
1102 epctx
->state
= EP_RUNNING
;
1103 ctx
[0] &= ~EP_STATE_MASK
;
1104 ctx
[0] |= EP_RUNNING
;
1109 static XHCITransfer
*xhci_ep_alloc_xfer(XHCIEPContext
*epctx
,
1112 uint32_t limit
= epctx
->nr_pstreams
+ 16;
1115 if (epctx
->xfer_count
>= limit
) {
1119 xfer
= g_new0(XHCITransfer
, 1);
1120 xfer
->epctx
= epctx
;
1121 xfer
->trbs
= g_new(XHCITRB
, length
);
1122 xfer
->trb_count
= length
;
1123 usb_packet_init(&xfer
->packet
);
1125 QTAILQ_INSERT_TAIL(&epctx
->transfers
, xfer
, next
);
1126 epctx
->xfer_count
++;
1131 static void xhci_ep_free_xfer(XHCITransfer
*xfer
)
1133 QTAILQ_REMOVE(&xfer
->epctx
->transfers
, xfer
, next
);
1134 xfer
->epctx
->xfer_count
--;
1136 usb_packet_cleanup(&xfer
->packet
);
1141 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
, TRBCCode report
)
1145 if (report
&& (t
->running_async
|| t
->running_retry
)) {
1147 xhci_xfer_report(t
);
1150 if (t
->running_async
) {
1151 usb_cancel_packet(&t
->packet
);
1152 t
->running_async
= 0;
1155 if (t
->running_retry
) {
1157 t
->epctx
->retry
= NULL
;
1158 timer_del(t
->epctx
->kick_timer
);
1160 t
->running_retry
= 0;
1171 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1172 unsigned int epid
, TRBCCode report
)
1175 XHCIEPContext
*epctx
;
1178 USBEndpoint
*ep
= NULL
;
1179 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1180 assert(epid
>= 1 && epid
<= 31);
1182 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1184 slot
= &xhci
->slots
[slotid
-1];
1186 if (!slot
->eps
[epid
-1]) {
1190 epctx
= slot
->eps
[epid
-1];
1193 xfer
= QTAILQ_FIRST(&epctx
->transfers
);
1197 killed
+= xhci_ep_nuke_one_xfer(xfer
, report
);
1199 report
= 0; /* Only report once */
1201 xhci_ep_free_xfer(xfer
);
1204 ep
= xhci_epid_to_usbep(epctx
);
1206 usb_device_ep_stopped(ep
->dev
, ep
);
1211 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1215 XHCIEPContext
*epctx
;
1217 trace_usb_xhci_ep_disable(slotid
, epid
);
1218 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1219 assert(epid
>= 1 && epid
<= 31);
1221 slot
= &xhci
->slots
[slotid
-1];
1223 if (!slot
->eps
[epid
-1]) {
1224 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1228 xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0);
1230 epctx
= slot
->eps
[epid
-1];
1232 if (epctx
->nr_pstreams
) {
1233 xhci_free_streams(epctx
);
1236 /* only touch guest RAM if we're not resetting the HC */
1237 if (xhci
->dcbaap_low
|| xhci
->dcbaap_high
) {
1238 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1241 timer_free(epctx
->kick_timer
);
1243 slot
->eps
[epid
-1] = NULL
;
1248 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1252 XHCIEPContext
*epctx
;
1254 trace_usb_xhci_ep_stop(slotid
, epid
);
1255 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1257 if (epid
< 1 || epid
> 31) {
1258 DPRINTF("xhci: bad ep %d\n", epid
);
1259 return CC_TRB_ERROR
;
1262 slot
= &xhci
->slots
[slotid
-1];
1264 if (!slot
->eps
[epid
-1]) {
1265 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1266 return CC_EP_NOT_ENABLED_ERROR
;
1269 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, CC_STOPPED
) > 0) {
1270 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1271 "data might be lost\n");
1274 epctx
= slot
->eps
[epid
-1];
1276 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1278 if (epctx
->nr_pstreams
) {
1279 xhci_reset_streams(epctx
);
1285 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1289 XHCIEPContext
*epctx
;
1291 trace_usb_xhci_ep_reset(slotid
, epid
);
1292 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1294 if (epid
< 1 || epid
> 31) {
1295 DPRINTF("xhci: bad ep %d\n", epid
);
1296 return CC_TRB_ERROR
;
1299 slot
= &xhci
->slots
[slotid
-1];
1301 if (!slot
->eps
[epid
-1]) {
1302 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1303 return CC_EP_NOT_ENABLED_ERROR
;
1306 epctx
= slot
->eps
[epid
-1];
1308 if (epctx
->state
!= EP_HALTED
) {
1309 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1310 epid
, epctx
->state
);
1311 return CC_CONTEXT_STATE_ERROR
;
1314 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0) > 0) {
1315 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1316 "data might be lost\n");
1319 if (!xhci
->slots
[slotid
-1].uport
||
1320 !xhci
->slots
[slotid
-1].uport
->dev
||
1321 !xhci
->slots
[slotid
-1].uport
->dev
->attached
) {
1322 return CC_USB_TRANSACTION_ERROR
;
1325 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1327 if (epctx
->nr_pstreams
) {
1328 xhci_reset_streams(epctx
);
1334 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1335 unsigned int epid
, unsigned int streamid
,
1339 XHCIEPContext
*epctx
;
1340 XHCIStreamContext
*sctx
;
1343 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1345 if (epid
< 1 || epid
> 31) {
1346 DPRINTF("xhci: bad ep %d\n", epid
);
1347 return CC_TRB_ERROR
;
1350 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1351 dequeue
= xhci_mask64(pdequeue
);
1353 slot
= &xhci
->slots
[slotid
-1];
1355 if (!slot
->eps
[epid
-1]) {
1356 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1357 return CC_EP_NOT_ENABLED_ERROR
;
1360 epctx
= slot
->eps
[epid
-1];
1362 if (epctx
->state
!= EP_STOPPED
) {
1363 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1364 return CC_CONTEXT_STATE_ERROR
;
1367 if (epctx
->nr_pstreams
) {
1369 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1373 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1374 sctx
->ring
.ccs
= dequeue
& 1;
1377 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1378 epctx
->ring
.ccs
= dequeue
& 1;
1381 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1386 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1388 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1391 xfer
->int_req
= false;
1392 qemu_sglist_init(&xfer
->sgl
, DEVICE(xhci
), xfer
->trb_count
, xhci
->as
);
1393 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1394 XHCITRB
*trb
= &xfer
->trbs
[i
];
1396 unsigned int chunk
= 0;
1398 if (trb
->control
& TRB_TR_IOC
) {
1399 xfer
->int_req
= true;
1402 switch (TRB_TYPE(*trb
)) {
1404 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1405 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1411 addr
= xhci_mask64(trb
->parameter
);
1412 chunk
= trb
->status
& 0x1ffff;
1413 if (trb
->control
& TRB_TR_IDT
) {
1414 if (chunk
> 8 || in_xfer
) {
1415 DPRINTF("xhci: invalid immediate data TRB\n");
1418 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1420 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1429 qemu_sglist_destroy(&xfer
->sgl
);
1434 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1436 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1437 qemu_sglist_destroy(&xfer
->sgl
);
1440 static void xhci_xfer_report(XHCITransfer
*xfer
)
1446 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1447 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1450 left
= xfer
->packet
.actual_length
;
1452 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1453 XHCITRB
*trb
= &xfer
->trbs
[i
];
1454 unsigned int chunk
= 0;
1456 switch (TRB_TYPE(*trb
)) {
1458 chunk
= trb
->status
& 0x1ffff;
1466 chunk
= trb
->status
& 0x1ffff;
1469 if (xfer
->status
== CC_SUCCESS
) {
1482 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1483 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1484 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1485 event
.slotid
= xfer
->epctx
->slotid
;
1486 event
.epid
= xfer
->epctx
->epid
;
1487 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1489 event
.ptr
= trb
->addr
;
1490 if (xfer
->status
== CC_SUCCESS
) {
1491 event
.ccode
= shortpkt ? CC_SHORT_PACKET
: CC_SUCCESS
;
1493 event
.ccode
= xfer
->status
;
1495 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1496 event
.ptr
= trb
->parameter
;
1497 event
.flags
|= TRB_EV_ED
;
1498 event
.length
= edtla
& 0xffffff;
1499 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1502 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1504 if (xfer
->status
!= CC_SUCCESS
) {
1509 switch (TRB_TYPE(*trb
)) {
1519 static void xhci_stall_ep(XHCITransfer
*xfer
)
1521 XHCIEPContext
*epctx
= xfer
->epctx
;
1522 XHCIState
*xhci
= epctx
->xhci
;
1524 XHCIStreamContext
*sctx
;
1526 if (epctx
->type
== ET_ISO_IN
|| epctx
->type
== ET_ISO_OUT
) {
1527 /* never halt isoch endpoints, 4.10.2 */
1531 if (epctx
->nr_pstreams
) {
1532 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1536 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1537 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1538 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1540 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1541 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1542 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1546 static int xhci_setup_packet(XHCITransfer
*xfer
)
1551 dir
= xfer
->in_xfer ? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1553 if (xfer
->packet
.ep
) {
1554 ep
= xfer
->packet
.ep
;
1556 ep
= xhci_epid_to_usbep(xfer
->epctx
);
1558 DPRINTF("xhci: slot %d has no device\n",
1559 xfer
->epctx
->slotid
);
1564 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1565 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1566 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1567 if (usb_packet_map(&xfer
->packet
, &xfer
->sgl
)) {
1568 qemu_sglist_destroy(&xfer
->sgl
);
1571 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1572 xfer
->packet
.pid
, ep
->dev
->addr
, ep
->nr
);
1576 static int xhci_try_complete_packet(XHCITransfer
*xfer
)
1578 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1579 trace_usb_xhci_xfer_async(xfer
);
1580 xfer
->running_async
= 1;
1581 xfer
->running_retry
= 0;
1584 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1585 trace_usb_xhci_xfer_nak(xfer
);
1586 xfer
->running_async
= 0;
1587 xfer
->running_retry
= 1;
1591 xfer
->running_async
= 0;
1592 xfer
->running_retry
= 0;
1594 xhci_xfer_unmap(xfer
);
1597 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1598 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1599 xfer
->status
= CC_SUCCESS
;
1600 xhci_xfer_report(xfer
);
1605 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1606 switch (xfer
->packet
.status
) {
1608 case USB_RET_IOERROR
:
1609 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1610 xhci_xfer_report(xfer
);
1611 xhci_stall_ep(xfer
);
1614 xfer
->status
= CC_STALL_ERROR
;
1615 xhci_xfer_report(xfer
);
1616 xhci_stall_ep(xfer
);
1618 case USB_RET_BABBLE
:
1619 xfer
->status
= CC_BABBLE_DETECTED
;
1620 xhci_xfer_report(xfer
);
1621 xhci_stall_ep(xfer
);
1624 DPRINTF("%s: FIXME: status = %d\n", __func__
,
1625 xfer
->packet
.status
);
1626 FIXME("unhandled USB_RET_*");
1631 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1633 XHCITRB
*trb_setup
, *trb_status
;
1634 uint8_t bmRequestType
;
1636 trb_setup
= &xfer
->trbs
[0];
1637 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1639 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1640 xfer
->epctx
->epid
, xfer
->streamid
);
1642 /* at most one Event Data TRB allowed after STATUS */
1643 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1647 /* do some sanity checks */
1648 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1649 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1650 TRB_TYPE(*trb_setup
));
1653 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1654 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1655 TRB_TYPE(*trb_status
));
1658 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1659 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1662 if ((trb_setup
->status
& 0x1ffff) != 8) {
1663 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1664 (trb_setup
->status
& 0x1ffff));
1668 bmRequestType
= trb_setup
->parameter
;
1670 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1671 xfer
->iso_xfer
= false;
1672 xfer
->timed_xfer
= false;
1674 if (xhci_setup_packet(xfer
) < 0) {
1677 xfer
->packet
.parameter
= trb_setup
->parameter
;
1679 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1680 xhci_try_complete_packet(xfer
);
1684 static void xhci_calc_intr_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1685 XHCIEPContext
*epctx
, uint64_t mfindex
)
1687 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1688 ~(epctx
->interval
-1));
1689 uint64_t kick
= epctx
->mfindex_last
+ epctx
->interval
;
1691 assert(epctx
->interval
!= 0);
1692 xfer
->mfindex_kick
= MAX(asap
, kick
);
1695 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1696 XHCIEPContext
*epctx
, uint64_t mfindex
)
1698 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1699 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1700 ~(epctx
->interval
-1));
1701 if (asap
>= epctx
->mfindex_last
&&
1702 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1703 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1705 xfer
->mfindex_kick
= asap
;
1708 xfer
->mfindex_kick
= ((xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1709 & TRB_TR_FRAMEID_MASK
) << 3;
1710 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1711 if (xfer
->mfindex_kick
+ 0x100 < mfindex
) {
1712 xfer
->mfindex_kick
+= 0x4000;
1717 static void xhci_check_intr_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1718 XHCIEPContext
*epctx
, uint64_t mfindex
)
1720 if (xfer
->mfindex_kick
> mfindex
) {
1721 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1722 (xfer
->mfindex_kick
- mfindex
) * 125000);
1723 xfer
->running_retry
= 1;
1725 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1726 timer_del(epctx
->kick_timer
);
1727 xfer
->running_retry
= 0;
1732 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1736 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx
->slotid
, epctx
->epid
);
1738 xfer
->in_xfer
= epctx
->type
>>2;
1740 switch(epctx
->type
) {
1744 xfer
->iso_xfer
= false;
1745 xfer
->timed_xfer
= true;
1746 mfindex
= xhci_mfindex_get(xhci
);
1747 xhci_calc_intr_kick(xhci
, xfer
, epctx
, mfindex
);
1748 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1749 if (xfer
->running_retry
) {
1756 xfer
->iso_xfer
= false;
1757 xfer
->timed_xfer
= false;
1762 xfer
->iso_xfer
= true;
1763 xfer
->timed_xfer
= true;
1764 mfindex
= xhci_mfindex_get(xhci
);
1765 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1766 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1767 if (xfer
->running_retry
) {
1772 trace_usb_xhci_unimplemented("endpoint type", epctx
->type
);
1776 if (xhci_setup_packet(xfer
) < 0) {
1779 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1780 xhci_try_complete_packet(xfer
);
1784 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1786 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1787 xfer
->epctx
->epid
, xfer
->streamid
);
1788 return xhci_submit(xhci
, xfer
, epctx
);
1791 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
1792 unsigned int epid
, unsigned int streamid
)
1794 XHCIEPContext
*epctx
;
1796 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1797 assert(epid
>= 1 && epid
<= 31);
1799 if (!xhci
->slots
[slotid
-1].enabled
) {
1800 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1803 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1805 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1810 if (epctx
->kick_active
) {
1813 xhci_kick_epctx(epctx
, streamid
);
1816 static bool xhci_slot_ok(XHCIState
*xhci
, int slotid
)
1818 return (xhci
->slots
[slotid
- 1].uport
&&
1819 xhci
->slots
[slotid
- 1].uport
->dev
&&
1820 xhci
->slots
[slotid
- 1].uport
->dev
->attached
);
1823 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
)
1825 XHCIState
*xhci
= epctx
->xhci
;
1826 XHCIStreamContext
*stctx
= NULL
;
1829 USBEndpoint
*ep
= NULL
;
1831 unsigned int count
= 0;
1835 trace_usb_xhci_ep_kick(epctx
->slotid
, epctx
->epid
, streamid
);
1836 assert(!epctx
->kick_active
);
1838 /* If the device has been detached, but the guest has not noticed this
1839 yet the 2 above checks will succeed, but we must NOT continue */
1840 if (!xhci_slot_ok(xhci
, epctx
->slotid
)) {
1845 XHCITransfer
*xfer
= epctx
->retry
;
1847 trace_usb_xhci_xfer_retry(xfer
);
1848 assert(xfer
->running_retry
);
1849 if (xfer
->timed_xfer
) {
1850 /* time to kick the transfer? */
1851 mfindex
= xhci_mfindex_get(xhci
);
1852 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1853 if (xfer
->running_retry
) {
1856 xfer
->timed_xfer
= 0;
1857 xfer
->running_retry
= 1;
1859 if (xfer
->iso_xfer
) {
1860 /* retry iso transfer */
1861 if (xhci_setup_packet(xfer
) < 0) {
1864 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1865 assert(xfer
->packet
.status
!= USB_RET_NAK
);
1866 xhci_try_complete_packet(xfer
);
1868 /* retry nak'ed transfer */
1869 if (xhci_setup_packet(xfer
) < 0) {
1872 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1873 if (xfer
->packet
.status
== USB_RET_NAK
) {
1874 xhci_xfer_unmap(xfer
);
1877 xhci_try_complete_packet(xfer
);
1879 assert(!xfer
->running_retry
);
1880 if (xfer
->complete
) {
1881 /* update ring dequeue ptr */
1882 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1883 xhci_ep_free_xfer(epctx
->retry
);
1885 epctx
->retry
= NULL
;
1888 if (epctx
->state
== EP_HALTED
) {
1889 DPRINTF("xhci: ep halted, not running schedule\n");
1894 if (epctx
->nr_pstreams
) {
1896 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
1897 if (stctx
== NULL
) {
1900 ring
= &stctx
->ring
;
1901 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
1903 ring
= &epctx
->ring
;
1905 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
1907 assert(ring
->dequeue
!= 0);
1909 epctx
->kick_active
++;
1911 length
= xhci_ring_chain_length(xhci
, ring
);
1913 if (epctx
->type
== ET_ISO_OUT
|| epctx
->type
== ET_ISO_IN
) {
1915 XHCIEvent ev
= { ER_TRANSFER
};
1916 ev
.ccode
= epctx
->type
== ET_ISO_IN ?
1917 CC_RING_OVERRUN
: CC_RING_UNDERRUN
;
1918 ev
.slotid
= epctx
->slotid
;
1919 ev
.epid
= epctx
->epid
;
1920 ev
.ptr
= epctx
->ring
.dequeue
;
1921 xhci_event(xhci
, &ev
, xhci
->slots
[epctx
->slotid
-1].intr
);
1925 xfer
= xhci_ep_alloc_xfer(epctx
, length
);
1930 for (i
= 0; i
< length
; i
++) {
1932 type
= xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
);
1935 xhci_ep_free_xfer(xfer
);
1936 epctx
->kick_active
--;
1940 xfer
->streamid
= streamid
;
1942 if (epctx
->epid
== 1) {
1943 xhci_fire_ctl_transfer(xhci
, xfer
);
1945 xhci_fire_transfer(xhci
, xfer
, epctx
);
1947 if (!xhci_slot_ok(xhci
, epctx
->slotid
)) {
1948 /* surprise removal -> stop processing */
1951 if (xfer
->complete
) {
1952 /* update ring dequeue ptr */
1953 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1954 xhci_ep_free_xfer(xfer
);
1958 if (epctx
->state
== EP_HALTED
) {
1961 if (xfer
!= NULL
&& xfer
->running_retry
) {
1962 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1963 epctx
->retry
= xfer
;
1964 xhci_xfer_unmap(xfer
);
1967 if (count
++ > TRANSFER_LIMIT
) {
1968 trace_usb_xhci_enforced_limit("transfers");
1972 epctx
->kick_active
--;
1974 ep
= xhci_epid_to_usbep(epctx
);
1976 usb_device_flush_ep_queue(ep
->dev
, ep
);
1980 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
1982 trace_usb_xhci_slot_enable(slotid
);
1983 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1984 xhci
->slots
[slotid
-1].enabled
= 1;
1985 xhci
->slots
[slotid
-1].uport
= NULL
;
1986 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
1991 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
1995 trace_usb_xhci_slot_disable(slotid
);
1996 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1998 for (i
= 1; i
<= 31; i
++) {
1999 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2000 xhci_disable_ep(xhci
, slotid
, i
);
2004 xhci
->slots
[slotid
-1].enabled
= 0;
2005 xhci
->slots
[slotid
-1].addressed
= 0;
2006 xhci
->slots
[slotid
-1].uport
= NULL
;
2007 xhci
->slots
[slotid
-1].intr
= 0;
2011 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2017 port
= (slot_ctx
[1]>>16) & 0xFF;
2018 if (port
< 1 || port
> xhci
->numports
) {
2021 port
= xhci
->ports
[port
-1].uport
->index
+1;
2022 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2023 for (i
= 0; i
< 5; i
++) {
2024 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2028 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2031 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2032 if (strcmp(uport
->path
, path
) == 0) {
2039 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2040 uint64_t pictx
, bool bsr
)
2045 dma_addr_t ictx
, octx
, dcbaap
;
2047 uint32_t ictl_ctx
[2];
2048 uint32_t slot_ctx
[4];
2049 uint32_t ep0_ctx
[5];
2053 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2055 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2056 poctx
= ldq_le_dma(xhci
->as
, dcbaap
+ 8 * slotid
);
2057 ictx
= xhci_mask64(pictx
);
2058 octx
= xhci_mask64(poctx
);
2060 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2061 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2063 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2065 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2066 DPRINTF("xhci: invalid input context control %08x %08x\n",
2067 ictl_ctx
[0], ictl_ctx
[1]);
2068 return CC_TRB_ERROR
;
2071 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2072 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2074 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2075 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2077 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2078 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2080 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2081 if (uport
== NULL
) {
2082 DPRINTF("xhci: port not found\n");
2083 return CC_TRB_ERROR
;
2085 trace_usb_xhci_slot_address(slotid
, uport
->path
);
2088 if (!dev
|| !dev
->attached
) {
2089 DPRINTF("xhci: port %s not connected\n", uport
->path
);
2090 return CC_USB_TRANSACTION_ERROR
;
2093 for (i
= 0; i
< xhci
->numslots
; i
++) {
2094 if (i
== slotid
-1) {
2097 if (xhci
->slots
[i
].uport
== uport
) {
2098 DPRINTF("xhci: port %s already assigned to slot %d\n",
2100 return CC_TRB_ERROR
;
2104 slot
= &xhci
->slots
[slotid
-1];
2105 slot
->uport
= uport
;
2107 slot
->intr
= get_field(slot_ctx
[2], TRB_INTR
);
2109 /* Make sure device is in USB_STATE_DEFAULT state */
2110 usb_device_reset(dev
);
2112 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2117 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2118 memset(&p
, 0, sizeof(p
));
2119 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2120 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2121 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2123 usb_device_handle_control(dev
, &p
,
2124 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2125 slotid
, 0, 0, NULL
);
2126 assert(p
.status
!= USB_RET_ASYNC
);
2127 usb_packet_cleanup(&p
);
2130 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2132 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2133 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2134 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2135 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2137 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2138 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2140 xhci
->slots
[slotid
-1].addressed
= 1;
2145 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2146 uint64_t pictx
, bool dc
)
2148 dma_addr_t ictx
, octx
;
2149 uint32_t ictl_ctx
[2];
2150 uint32_t slot_ctx
[4];
2151 uint32_t islot_ctx
[4];
2156 trace_usb_xhci_slot_configure(slotid
);
2157 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2159 ictx
= xhci_mask64(pictx
);
2160 octx
= xhci
->slots
[slotid
-1].ctx
;
2162 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2163 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2166 for (i
= 2; i
<= 31; i
++) {
2167 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2168 xhci_disable_ep(xhci
, slotid
, i
);
2172 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2173 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2174 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2175 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2176 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2177 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2182 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2184 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2185 DPRINTF("xhci: invalid input context control %08x %08x\n",
2186 ictl_ctx
[0], ictl_ctx
[1]);
2187 return CC_TRB_ERROR
;
2190 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2191 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2193 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2194 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx
[3]);
2195 return CC_CONTEXT_STATE_ERROR
;
2198 xhci_free_device_streams(xhci
, slotid
, ictl_ctx
[0] | ictl_ctx
[1]);
2200 for (i
= 2; i
<= 31; i
++) {
2201 if (ictl_ctx
[0] & (1<<i
)) {
2202 xhci_disable_ep(xhci
, slotid
, i
);
2204 if (ictl_ctx
[1] & (1<<i
)) {
2205 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2206 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2207 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2208 ep_ctx
[3], ep_ctx
[4]);
2209 xhci_disable_ep(xhci
, slotid
, i
);
2210 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2211 if (res
!= CC_SUCCESS
) {
2214 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2215 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2216 ep_ctx
[3], ep_ctx
[4]);
2217 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2221 res
= xhci_alloc_device_streams(xhci
, slotid
, ictl_ctx
[1]);
2222 if (res
!= CC_SUCCESS
) {
2223 for (i
= 2; i
<= 31; i
++) {
2224 if (ictl_ctx
[1] & (1u << i
)) {
2225 xhci_disable_ep(xhci
, slotid
, i
);
2231 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2232 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2233 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2234 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2235 SLOT_CONTEXT_ENTRIES_SHIFT
);
2236 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2237 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2239 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2245 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2248 dma_addr_t ictx
, octx
;
2249 uint32_t ictl_ctx
[2];
2250 uint32_t iep0_ctx
[5];
2251 uint32_t ep0_ctx
[5];
2252 uint32_t islot_ctx
[4];
2253 uint32_t slot_ctx
[4];
2255 trace_usb_xhci_slot_evaluate(slotid
);
2256 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2258 ictx
= xhci_mask64(pictx
);
2259 octx
= xhci
->slots
[slotid
-1].ctx
;
2261 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2262 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2264 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2266 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2267 DPRINTF("xhci: invalid input context control %08x %08x\n",
2268 ictl_ctx
[0], ictl_ctx
[1]);
2269 return CC_TRB_ERROR
;
2272 if (ictl_ctx
[1] & 0x1) {
2273 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2275 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2276 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2278 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2280 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2281 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2282 /* update interrupter target field */
2283 xhci
->slots
[slotid
-1].intr
= get_field(islot_ctx
[2], TRB_INTR
);
2284 set_field(&slot_ctx
[2], xhci
->slots
[slotid
-1].intr
, TRB_INTR
);
2286 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2287 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2289 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2292 if (ictl_ctx
[1] & 0x2) {
2293 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2295 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2296 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2297 iep0_ctx
[3], iep0_ctx
[4]);
2299 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2301 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2302 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2304 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2305 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2307 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2313 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2315 uint32_t slot_ctx
[4];
2319 trace_usb_xhci_slot_reset(slotid
);
2320 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2322 octx
= xhci
->slots
[slotid
-1].ctx
;
2324 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2326 for (i
= 2; i
<= 31; i
++) {
2327 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2328 xhci_disable_ep(xhci
, slotid
, i
);
2332 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2333 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2334 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2335 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2336 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2337 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2342 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2344 unsigned int slotid
;
2345 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2346 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2347 DPRINTF("xhci: bad slot id %d\n", slotid
);
2348 event
->ccode
= CC_TRB_ERROR
;
2350 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2351 DPRINTF("xhci: slot id %d not enabled\n", slotid
);
2352 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2358 /* cleanup slot state on usb device detach */
2359 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2363 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2364 if (xhci
->slots
[slot
].uport
== uport
) {
2368 if (slot
== xhci
->numslots
) {
2372 for (ep
= 0; ep
< 31; ep
++) {
2373 if (xhci
->slots
[slot
].eps
[ep
]) {
2374 xhci_ep_nuke_xfers(xhci
, slot
+ 1, ep
+ 1, 0);
2377 xhci
->slots
[slot
].uport
= NULL
;
2380 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2383 uint8_t bw_ctx
[xhci
->numports
+1];
2385 DPRINTF("xhci_get_port_bandwidth()\n");
2387 ctx
= xhci_mask64(pctx
);
2389 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2391 /* TODO: actually implement real values here */
2393 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2394 dma_memory_write(xhci
->as
, ctx
, bw_ctx
, sizeof(bw_ctx
));
2399 static uint32_t rotl(uint32_t v
, unsigned count
)
2402 return (v
<< count
) | (v
>> (32 - count
));
2406 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2409 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2410 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2411 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2415 static void xhci_process_commands(XHCIState
*xhci
)
2419 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2421 unsigned int i
, slotid
= 0, count
= 0;
2423 DPRINTF("xhci_process_commands()\n");
2424 if (!xhci_running(xhci
)) {
2425 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2429 xhci
->crcr_low
|= CRCR_CRR
;
2431 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2434 case CR_ENABLE_SLOT
:
2435 for (i
= 0; i
< xhci
->numslots
; i
++) {
2436 if (!xhci
->slots
[i
].enabled
) {
2440 if (i
>= xhci
->numslots
) {
2441 DPRINTF("xhci: no device slots available\n");
2442 event
.ccode
= CC_NO_SLOTS_ERROR
;
2445 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2448 case CR_DISABLE_SLOT
:
2449 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2451 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2454 case CR_ADDRESS_DEVICE
:
2455 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2457 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2458 trb
.control
& TRB_CR_BSR
);
2461 case CR_CONFIGURE_ENDPOINT
:
2462 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2464 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2465 trb
.control
& TRB_CR_DC
);
2468 case CR_EVALUATE_CONTEXT
:
2469 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2471 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2474 case CR_STOP_ENDPOINT
:
2475 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2477 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2479 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2482 case CR_RESET_ENDPOINT
:
2483 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2485 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2487 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2490 case CR_SET_TR_DEQUEUE
:
2491 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2493 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2495 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2496 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2501 case CR_RESET_DEVICE
:
2502 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2504 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2507 case CR_GET_PORT_BANDWIDTH
:
2508 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2511 event
.ccode
= CC_SUCCESS
;
2513 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2514 if (xhci
->nec_quirks
) {
2515 event
.type
= 48; /* NEC reply */
2516 event
.length
= 0x3025;
2518 event
.ccode
= CC_TRB_ERROR
;
2521 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2522 if (xhci
->nec_quirks
) {
2523 uint32_t chi
= trb
.parameter
>> 32;
2524 uint32_t clo
= trb
.parameter
;
2525 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2526 event
.length
= val
& 0xFFFF;
2527 event
.epid
= val
>> 16;
2529 event
.type
= 48; /* NEC reply */
2531 event
.ccode
= CC_TRB_ERROR
;
2535 trace_usb_xhci_unimplemented("command", type
);
2536 event
.ccode
= CC_TRB_ERROR
;
2539 event
.slotid
= slotid
;
2540 xhci_event(xhci
, &event
, 0);
2542 if (count
++ > COMMAND_LIMIT
) {
2543 trace_usb_xhci_enforced_limit("commands");
2549 static bool xhci_port_have_device(XHCIPort
*port
)
2551 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2552 return false; /* no device present */
2554 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2555 return false; /* speed mismatch */
2560 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2562 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2563 port
->portnr
<< 24 };
2565 if ((port
->portsc
& bits
) == bits
) {
2568 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2569 port
->portsc
|= bits
;
2570 if (!xhci_running(port
->xhci
)) {
2573 xhci_event(port
->xhci
, &ev
, 0);
2576 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2578 uint32_t pls
= PLS_RX_DETECT
;
2581 port
->portsc
= PORTSC_PP
;
2582 if (!is_detach
&& xhci_port_have_device(port
)) {
2583 port
->portsc
|= PORTSC_CCS
;
2584 switch (port
->uport
->dev
->speed
) {
2586 port
->portsc
|= PORTSC_SPEED_LOW
;
2589 case USB_SPEED_FULL
:
2590 port
->portsc
|= PORTSC_SPEED_FULL
;
2593 case USB_SPEED_HIGH
:
2594 port
->portsc
|= PORTSC_SPEED_HIGH
;
2597 case USB_SPEED_SUPER
:
2598 port
->portsc
|= PORTSC_SPEED_SUPER
;
2599 port
->portsc
|= PORTSC_PED
;
2604 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2605 trace_usb_xhci_port_link(port
->portnr
, pls
);
2606 xhci_port_notify(port
, PORTSC_CSC
);
2609 static void xhci_port_reset(XHCIPort
*port
, bool warm_reset
)
2611 trace_usb_xhci_port_reset(port
->portnr
, warm_reset
);
2613 if (!xhci_port_have_device(port
)) {
2617 usb_device_reset(port
->uport
->dev
);
2619 switch (port
->uport
->dev
->speed
) {
2620 case USB_SPEED_SUPER
:
2622 port
->portsc
|= PORTSC_WRC
;
2626 case USB_SPEED_FULL
:
2627 case USB_SPEED_HIGH
:
2628 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2629 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2630 port
->portsc
|= PORTSC_PED
;
2634 port
->portsc
&= ~PORTSC_PR
;
2635 xhci_port_notify(port
, PORTSC_PRC
);
2638 static void xhci_reset(DeviceState
*dev
)
2640 XHCIState
*xhci
= XHCI(dev
);
2643 trace_usb_xhci_reset();
2644 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2645 DPRINTF("xhci: reset while running!\n");
2649 xhci
->usbsts
= USBSTS_HCH
;
2652 xhci
->crcr_high
= 0;
2653 xhci
->dcbaap_low
= 0;
2654 xhci
->dcbaap_high
= 0;
2657 for (i
= 0; i
< xhci
->numslots
; i
++) {
2658 xhci_disable_slot(xhci
, i
+1);
2661 for (i
= 0; i
< xhci
->numports
; i
++) {
2662 xhci_port_update(xhci
->ports
+ i
, 0);
2665 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2666 xhci
->intr
[i
].iman
= 0;
2667 xhci
->intr
[i
].imod
= 0;
2668 xhci
->intr
[i
].erstsz
= 0;
2669 xhci
->intr
[i
].erstba_low
= 0;
2670 xhci
->intr
[i
].erstba_high
= 0;
2671 xhci
->intr
[i
].erdp_low
= 0;
2672 xhci
->intr
[i
].erdp_high
= 0;
2674 xhci
->intr
[i
].er_ep_idx
= 0;
2675 xhci
->intr
[i
].er_pcs
= 1;
2676 xhci
->intr
[i
].ev_buffer_put
= 0;
2677 xhci
->intr
[i
].ev_buffer_get
= 0;
2680 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2681 xhci_mfwrap_update(xhci
);
2684 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2686 XHCIState
*xhci
= ptr
;
2690 case 0x00: /* HCIVERSION, CAPLENGTH */
2691 ret
= 0x01000000 | LEN_CAP
;
2693 case 0x04: /* HCSPARAMS 1 */
2694 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2695 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2697 case 0x08: /* HCSPARAMS 2 */
2700 case 0x0c: /* HCSPARAMS 3 */
2703 case 0x10: /* HCCPARAMS */
2704 if (sizeof(dma_addr_t
) == 4) {
2705 ret
= 0x00080000 | (xhci
->max_pstreams_mask
<< 12);
2707 ret
= 0x00080001 | (xhci
->max_pstreams_mask
<< 12);
2710 case 0x14: /* DBOFF */
2713 case 0x18: /* RTSOFF */
2717 /* extended capabilities */
2718 case 0x20: /* Supported Protocol:00 */
2719 ret
= 0x02000402; /* USB 2.0 */
2721 case 0x24: /* Supported Protocol:04 */
2722 ret
= 0x20425355; /* "USB " */
2724 case 0x28: /* Supported Protocol:08 */
2725 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2726 ret
= (xhci
->numports_2
<<8) | (xhci
->numports_3
+1);
2728 ret
= (xhci
->numports_2
<<8) | 1;
2731 case 0x2c: /* Supported Protocol:0c */
2732 ret
= 0x00000000; /* reserved */
2734 case 0x30: /* Supported Protocol:00 */
2735 ret
= 0x03000002; /* USB 3.0 */
2737 case 0x34: /* Supported Protocol:04 */
2738 ret
= 0x20425355; /* "USB " */
2740 case 0x38: /* Supported Protocol:08 */
2741 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2742 ret
= (xhci
->numports_3
<<8) | 1;
2744 ret
= (xhci
->numports_3
<<8) | (xhci
->numports_2
+1);
2747 case 0x3c: /* Supported Protocol:0c */
2748 ret
= 0x00000000; /* reserved */
2751 trace_usb_xhci_unimplemented("cap read", reg
);
2755 trace_usb_xhci_cap_read(reg
, ret
);
2759 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2761 XHCIPort
*port
= ptr
;
2765 case 0x00: /* PORTSC */
2768 case 0x04: /* PORTPMSC */
2769 case 0x08: /* PORTLI */
2772 case 0x0c: /* reserved */
2774 trace_usb_xhci_unimplemented("port read", reg
);
2778 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2782 static void xhci_port_write(void *ptr
, hwaddr reg
,
2783 uint64_t val
, unsigned size
)
2785 XHCIPort
*port
= ptr
;
2786 uint32_t portsc
, notify
;
2788 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2791 case 0x00: /* PORTSC */
2792 /* write-1-to-start bits */
2793 if (val
& PORTSC_WPR
) {
2794 xhci_port_reset(port
, true);
2797 if (val
& PORTSC_PR
) {
2798 xhci_port_reset(port
, false);
2802 portsc
= port
->portsc
;
2804 /* write-1-to-clear bits*/
2805 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2806 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2807 if (val
& PORTSC_LWS
) {
2808 /* overwrite PLS only when LWS=1 */
2809 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
2810 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
2813 if (old_pls
!= PLS_U0
) {
2814 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2815 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2816 notify
= PORTSC_PLC
;
2820 if (old_pls
< PLS_U3
) {
2821 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2822 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2826 /* windows does this for some reason, don't spam stderr */
2829 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2830 __func__
, old_pls
, new_pls
);
2834 /* read/write bits */
2835 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2836 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2837 port
->portsc
= portsc
;
2839 xhci_port_notify(port
, notify
);
2842 case 0x04: /* PORTPMSC */
2843 case 0x08: /* PORTLI */
2845 trace_usb_xhci_unimplemented("port write", reg
);
2849 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2851 XHCIState
*xhci
= ptr
;
2855 case 0x00: /* USBCMD */
2858 case 0x04: /* USBSTS */
2861 case 0x08: /* PAGESIZE */
2864 case 0x14: /* DNCTRL */
2867 case 0x18: /* CRCR low */
2868 ret
= xhci
->crcr_low
& ~0xe;
2870 case 0x1c: /* CRCR high */
2871 ret
= xhci
->crcr_high
;
2873 case 0x30: /* DCBAAP low */
2874 ret
= xhci
->dcbaap_low
;
2876 case 0x34: /* DCBAAP high */
2877 ret
= xhci
->dcbaap_high
;
2879 case 0x38: /* CONFIG */
2883 trace_usb_xhci_unimplemented("oper read", reg
);
2887 trace_usb_xhci_oper_read(reg
, ret
);
2891 static void xhci_oper_write(void *ptr
, hwaddr reg
,
2892 uint64_t val
, unsigned size
)
2894 XHCIState
*xhci
= XHCI(ptr
);
2896 trace_usb_xhci_oper_write(reg
, val
);
2899 case 0x00: /* USBCMD */
2900 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2902 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2905 if (val
& USBCMD_CSS
) {
2907 xhci
->usbsts
&= ~USBSTS_SRE
;
2909 if (val
& USBCMD_CRS
) {
2911 xhci
->usbsts
|= USBSTS_SRE
;
2913 xhci
->usbcmd
= val
& 0xc0f;
2914 xhci_mfwrap_update(xhci
);
2915 if (val
& USBCMD_HCRST
) {
2916 xhci_reset(DEVICE(xhci
));
2918 xhci_intr_update(xhci
, 0);
2921 case 0x04: /* USBSTS */
2922 /* these bits are write-1-to-clear */
2923 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2924 xhci_intr_update(xhci
, 0);
2927 case 0x14: /* DNCTRL */
2928 xhci
->dnctrl
= val
& 0xffff;
2930 case 0x18: /* CRCR low */
2931 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2933 case 0x1c: /* CRCR high */
2934 xhci
->crcr_high
= val
;
2935 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2936 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2937 xhci
->crcr_low
&= ~CRCR_CRR
;
2938 xhci_event(xhci
, &event
, 0);
2939 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2941 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2942 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2944 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2946 case 0x30: /* DCBAAP low */
2947 xhci
->dcbaap_low
= val
& 0xffffffc0;
2949 case 0x34: /* DCBAAP high */
2950 xhci
->dcbaap_high
= val
;
2952 case 0x38: /* CONFIG */
2953 xhci
->config
= val
& 0xff;
2956 trace_usb_xhci_unimplemented("oper write", reg
);
2960 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
2963 XHCIState
*xhci
= ptr
;
2968 case 0x00: /* MFINDEX */
2969 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
2972 trace_usb_xhci_unimplemented("runtime read", reg
);
2976 int v
= (reg
- 0x20) / 0x20;
2977 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
2978 switch (reg
& 0x1f) {
2979 case 0x00: /* IMAN */
2982 case 0x04: /* IMOD */
2985 case 0x08: /* ERSTSZ */
2988 case 0x10: /* ERSTBA low */
2989 ret
= intr
->erstba_low
;
2991 case 0x14: /* ERSTBA high */
2992 ret
= intr
->erstba_high
;
2994 case 0x18: /* ERDP low */
2995 ret
= intr
->erdp_low
;
2997 case 0x1c: /* ERDP high */
2998 ret
= intr
->erdp_high
;
3003 trace_usb_xhci_runtime_read(reg
, ret
);
3007 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3008 uint64_t val
, unsigned size
)
3010 XHCIState
*xhci
= ptr
;
3011 int v
= (reg
- 0x20) / 0x20;
3012 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3013 trace_usb_xhci_runtime_write(reg
, val
);
3016 trace_usb_xhci_unimplemented("runtime write", reg
);
3020 switch (reg
& 0x1f) {
3021 case 0x00: /* IMAN */
3022 if (val
& IMAN_IP
) {
3023 intr
->iman
&= ~IMAN_IP
;
3025 intr
->iman
&= ~IMAN_IE
;
3026 intr
->iman
|= val
& IMAN_IE
;
3027 xhci_intr_update(xhci
, v
);
3029 case 0x04: /* IMOD */
3032 case 0x08: /* ERSTSZ */
3033 intr
->erstsz
= val
& 0xffff;
3035 case 0x10: /* ERSTBA low */
3036 if (xhci
->nec_quirks
) {
3037 /* NEC driver bug: it doesn't align this to 64 bytes */
3038 intr
->erstba_low
= val
& 0xfffffff0;
3040 intr
->erstba_low
= val
& 0xffffffc0;
3043 case 0x14: /* ERSTBA high */
3044 intr
->erstba_high
= val
;
3045 xhci_er_reset(xhci
, v
);
3047 case 0x18: /* ERDP low */
3048 if (val
& ERDP_EHB
) {
3049 intr
->erdp_low
&= ~ERDP_EHB
;
3051 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3052 if (val
& ERDP_EHB
) {
3053 dma_addr_t erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
3054 unsigned int dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
3055 if (erdp
>= intr
->er_start
&&
3056 erdp
< (intr
->er_start
+ TRB_SIZE
* intr
->er_size
) &&
3057 dp_idx
!= intr
->er_ep_idx
) {
3058 xhci_intr_raise(xhci
, v
);
3062 case 0x1c: /* ERDP high */
3063 intr
->erdp_high
= val
;
3066 trace_usb_xhci_unimplemented("oper write", reg
);
3070 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3073 /* doorbells always read as 0 */
3074 trace_usb_xhci_doorbell_read(reg
, 0);
3078 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3079 uint64_t val
, unsigned size
)
3081 XHCIState
*xhci
= ptr
;
3082 unsigned int epid
, streamid
;
3084 trace_usb_xhci_doorbell_write(reg
, val
);
3086 if (!xhci_running(xhci
)) {
3087 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3095 xhci_process_commands(xhci
);
3097 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3102 streamid
= (val
>> 16) & 0xffff;
3103 if (reg
> xhci
->numslots
) {
3104 DPRINTF("xhci: bad doorbell %d\n", (int)reg
);
3105 } else if (epid
== 0 || epid
> 31) {
3106 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3107 (int)reg
, (uint32_t)val
);
3109 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3114 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3120 static const MemoryRegionOps xhci_cap_ops
= {
3121 .read
= xhci_cap_read
,
3122 .write
= xhci_cap_write
,
3123 .valid
.min_access_size
= 1,
3124 .valid
.max_access_size
= 4,
3125 .impl
.min_access_size
= 4,
3126 .impl
.max_access_size
= 4,
3127 .endianness
= DEVICE_LITTLE_ENDIAN
,
3130 static const MemoryRegionOps xhci_oper_ops
= {
3131 .read
= xhci_oper_read
,
3132 .write
= xhci_oper_write
,
3133 .valid
.min_access_size
= 4,
3134 .valid
.max_access_size
= sizeof(dma_addr_t
),
3135 .endianness
= DEVICE_LITTLE_ENDIAN
,
3138 static const MemoryRegionOps xhci_port_ops
= {
3139 .read
= xhci_port_read
,
3140 .write
= xhci_port_write
,
3141 .valid
.min_access_size
= 4,
3142 .valid
.max_access_size
= 4,
3143 .endianness
= DEVICE_LITTLE_ENDIAN
,
3146 static const MemoryRegionOps xhci_runtime_ops
= {
3147 .read
= xhci_runtime_read
,
3148 .write
= xhci_runtime_write
,
3149 .valid
.min_access_size
= 4,
3150 .valid
.max_access_size
= sizeof(dma_addr_t
),
3151 .endianness
= DEVICE_LITTLE_ENDIAN
,
3154 static const MemoryRegionOps xhci_doorbell_ops
= {
3155 .read
= xhci_doorbell_read
,
3156 .write
= xhci_doorbell_write
,
3157 .valid
.min_access_size
= 4,
3158 .valid
.max_access_size
= 4,
3159 .endianness
= DEVICE_LITTLE_ENDIAN
,
3162 static void xhci_attach(USBPort
*usbport
)
3164 XHCIState
*xhci
= usbport
->opaque
;
3165 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3167 xhci_port_update(port
, 0);
3170 static void xhci_detach(USBPort
*usbport
)
3172 XHCIState
*xhci
= usbport
->opaque
;
3173 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3175 xhci_detach_slot(xhci
, usbport
);
3176 xhci_port_update(port
, 1);
3179 static void xhci_wakeup(USBPort
*usbport
)
3181 XHCIState
*xhci
= usbport
->opaque
;
3182 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3185 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3188 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3189 xhci_port_notify(port
, PORTSC_PLC
);
3192 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3194 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3196 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3197 xhci_ep_nuke_one_xfer(xfer
, 0);
3200 xhci_try_complete_packet(xfer
);
3201 xhci_kick_epctx(xfer
->epctx
, xfer
->streamid
);
3202 if (xfer
->complete
) {
3203 xhci_ep_free_xfer(xfer
);
3207 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3209 USBBus
*bus
= usb_bus_from_device(child
);
3210 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3212 xhci_detach_slot(xhci
, child
->port
);
3215 static USBPortOps xhci_uport_ops
= {
3216 .attach
= xhci_attach
,
3217 .detach
= xhci_detach
,
3218 .wakeup
= xhci_wakeup
,
3219 .complete
= xhci_complete
,
3220 .child_detach
= xhci_child_detach
,
3223 static int xhci_find_epid(USBEndpoint
*ep
)
3228 if (ep
->pid
== USB_TOKEN_IN
) {
3229 return ep
->nr
* 2 + 1;
3235 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
)
3243 uport
= epctx
->xhci
->slots
[epctx
->slotid
- 1].uport
;
3244 if (!uport
|| !uport
->dev
) {
3247 token
= (epctx
->epid
& 1) ? USB_TOKEN_IN
: USB_TOKEN_OUT
;
3248 return usb_ep_get(uport
->dev
, token
, epctx
->epid
>> 1);
3251 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3252 unsigned int stream
)
3254 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3257 DPRINTF("%s\n", __func__
);
3258 slotid
= ep
->dev
->addr
;
3259 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3260 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);