PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / versatile_pci.c
1 /*
2 * ARM Versatile/PB PCI host controller
3 *
4 * Copyright (c) 2006-2009 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the LGPL.
8 */
9
10 #include "sysbus.h"
11 #include "pci.h"
12 #include "pci_host.h"
13 #include "exec-memory.h"
14
15 typedef struct {
16 SysBusDevice busdev;
17 qemu_irq irq[4];
18 int realview;
19 MemoryRegion mem_config;
20 MemoryRegion mem_config2;
21 MemoryRegion isa;
22 } PCIVPBState;
23
24 static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
25 {
26 return addr & 0xffffff;
27 }
28
29 static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
30 uint64_t val, unsigned size)
31 {
32 pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
33 }
34
35 static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
36 unsigned size)
37 {
38 uint32_t val;
39 val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
40 return val;
41 }
42
43 static const MemoryRegionOps pci_vpb_config_ops = {
44 .read = pci_vpb_config_read,
45 .write = pci_vpb_config_write,
46 .endianness = DEVICE_NATIVE_ENDIAN,
47 };
48
49 static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
50 {
51 return irq_num;
52 }
53
54 static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
55 {
56 qemu_irq *pic = opaque;
57
58 qemu_set_irq(pic[irq_num], level);
59 }
60
61 static int pci_vpb_init(SysBusDevice *dev)
62 {
63 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
64 PCIBus *bus;
65 int i;
66
67 for (i = 0; i < 4; i++) {
68 sysbus_init_irq(dev, &s->irq[i]);
69 }
70 bus = pci_register_bus(&dev->qdev, "pci",
71 pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
72 get_system_memory(), get_system_io(),
73 PCI_DEVFN(11, 0), 4);
74
75 /* ??? Register memory space. */
76
77 /* Our memory regions are:
78 * 0 : PCI self config window
79 * 1 : PCI config window
80 * 2 : PCI IO window (realview_pci only)
81 */
82 memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
83 "pci-vpb-selfconfig", 0x1000000);
84 sysbus_init_mmio(dev, &s->mem_config);
85 memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
86 "pci-vpb-config", 0x1000000);
87 sysbus_init_mmio(dev, &s->mem_config2);
88 if (s->realview) {
89 isa_mmio_setup(&s->isa, 0x0100000);
90 sysbus_init_mmio(dev, &s->isa);
91 }
92
93 pci_create_simple(bus, -1, "versatile_pci_host");
94 return 0;
95 }
96
97 static int pci_realview_init(SysBusDevice *dev)
98 {
99 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
100 s->realview = 1;
101 return pci_vpb_init(dev);
102 }
103
104 static int versatile_pci_host_init(PCIDevice *d)
105 {
106 pci_set_word(d->config + PCI_STATUS,
107 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
108 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
109 return 0;
110 }
111
112 static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
113 {
114 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
115
116 k->init = versatile_pci_host_init;
117 k->vendor_id = PCI_VENDOR_ID_XILINX;
118 k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
119 k->class_id = PCI_CLASS_PROCESSOR_CO;
120 }
121
122 static DeviceInfo versatile_pci_host_info = {
123 .name = "versatile_pci_host",
124 .size = sizeof(PCIDevice),
125 .class_init = versatile_pci_host_class_init,
126 };
127
128 static void pci_vpb_class_init(ObjectClass *klass, void *data)
129 {
130 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
131
132 sdc->init = pci_vpb_init;
133 }
134
135 static DeviceInfo pci_vpb_info = {
136 .name = "versatile_pci",
137 .size = sizeof(PCIVPBState),
138 .class_init = pci_vpb_class_init,
139 };
140
141 static void pci_realview_class_init(ObjectClass *klass, void *data)
142 {
143 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
144
145 sdc->init = pci_realview_init;
146 }
147
148 static DeviceInfo pci_realview_info = {
149 .name = "realview_pci",
150 .size = sizeof(PCIVPBState),
151 .class_init = pci_realview_class_init,
152 };
153
154 static void versatile_pci_register_devices(void)
155 {
156 sysbus_qdev_register(&pci_vpb_info);
157 sysbus_qdev_register(&pci_realview_info);
158 pci_qdev_register(&versatile_pci_host_info);
159 }
160
161 device_init(versatile_pci_register_devices)