PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / versatilepb.c
1 /*
2 * ARM Versatile Platform/Application Baseboard System emulation.
3 *
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "arm-misc.h"
12 #include "primecell.h"
13 #include "devices.h"
14 #include "net.h"
15 #include "sysemu.h"
16 #include "pci.h"
17 #include "usb-ohci.h"
18 #include "boards.h"
19 #include "blockdev.h"
20 #include "exec-memory.h"
21
22 /* Primary interrupt controller. */
23
24 typedef struct vpb_sic_state
25 {
26 SysBusDevice busdev;
27 MemoryRegion iomem;
28 uint32_t level;
29 uint32_t mask;
30 uint32_t pic_enable;
31 qemu_irq parent[32];
32 int irq;
33 } vpb_sic_state;
34
35 static const VMStateDescription vmstate_vpb_sic = {
36 .name = "versatilepb_sic",
37 .version_id = 1,
38 .minimum_version_id = 1,
39 .fields = (VMStateField[]) {
40 VMSTATE_UINT32(level, vpb_sic_state),
41 VMSTATE_UINT32(mask, vpb_sic_state),
42 VMSTATE_UINT32(pic_enable, vpb_sic_state),
43 VMSTATE_END_OF_LIST()
44 }
45 };
46
47 static void vpb_sic_update(vpb_sic_state *s)
48 {
49 uint32_t flags;
50
51 flags = s->level & s->mask;
52 qemu_set_irq(s->parent[s->irq], flags != 0);
53 }
54
55 static void vpb_sic_update_pic(vpb_sic_state *s)
56 {
57 int i;
58 uint32_t mask;
59
60 for (i = 21; i <= 30; i++) {
61 mask = 1u << i;
62 if (!(s->pic_enable & mask))
63 continue;
64 qemu_set_irq(s->parent[i], (s->level & mask) != 0);
65 }
66 }
67
68 static void vpb_sic_set_irq(void *opaque, int irq, int level)
69 {
70 vpb_sic_state *s = (vpb_sic_state *)opaque;
71 if (level)
72 s->level |= 1u << irq;
73 else
74 s->level &= ~(1u << irq);
75 if (s->pic_enable & (1u << irq))
76 qemu_set_irq(s->parent[irq], level);
77 vpb_sic_update(s);
78 }
79
80 static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
81 unsigned size)
82 {
83 vpb_sic_state *s = (vpb_sic_state *)opaque;
84
85 switch (offset >> 2) {
86 case 0: /* STATUS */
87 return s->level & s->mask;
88 case 1: /* RAWSTAT */
89 return s->level;
90 case 2: /* ENABLE */
91 return s->mask;
92 case 4: /* SOFTINT */
93 return s->level & 1;
94 case 8: /* PICENABLE */
95 return s->pic_enable;
96 default:
97 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
98 return 0;
99 }
100 }
101
102 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
103 uint64_t value, unsigned size)
104 {
105 vpb_sic_state *s = (vpb_sic_state *)opaque;
106
107 switch (offset >> 2) {
108 case 2: /* ENSET */
109 s->mask |= value;
110 break;
111 case 3: /* ENCLR */
112 s->mask &= ~value;
113 break;
114 case 4: /* SOFTINTSET */
115 if (value)
116 s->mask |= 1;
117 break;
118 case 5: /* SOFTINTCLR */
119 if (value)
120 s->mask &= ~1u;
121 break;
122 case 8: /* PICENSET */
123 s->pic_enable |= (value & 0x7fe00000);
124 vpb_sic_update_pic(s);
125 break;
126 case 9: /* PICENCLR */
127 s->pic_enable &= ~value;
128 vpb_sic_update_pic(s);
129 break;
130 default:
131 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
132 return;
133 }
134 vpb_sic_update(s);
135 }
136
137 static const MemoryRegionOps vpb_sic_ops = {
138 .read = vpb_sic_read,
139 .write = vpb_sic_write,
140 .endianness = DEVICE_NATIVE_ENDIAN,
141 };
142
143 static int vpb_sic_init(SysBusDevice *dev)
144 {
145 vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
146 int i;
147
148 qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
149 for (i = 0; i < 32; i++) {
150 sysbus_init_irq(dev, &s->parent[i]);
151 }
152 s->irq = 31;
153 memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
154 sysbus_init_mmio(dev, &s->iomem);
155 return 0;
156 }
157
158 /* Board init. */
159
160 /* The AB and PB boards both use the same core, just with different
161 peripherans and expansion busses. For now we emulate a subset of the
162 PB peripherals and just change the board ID. */
163
164 static struct arm_boot_info versatile_binfo;
165
166 static void versatile_init(ram_addr_t ram_size,
167 const char *boot_device,
168 const char *kernel_filename, const char *kernel_cmdline,
169 const char *initrd_filename, const char *cpu_model,
170 int board_id)
171 {
172 CPUState *env;
173 MemoryRegion *sysmem = get_system_memory();
174 MemoryRegion *ram = g_new(MemoryRegion, 1);
175 qemu_irq *cpu_pic;
176 qemu_irq pic[32];
177 qemu_irq sic[32];
178 DeviceState *dev, *sysctl;
179 SysBusDevice *busdev;
180 DeviceState *pl041;
181 PCIBus *pci_bus;
182 NICInfo *nd;
183 int n;
184 int done_smc = 0;
185
186 if (!cpu_model)
187 cpu_model = "arm926";
188 env = cpu_init(cpu_model);
189 if (!env) {
190 fprintf(stderr, "Unable to find CPU definition\n");
191 exit(1);
192 }
193 memory_region_init_ram(ram, "versatile.ram", ram_size);
194 vmstate_register_ram_global(ram);
195 /* ??? RAM should repeat to fill physical memory space. */
196 /* SDRAM at address zero. */
197 memory_region_add_subregion(sysmem, 0, ram);
198
199 sysctl = qdev_create(NULL, "realview_sysctl");
200 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
201 qdev_init_nofail(sysctl);
202 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
203 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
204
205 cpu_pic = arm_pic_init_cpu(env);
206 dev = sysbus_create_varargs("pl190", 0x10140000,
207 cpu_pic[0], cpu_pic[1], NULL);
208 for (n = 0; n < 32; n++) {
209 pic[n] = qdev_get_gpio_in(dev, n);
210 }
211 dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
212 for (n = 0; n < 32; n++) {
213 sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
214 sic[n] = qdev_get_gpio_in(dev, n);
215 }
216
217 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
218 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
219
220 dev = qdev_create(NULL, "versatile_pci");
221 busdev = sysbus_from_qdev(dev);
222 qdev_init_nofail(dev);
223 sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
224 sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
225 sysbus_connect_irq(busdev, 0, sic[27]);
226 sysbus_connect_irq(busdev, 1, sic[28]);
227 sysbus_connect_irq(busdev, 2, sic[29]);
228 sysbus_connect_irq(busdev, 3, sic[30]);
229 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
230
231 /* The Versatile PCI bridge does not provide access to PCI IO space,
232 so many of the qemu PCI devices are not useable. */
233 for(n = 0; n < nb_nics; n++) {
234 nd = &nd_table[n];
235
236 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
237 smc91c111_init(nd, 0x10010000, sic[25]);
238 done_smc = 1;
239 } else {
240 pci_nic_init_nofail(nd, "rtl8139", NULL);
241 }
242 }
243 if (usb_enabled) {
244 usb_ohci_init_pci(pci_bus, -1);
245 }
246 n = drive_get_max_bus(IF_SCSI);
247 while (n >= 0) {
248 pci_create_simple(pci_bus, -1, "lsi53c895a");
249 n--;
250 }
251
252 sysbus_create_simple("pl011", 0x101f1000, pic[12]);
253 sysbus_create_simple("pl011", 0x101f2000, pic[13]);
254 sysbus_create_simple("pl011", 0x101f3000, pic[14]);
255 sysbus_create_simple("pl011", 0x10009000, sic[6]);
256
257 sysbus_create_simple("pl080", 0x10130000, pic[17]);
258 sysbus_create_simple("sp804", 0x101e2000, pic[4]);
259 sysbus_create_simple("sp804", 0x101e3000, pic[5]);
260
261 /* The versatile/PB actually has a modified Color LCD controller
262 that includes hardware cursor support from the PL111. */
263 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
264 /* Wire up the mux control signals from the SYS_CLCD register */
265 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
266
267 sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
268 sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
269
270 /* Add PL031 Real Time Clock. */
271 sysbus_create_simple("pl031", 0x101e8000, pic[10]);
272
273 /* Add PL041 AACI Interface to the LM4549 codec */
274 pl041 = qdev_create(NULL, "pl041");
275 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
276 qdev_init_nofail(pl041);
277 sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
278 sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);
279
280 /* Memory map for Versatile/PB: */
281 /* 0x10000000 System registers. */
282 /* 0x10001000 PCI controller config registers. */
283 /* 0x10002000 Serial bus interface. */
284 /* 0x10003000 Secondary interrupt controller. */
285 /* 0x10004000 AACI (audio). */
286 /* 0x10005000 MMCI0. */
287 /* 0x10006000 KMI0 (keyboard). */
288 /* 0x10007000 KMI1 (mouse). */
289 /* 0x10008000 Character LCD Interface. */
290 /* 0x10009000 UART3. */
291 /* 0x1000a000 Smart card 1. */
292 /* 0x1000b000 MMCI1. */
293 /* 0x10010000 Ethernet. */
294 /* 0x10020000 USB. */
295 /* 0x10100000 SSMC. */
296 /* 0x10110000 MPMC. */
297 /* 0x10120000 CLCD Controller. */
298 /* 0x10130000 DMA Controller. */
299 /* 0x10140000 Vectored interrupt controller. */
300 /* 0x101d0000 AHB Monitor Interface. */
301 /* 0x101e0000 System Controller. */
302 /* 0x101e1000 Watchdog Interface. */
303 /* 0x101e2000 Timer 0/1. */
304 /* 0x101e3000 Timer 2/3. */
305 /* 0x101e4000 GPIO port 0. */
306 /* 0x101e5000 GPIO port 1. */
307 /* 0x101e6000 GPIO port 2. */
308 /* 0x101e7000 GPIO port 3. */
309 /* 0x101e8000 RTC. */
310 /* 0x101f0000 Smart card 0. */
311 /* 0x101f1000 UART0. */
312 /* 0x101f2000 UART1. */
313 /* 0x101f3000 UART2. */
314 /* 0x101f4000 SSPI. */
315
316 versatile_binfo.ram_size = ram_size;
317 versatile_binfo.kernel_filename = kernel_filename;
318 versatile_binfo.kernel_cmdline = kernel_cmdline;
319 versatile_binfo.initrd_filename = initrd_filename;
320 versatile_binfo.board_id = board_id;
321 arm_load_kernel(env, &versatile_binfo);
322 }
323
324 static void vpb_init(ram_addr_t ram_size,
325 const char *boot_device,
326 const char *kernel_filename, const char *kernel_cmdline,
327 const char *initrd_filename, const char *cpu_model)
328 {
329 versatile_init(ram_size,
330 boot_device,
331 kernel_filename, kernel_cmdline,
332 initrd_filename, cpu_model, 0x183);
333 }
334
335 static void vab_init(ram_addr_t ram_size,
336 const char *boot_device,
337 const char *kernel_filename, const char *kernel_cmdline,
338 const char *initrd_filename, const char *cpu_model)
339 {
340 versatile_init(ram_size,
341 boot_device,
342 kernel_filename, kernel_cmdline,
343 initrd_filename, cpu_model, 0x25e);
344 }
345
346 static QEMUMachine versatilepb_machine = {
347 .name = "versatilepb",
348 .desc = "ARM Versatile/PB (ARM926EJ-S)",
349 .init = vpb_init,
350 .use_scsi = 1,
351 };
352
353 static QEMUMachine versatileab_machine = {
354 .name = "versatileab",
355 .desc = "ARM Versatile/AB (ARM926EJ-S)",
356 .init = vab_init,
357 .use_scsi = 1,
358 };
359
360 static void versatile_machine_init(void)
361 {
362 qemu_register_machine(&versatilepb_machine);
363 qemu_register_machine(&versatileab_machine);
364 }
365
366 machine_init(versatile_machine_init);
367
368 static void vpb_sic_class_init(ObjectClass *klass, void *data)
369 {
370 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
371
372 k->init = vpb_sic_init;
373 }
374
375 static DeviceInfo vpb_sic_info = {
376 .name = "versatilepb_sic",
377 .size = sizeof(vpb_sic_state),
378 .vmsd = &vmstate_vpb_sic,
379 .no_user = 1,
380 .class_init = vpb_sic_class_init,
381 };
382
383 static void versatilepb_register_devices(void)
384 {
385 sysbus_register_withprop(&vpb_sic_info);
386 }
387
388 device_init(versatilepb_register_devices)