VMXNET3 device implementation
[qemu.git] / hw / vmxnet3.c
1 /*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "hw.h"
19 #include "pci/pci.h"
20 #include "net/net.h"
21 #include "virtio-net.h"
22 #include "net/tap.h"
23 #include "net/checksum.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu-common.h"
26 #include "qemu/bswap.h"
27 #include "pci/msix.h"
28 #include "pci/msi.h"
29
30 #include "vmxnet3.h"
31 #include "vmxnet_debug.h"
32 #include "vmware_utils.h"
33 #include "vmxnet_tx_pkt.h"
34 #include "vmxnet_rx_pkt.h"
35
36 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
37 #define VMXNET3_MSIX_BAR_SIZE 0x2000
38
39 #define VMXNET3_BAR0_IDX (0)
40 #define VMXNET3_BAR1_IDX (1)
41 #define VMXNET3_MSIX_BAR_IDX (2)
42
43 #define VMXNET3_OFF_MSIX_TABLE (0x000)
44 #define VMXNET3_OFF_MSIX_PBA (0x800)
45
46 /* Link speed in Mbps should be shifted by 16 */
47 #define VMXNET3_LINK_SPEED (1000 << 16)
48
49 /* Link status: 1 - up, 0 - down. */
50 #define VMXNET3_LINK_STATUS_UP 0x1
51
52 /* Least significant bit should be set for revision and version */
53 #define VMXNET3_DEVICE_VERSION 0x1
54 #define VMXNET3_DEVICE_REVISION 0x1
55
56 /* Macros for rings descriptors access */
57 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
58 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
59
60 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
61 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
62
63 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
64 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
65
66 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
67 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
68
69 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
70 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
71
72 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
73 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
74
75 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
76 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
77
78 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
79 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
80
81 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
82 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
83
84 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
85 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
86
87 /* Macros for guest driver shared area access */
88 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
89 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
90
91 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
92 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
93
94 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
95 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
96
97 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
98 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
99
100 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
101 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
102
103 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
104 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
105
106 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
107
108 #define TYPE_VMXNET3 "vmxnet3"
109 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
110
111 /* Cyclic ring abstraction */
112 typedef struct {
113 hwaddr pa;
114 size_t size;
115 size_t cell_size;
116 size_t next;
117 uint8_t gen;
118 } Vmxnet3Ring;
119
120 static inline void vmxnet3_ring_init(Vmxnet3Ring *ring,
121 hwaddr pa,
122 size_t size,
123 size_t cell_size,
124 bool zero_region)
125 {
126 ring->pa = pa;
127 ring->size = size;
128 ring->cell_size = cell_size;
129 ring->gen = VMXNET3_INIT_GEN;
130 ring->next = 0;
131
132 if (zero_region) {
133 vmw_shmem_set(pa, 0, size * cell_size);
134 }
135 }
136
137 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
138 macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu", \
139 (ring_name), (ridx), \
140 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
141
142 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
143 {
144 if (++ring->next >= ring->size) {
145 ring->next = 0;
146 ring->gen ^= 1;
147 }
148 }
149
150 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
151 {
152 if (ring->next-- == 0) {
153 ring->next = ring->size - 1;
154 ring->gen ^= 1;
155 }
156 }
157
158 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
159 {
160 return ring->pa + ring->next * ring->cell_size;
161 }
162
163 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff)
164 {
165 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
166 }
167
168 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff)
169 {
170 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
171 }
172
173 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
174 {
175 return ring->next;
176 }
177
178 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
179 {
180 return ring->gen;
181 }
182
183 /* Debug trace-related functions */
184 static inline void
185 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
186 {
187 VMW_PKPRN("TX DESCR: "
188 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
189 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
190 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
191 le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,
192 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
193 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
194 }
195
196 static inline void
197 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
198 {
199 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
200 "csum_start: %d, csum_offset: %d",
201 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
202 vhdr->csum_start, vhdr->csum_offset);
203 }
204
205 static inline void
206 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
207 {
208 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
209 "dtype: %d, ext1: %d, btype: %d",
210 le64_to_cpu(descr->addr), descr->len, descr->gen,
211 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
212 }
213
214 /* Device state and helper functions */
215 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
216
217 typedef struct {
218 Vmxnet3Ring tx_ring;
219 Vmxnet3Ring comp_ring;
220
221 uint8_t intr_idx;
222 hwaddr tx_stats_pa;
223 struct UPT1_TxStats txq_stats;
224 } Vmxnet3TxqDescr;
225
226 typedef struct {
227 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
228 Vmxnet3Ring comp_ring;
229 uint8_t intr_idx;
230 hwaddr rx_stats_pa;
231 struct UPT1_RxStats rxq_stats;
232 } Vmxnet3RxqDescr;
233
234 typedef struct {
235 bool is_masked;
236 bool is_pending;
237 bool is_asserted;
238 } Vmxnet3IntState;
239
240 typedef struct {
241 PCIDevice parent_obj;
242 NICState *nic;
243 NICConf conf;
244 MemoryRegion bar0;
245 MemoryRegion bar1;
246 MemoryRegion msix_bar;
247
248 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
249 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
250
251 /* Whether MSI-X support was installed successfully */
252 bool msix_used;
253 /* Whether MSI support was installed successfully */
254 bool msi_used;
255 hwaddr drv_shmem;
256 hwaddr temp_shared_guest_driver_memory;
257
258 uint8_t txq_num;
259
260 /* This boolean tells whether RX packet being indicated has to */
261 /* be split into head and body chunks from different RX rings */
262 bool rx_packets_compound;
263
264 bool rx_vlan_stripping;
265 bool lro_supported;
266
267 uint8_t rxq_num;
268
269 /* Network MTU */
270 uint32_t mtu;
271
272 /* Maximum number of fragments for indicated TX packets */
273 uint32_t max_tx_frags;
274
275 /* Maximum number of fragments for indicated RX packets */
276 uint16_t max_rx_frags;
277
278 /* Index for events interrupt */
279 uint8_t event_int_idx;
280
281 /* Whether automatic interrupts masking enabled */
282 bool auto_int_masking;
283
284 bool peer_has_vhdr;
285
286 /* TX packets to QEMU interface */
287 struct VmxnetTxPkt *tx_pkt;
288 uint32_t offload_mode;
289 uint32_t cso_or_gso_size;
290 uint16_t tci;
291 bool needs_vlan;
292
293 struct VmxnetRxPkt *rx_pkt;
294
295 bool tx_sop;
296 bool skip_current_tx_pkt;
297
298 uint32_t device_active;
299 uint32_t last_command;
300
301 uint32_t link_status_and_speed;
302
303 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
304
305 uint32_t temp_mac; /* To store the low part first */
306
307 MACAddr perm_mac;
308 uint32_t vlan_table[VMXNET3_VFT_SIZE];
309 uint32_t rx_mode;
310 MACAddr *mcast_list;
311 uint32_t mcast_list_len;
312 uint32_t mcast_list_buff_size; /* needed for live migration. */
313 } VMXNET3State;
314
315 /* Interrupt management */
316
317 /*
318 *This function returns sign whether interrupt line is in asserted state
319 * This depends on the type of interrupt used. For INTX interrupt line will
320 * be asserted until explicit deassertion, for MSI(X) interrupt line will
321 * be deasserted automatically due to notification semantics of the MSI(X)
322 * interrupts
323 */
324 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
325 {
326 PCIDevice *d = PCI_DEVICE(s);
327
328 if (s->msix_used && msix_enabled(d)) {
329 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
330 msix_notify(d, int_idx);
331 return false;
332 }
333 if (s->msi_used && msi_enabled(d)) {
334 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
335 msi_notify(d, int_idx);
336 return false;
337 }
338
339 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
340 qemu_set_irq(d->irq[int_idx], 1);
341 return true;
342 }
343
344 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
345 {
346 PCIDevice *d = PCI_DEVICE(s);
347
348 /*
349 * This function should never be called for MSI(X) interrupts
350 * because deassertion never required for message interrupts
351 */
352 assert(!s->msix_used || !msix_enabled(d));
353 /*
354 * This function should never be called for MSI(X) interrupts
355 * because deassertion never required for message interrupts
356 */
357 assert(!s->msi_used || !msi_enabled(d));
358
359 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
360 qemu_set_irq(d->irq[lidx], 0);
361 }
362
363 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
364 {
365 if (!s->interrupt_states[lidx].is_pending &&
366 s->interrupt_states[lidx].is_asserted) {
367 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
368 _vmxnet3_deassert_interrupt_line(s, lidx);
369 s->interrupt_states[lidx].is_asserted = false;
370 return;
371 }
372
373 if (s->interrupt_states[lidx].is_pending &&
374 !s->interrupt_states[lidx].is_masked &&
375 !s->interrupt_states[lidx].is_asserted) {
376 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
377 s->interrupt_states[lidx].is_asserted =
378 _vmxnet3_assert_interrupt_line(s, lidx);
379 s->interrupt_states[lidx].is_pending = false;
380 return;
381 }
382 }
383
384 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
385 {
386 PCIDevice *d = PCI_DEVICE(s);
387 s->interrupt_states[lidx].is_pending = true;
388 vmxnet3_update_interrupt_line_state(s, lidx);
389
390 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
391 goto do_automask;
392 }
393
394 if (s->msi_used && msi_enabled(d) && s->auto_int_masking) {
395 goto do_automask;
396 }
397
398 return;
399
400 do_automask:
401 s->interrupt_states[lidx].is_masked = true;
402 vmxnet3_update_interrupt_line_state(s, lidx);
403 }
404
405 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
406 {
407 return s->interrupt_states[lidx].is_asserted;
408 }
409
410 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
411 {
412 s->interrupt_states[int_idx].is_pending = false;
413 if (s->auto_int_masking) {
414 s->interrupt_states[int_idx].is_masked = true;
415 }
416 vmxnet3_update_interrupt_line_state(s, int_idx);
417 }
418
419 static void
420 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
421 {
422 s->interrupt_states[lidx].is_masked = is_masked;
423 vmxnet3_update_interrupt_line_state(s, lidx);
424 }
425
426 static bool vmxnet3_verify_driver_magic(hwaddr dshmem)
427 {
428 return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC);
429 }
430
431 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
432 #define VMXNET3_MAKE_BYTE(byte_num, val) \
433 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
434
435 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
436 {
437 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
438 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
439 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
440 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
441 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
442 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
443
444 VMW_CFPRN("Variable MAC: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
445
446 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
447 }
448
449 static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
450 {
451 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
452 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
453 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
454 VMXNET3_MAKE_BYTE(3, addr->a[3]);
455 }
456
457 static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
458 {
459 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
460 VMXNET3_MAKE_BYTE(1, addr->a[5]);
461 }
462
463 static void
464 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
465 {
466 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
467 }
468
469 static inline void
470 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
471 {
472 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
473 }
474
475 static inline void
476 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
477 {
478 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
479 }
480
481 static void
482 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
483 {
484 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
485 }
486
487 static void
488 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
489 {
490 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
491 }
492
493 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32 tx_ridx)
494 {
495 struct Vmxnet3_TxCompDesc txcq_descr;
496
497 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
498
499 txcq_descr.txdIdx = tx_ridx;
500 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
501
502 vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr);
503
504 /* Flush changes in TX descriptor before changing the counter value */
505 smp_wmb();
506
507 vmxnet3_inc_tx_completion_counter(s, qidx);
508 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
509 }
510
511 static bool
512 vmxnet3_setup_tx_offloads(VMXNET3State *s)
513 {
514 switch (s->offload_mode) {
515 case VMXNET3_OM_NONE:
516 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
517 break;
518
519 case VMXNET3_OM_CSUM:
520 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
521 VMW_PKPRN("L4 CSO requested\n");
522 break;
523
524 case VMXNET3_OM_TSO:
525 vmxnet_tx_pkt_build_vheader(s->tx_pkt, true, true,
526 s->cso_or_gso_size);
527 vmxnet_tx_pkt_update_ip_checksums(s->tx_pkt);
528 VMW_PKPRN("GSO offload requested.");
529 break;
530
531 default:
532 assert(false);
533 return false;
534 }
535
536 return true;
537 }
538
539 static void
540 vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
541 const struct Vmxnet3_TxDesc *txd)
542 {
543 s->offload_mode = txd->om;
544 s->cso_or_gso_size = txd->msscof;
545 s->tci = txd->tci;
546 s->needs_vlan = txd->ti;
547 }
548
549 typedef enum {
550 VMXNET3_PKT_STATUS_OK,
551 VMXNET3_PKT_STATUS_ERROR,
552 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
553 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
554 } Vmxnet3PktStatus;
555
556 static void
557 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
558 Vmxnet3PktStatus status)
559 {
560 size_t tot_len = vmxnet_tx_pkt_get_total_len(s->tx_pkt);
561 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
562
563 switch (status) {
564 case VMXNET3_PKT_STATUS_OK:
565 switch (vmxnet_tx_pkt_get_packet_type(s->tx_pkt)) {
566 case ETH_PKT_BCAST:
567 stats->bcastPktsTxOK++;
568 stats->bcastBytesTxOK += tot_len;
569 break;
570 case ETH_PKT_MCAST:
571 stats->mcastPktsTxOK++;
572 stats->mcastBytesTxOK += tot_len;
573 break;
574 case ETH_PKT_UCAST:
575 stats->ucastPktsTxOK++;
576 stats->ucastBytesTxOK += tot_len;
577 break;
578 default:
579 assert(false);
580 }
581
582 if (s->offload_mode == VMXNET3_OM_TSO) {
583 /*
584 * According to VMWARE headers this statistic is a number
585 * of packets after segmentation but since we don't have
586 * this information in QEMU model, the best we can do is to
587 * provide number of non-segmented packets
588 */
589 stats->TSOPktsTxOK++;
590 stats->TSOBytesTxOK += tot_len;
591 }
592 break;
593
594 case VMXNET3_PKT_STATUS_DISCARD:
595 stats->pktsTxDiscard++;
596 break;
597
598 case VMXNET3_PKT_STATUS_ERROR:
599 stats->pktsTxError++;
600 break;
601
602 default:
603 assert(false);
604 }
605 }
606
607 static void
608 vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
609 int qidx,
610 Vmxnet3PktStatus status)
611 {
612 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
613 size_t tot_len = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
614
615 switch (status) {
616 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
617 stats->pktsRxOutOfBuf++;
618 break;
619
620 case VMXNET3_PKT_STATUS_ERROR:
621 stats->pktsRxError++;
622 break;
623 case VMXNET3_PKT_STATUS_OK:
624 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
625 case ETH_PKT_BCAST:
626 stats->bcastPktsRxOK++;
627 stats->bcastBytesRxOK += tot_len;
628 break;
629 case ETH_PKT_MCAST:
630 stats->mcastPktsRxOK++;
631 stats->mcastBytesRxOK += tot_len;
632 break;
633 case ETH_PKT_UCAST:
634 stats->ucastPktsRxOK++;
635 stats->ucastBytesRxOK += tot_len;
636 break;
637 default:
638 assert(false);
639 }
640
641 if (tot_len > s->mtu) {
642 stats->LROPktsRxOK++;
643 stats->LROBytesRxOK += tot_len;
644 }
645 break;
646 default:
647 assert(false);
648 }
649 }
650
651 static inline bool
652 vmxnet3_pop_next_tx_descr(VMXNET3State *s,
653 int qidx,
654 struct Vmxnet3_TxDesc *txd,
655 uint32_t *descr_idx)
656 {
657 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
658
659 vmxnet3_ring_read_curr_cell(ring, txd);
660 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
661 /* Only read after generation field verification */
662 smp_rmb();
663 /* Re-read to be sure we got the latest version */
664 vmxnet3_ring_read_curr_cell(ring, txd);
665 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
666 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
667 vmxnet3_inc_tx_consumption_counter(s, qidx);
668 return true;
669 }
670
671 return false;
672 }
673
674 static bool
675 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
676 {
677 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
678
679 if (!vmxnet3_setup_tx_offloads(s)) {
680 status = VMXNET3_PKT_STATUS_ERROR;
681 goto func_exit;
682 }
683
684 /* debug prints */
685 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s->tx_pkt));
686 vmxnet_tx_pkt_dump(s->tx_pkt);
687
688 if (!vmxnet_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
689 status = VMXNET3_PKT_STATUS_DISCARD;
690 goto func_exit;
691 }
692
693 func_exit:
694 vmxnet3_on_tx_done_update_stats(s, qidx, status);
695 return (status == VMXNET3_PKT_STATUS_OK);
696 }
697
698 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
699 {
700 struct Vmxnet3_TxDesc txd;
701 uint32_t txd_idx;
702 uint32_t data_len;
703 hwaddr data_pa;
704
705 for (;;) {
706 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
707 break;
708 }
709
710 vmxnet3_dump_tx_descr(&txd);
711
712 if (!s->skip_current_tx_pkt) {
713 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
714 data_pa = le64_to_cpu(txd.addr);
715
716 if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
717 data_pa,
718 data_len)) {
719 s->skip_current_tx_pkt = true;
720 }
721 }
722
723 if (s->tx_sop) {
724 vmxnet3_tx_retrieve_metadata(s, &txd);
725 s->tx_sop = false;
726 }
727
728 if (txd.eop) {
729 if (!s->skip_current_tx_pkt) {
730 vmxnet_tx_pkt_parse(s->tx_pkt);
731
732 if (s->needs_vlan) {
733 vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
734 }
735
736 vmxnet3_send_packet(s, qidx);
737 } else {
738 vmxnet3_on_tx_done_update_stats(s, qidx,
739 VMXNET3_PKT_STATUS_ERROR);
740 }
741
742 vmxnet3_complete_packet(s, qidx, txd_idx);
743 s->tx_sop = true;
744 s->skip_current_tx_pkt = false;
745 vmxnet_tx_pkt_reset(s->tx_pkt);
746 }
747 }
748 }
749
750 static inline void
751 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
752 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
753 {
754 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
755 *didx = vmxnet3_ring_curr_cell_idx(ring);
756 vmxnet3_ring_read_curr_cell(ring, dbuf);
757 }
758
759 static inline uint8_t
760 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
761 {
762 return s->rxq_descr[qidx].rx_ring[ridx].gen;
763 }
764
765 static inline hwaddr
766 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
767 {
768 uint8_t ring_gen;
769 struct Vmxnet3_RxCompDesc rxcd;
770
771 hwaddr daddr =
772 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
773
774 cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
775 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
776
777 if (rxcd.gen != ring_gen) {
778 *descr_gen = ring_gen;
779 vmxnet3_inc_rx_completion_counter(s, qidx);
780 return daddr;
781 }
782
783 return 0;
784 }
785
786 static inline void
787 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
788 {
789 vmxnet3_dec_rx_completion_counter(s, qidx);
790 }
791
792 #define RXQ_IDX (0)
793 #define RX_HEAD_BODY_RING (0)
794 #define RX_BODY_ONLY_RING (1)
795
796 static bool
797 vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
798 struct Vmxnet3_RxDesc *descr_buf,
799 uint32_t *descr_idx,
800 uint32_t *ridx)
801 {
802 for (;;) {
803 uint32_t ring_gen;
804 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
805 descr_buf, descr_idx);
806
807 /* If no more free descriptors - return */
808 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
809 if (descr_buf->gen != ring_gen) {
810 return false;
811 }
812
813 /* Only read after generation field verification */
814 smp_rmb();
815 /* Re-read to be sure we got the latest version */
816 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
817 descr_buf, descr_idx);
818
819 /* Mark current descriptor as used/skipped */
820 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
821
822 /* If this is what we are looking for - return */
823 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
824 *ridx = RX_HEAD_BODY_RING;
825 return true;
826 }
827 }
828 }
829
830 static bool
831 vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
832 struct Vmxnet3_RxDesc *d,
833 uint32_t *didx,
834 uint32_t *ridx)
835 {
836 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
837
838 /* Try to find corresponding descriptor in head/body ring */
839 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
840 /* Only read after generation field verification */
841 smp_rmb();
842 /* Re-read to be sure we got the latest version */
843 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
844 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
845 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
846 *ridx = RX_HEAD_BODY_RING;
847 return true;
848 }
849 }
850
851 /*
852 * If there is no free descriptors on head/body ring or next free
853 * descriptor is a head descriptor switch to body only ring
854 */
855 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
856
857 /* If no more free descriptors - return */
858 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
859 /* Only read after generation field verification */
860 smp_rmb();
861 /* Re-read to be sure we got the latest version */
862 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
863 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
864 *ridx = RX_BODY_ONLY_RING;
865 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
866 return true;
867 }
868
869 return false;
870 }
871
872 static inline bool
873 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
874 struct Vmxnet3_RxDesc *descr_buf,
875 uint32_t *descr_idx,
876 uint32_t *ridx)
877 {
878 if (is_head || !s->rx_packets_compound) {
879 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
880 } else {
881 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
882 }
883 }
884
885 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
886 struct Vmxnet3_RxCompDesc *rxcd)
887 {
888 int csum_ok, is_gso;
889 bool isip4, isip6, istcp, isudp;
890 struct virtio_net_hdr *vhdr;
891 uint8_t offload_type;
892
893 if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
894 rxcd->ts = 1;
895 rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
896 }
897
898 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
899 goto nocsum;
900 }
901
902 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
903 /*
904 * Checksum is valid when lower level tell so or when lower level
905 * requires checksum offload telling that packet produced/bridged
906 * locally and did travel over network after last checksum calculation
907 * or production
908 */
909 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
910 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
911
912 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
913 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
914
915 if (!csum_ok && !is_gso) {
916 goto nocsum;
917 }
918
919 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
920 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
921 goto nocsum;
922 }
923
924 rxcd->cnc = 0;
925 rxcd->v4 = isip4 ? 1 : 0;
926 rxcd->v6 = isip6 ? 1 : 0;
927 rxcd->tcp = istcp ? 1 : 0;
928 rxcd->udp = isudp ? 1 : 0;
929 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
930 return;
931
932 nocsum:
933 rxcd->cnc = 1;
934 return;
935 }
936
937 static void
938 vmxnet3_physical_memory_writev(const struct iovec *iov,
939 size_t start_iov_off,
940 hwaddr target_addr,
941 size_t bytes_to_copy)
942 {
943 size_t curr_off = 0;
944 size_t copied = 0;
945
946 while (bytes_to_copy) {
947 if (start_iov_off < (curr_off + iov->iov_len)) {
948 size_t chunk_len =
949 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
950
951 cpu_physical_memory_write(target_addr + copied,
952 iov->iov_base + start_iov_off - curr_off,
953 chunk_len);
954
955 copied += chunk_len;
956 start_iov_off += chunk_len;
957 curr_off = start_iov_off;
958 bytes_to_copy -= chunk_len;
959 } else {
960 curr_off += iov->iov_len;
961 }
962 iov++;
963 }
964 }
965
966 static bool
967 vmxnet3_indicate_packet(VMXNET3State *s)
968 {
969 struct Vmxnet3_RxDesc rxd;
970 bool is_head = true;
971 uint32_t rxd_idx;
972 uint32_t rx_ridx;
973
974 struct Vmxnet3_RxCompDesc rxcd;
975 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
976 hwaddr new_rxcd_pa = 0;
977 hwaddr ready_rxcd_pa = 0;
978 struct iovec *data = vmxnet_rx_pkt_get_iovec(s->rx_pkt);
979 size_t bytes_copied = 0;
980 size_t bytes_left = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
981 uint16_t num_frags = 0;
982 size_t chunk_size;
983
984 vmxnet_rx_pkt_dump(s->rx_pkt);
985
986 while (bytes_left > 0) {
987
988 /* cannot add more frags to packet */
989 if (num_frags == s->max_rx_frags) {
990 break;
991 }
992
993 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
994 if (!new_rxcd_pa) {
995 break;
996 }
997
998 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
999 break;
1000 }
1001
1002 chunk_size = MIN(bytes_left, rxd.len);
1003 vmxnet3_physical_memory_writev(data, bytes_copied,
1004 le64_to_cpu(rxd.addr), chunk_size);
1005 bytes_copied += chunk_size;
1006 bytes_left -= chunk_size;
1007
1008 vmxnet3_dump_rx_descr(&rxd);
1009
1010 if (0 != ready_rxcd_pa) {
1011 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1012 }
1013
1014 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1015 rxcd.rxdIdx = rxd_idx;
1016 rxcd.len = chunk_size;
1017 rxcd.sop = is_head;
1018 rxcd.gen = new_rxcd_gen;
1019 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1020
1021 if (0 == bytes_left) {
1022 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1023 }
1024
1025 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1026 "sop %d csum_correct %lu",
1027 (unsigned long) rx_ridx,
1028 (unsigned long) rxcd.rxdIdx,
1029 (unsigned long) rxcd.len,
1030 (int) rxcd.sop,
1031 (unsigned long) rxcd.tuc);
1032
1033 is_head = false;
1034 ready_rxcd_pa = new_rxcd_pa;
1035 new_rxcd_pa = 0;
1036 }
1037
1038 if (0 != ready_rxcd_pa) {
1039 rxcd.eop = 1;
1040 rxcd.err = (0 != bytes_left);
1041 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1042
1043 /* Flush RX descriptor changes */
1044 smp_wmb();
1045 }
1046
1047 if (0 != new_rxcd_pa) {
1048 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1049 }
1050
1051 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1052
1053 if (bytes_left == 0) {
1054 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1055 return true;
1056 } else if (num_frags == s->max_rx_frags) {
1057 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1058 return false;
1059 } else {
1060 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1061 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1062 return false;
1063 }
1064 }
1065
1066 static void
1067 vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1068 uint64_t val, unsigned size)
1069 {
1070 VMXNET3State *s = opaque;
1071
1072 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1073 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1074 int tx_queue_idx =
1075 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1076 VMXNET3_REG_ALIGN);
1077 assert(tx_queue_idx <= s->txq_num);
1078 vmxnet3_process_tx_queue(s, tx_queue_idx);
1079 return;
1080 }
1081
1082 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1083 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1084 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1085 VMXNET3_REG_ALIGN);
1086
1087 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1088
1089 vmxnet3_on_interrupt_mask_changed(s, l, val);
1090 return;
1091 }
1092
1093 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1094 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1095 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1096 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1097 return;
1098 }
1099
1100 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1101 (uint64_t) addr, val, size);
1102 }
1103
1104 static uint64_t
1105 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1106 {
1107 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1108 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1109 assert(false);
1110 }
1111
1112 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1113 return 0;
1114 }
1115
1116 static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1117 {
1118 int i;
1119 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1120 s->interrupt_states[i].is_asserted = false;
1121 s->interrupt_states[i].is_pending = false;
1122 s->interrupt_states[i].is_masked = true;
1123 }
1124 }
1125
1126 static void vmxnet3_reset_mac(VMXNET3State *s)
1127 {
1128 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1129 VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
1130 }
1131
1132 static void vmxnet3_deactivate_device(VMXNET3State *s)
1133 {
1134 VMW_CBPRN("Deactivating vmxnet3...");
1135 s->device_active = false;
1136 }
1137
1138 static void vmxnet3_reset(VMXNET3State *s)
1139 {
1140 VMW_CBPRN("Resetting vmxnet3...");
1141
1142 vmxnet3_deactivate_device(s);
1143 vmxnet3_reset_interrupt_states(s);
1144 vmxnet_tx_pkt_reset(s->tx_pkt);
1145 s->drv_shmem = 0;
1146 s->tx_sop = true;
1147 s->skip_current_tx_pkt = false;
1148 }
1149
1150 static void vmxnet3_update_rx_mode(VMXNET3State *s)
1151 {
1152 s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1153 devRead.rxFilterConf.rxMode);
1154 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1155 }
1156
1157 static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1158 {
1159 int i;
1160
1161 /* Copy configuration from shared memory */
1162 VMXNET3_READ_DRV_SHARED(s->drv_shmem,
1163 devRead.rxFilterConf.vfTable,
1164 s->vlan_table,
1165 sizeof(s->vlan_table));
1166
1167 /* Invert byte order when needed */
1168 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1169 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1170 }
1171
1172 /* Dump configuration for debugging purposes */
1173 VMW_CFPRN("Configured VLANs:");
1174 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1175 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1176 VMW_CFPRN("\tVLAN %d is present", i);
1177 }
1178 }
1179 }
1180
1181 static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1182 {
1183 uint16_t list_bytes =
1184 VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
1185 devRead.rxFilterConf.mfTableLen);
1186
1187 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1188
1189 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1190 if (NULL == s->mcast_list) {
1191 if (0 == s->mcast_list_len) {
1192 VMW_CFPRN("Current multicast list is empty");
1193 } else {
1194 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1195 s->mcast_list_len);
1196 }
1197 s->mcast_list_len = 0;
1198 } else {
1199 int i;
1200 hwaddr mcast_list_pa =
1201 VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
1202 devRead.rxFilterConf.mfTablePA);
1203
1204 cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
1205 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1206 for (i = 0; i < s->mcast_list_len; i++) {
1207 VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
1208 }
1209 }
1210 }
1211
1212 static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1213 {
1214 vmxnet3_update_rx_mode(s);
1215 vmxnet3_update_vlan_filters(s);
1216 vmxnet3_update_mcast_filters(s);
1217 }
1218
1219 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1220 {
1221 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1222 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1223 return interrupt_mode;
1224 }
1225
1226 static void vmxnet3_fill_stats(VMXNET3State *s)
1227 {
1228 int i;
1229 for (i = 0; i < s->txq_num; i++) {
1230 cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
1231 &s->txq_descr[i].txq_stats,
1232 sizeof(s->txq_descr[i].txq_stats));
1233 }
1234
1235 for (i = 0; i < s->rxq_num; i++) {
1236 cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
1237 &s->rxq_descr[i].rxq_stats,
1238 sizeof(s->rxq_descr[i].rxq_stats));
1239 }
1240 }
1241
1242 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1243 {
1244 struct Vmxnet3_GOSInfo gos;
1245
1246 VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
1247 &gos, sizeof(gos));
1248 s->rx_packets_compound =
1249 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1250
1251 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1252 }
1253
1254 static void
1255 vmxnet3_dump_conf_descr(const char *name,
1256 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1257 {
1258 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1259 name, pm_descr->confVer, pm_descr->confLen);
1260
1261 };
1262
1263 static void vmxnet3_update_pm_state(VMXNET3State *s)
1264 {
1265 struct Vmxnet3_VariableLenConfDesc pm_descr;
1266
1267 pm_descr.confLen =
1268 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
1269 pm_descr.confVer =
1270 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
1271 pm_descr.confPA =
1272 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
1273
1274 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1275 }
1276
1277 static void vmxnet3_update_features(VMXNET3State *s)
1278 {
1279 uint32_t guest_features;
1280 int rxcso_supported;
1281
1282 guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1283 devRead.misc.uptFeatures);
1284
1285 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1286 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1287 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1288
1289 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1290 s->lro_supported, rxcso_supported,
1291 s->rx_vlan_stripping);
1292 if (s->peer_has_vhdr) {
1293 tap_set_offload(qemu_get_queue(s->nic)->peer,
1294 rxcso_supported,
1295 s->lro_supported,
1296 s->lro_supported,
1297 0,
1298 0);
1299 }
1300 }
1301
1302 static void vmxnet3_activate_device(VMXNET3State *s)
1303 {
1304 int i;
1305 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1306 hwaddr qdescr_table_pa;
1307 uint64_t pa;
1308 uint32_t size;
1309
1310 /* Verify configuration consistency */
1311 if (!vmxnet3_verify_driver_magic(s->drv_shmem)) {
1312 VMW_ERPRN("Device configuration received from driver is invalid");
1313 return;
1314 }
1315
1316 vmxnet3_adjust_by_guest_type(s);
1317 vmxnet3_update_features(s);
1318 vmxnet3_update_pm_state(s);
1319 vmxnet3_setup_rx_filtering(s);
1320 /* Cache fields from shared memory */
1321 s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu);
1322 VMW_CFPRN("MTU is %u", s->mtu);
1323
1324 s->max_rx_frags =
1325 VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG);
1326
1327 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1328
1329 s->event_int_idx =
1330 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);
1331 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1332
1333 s->auto_int_masking =
1334 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask);
1335 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1336
1337 s->txq_num =
1338 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues);
1339 s->rxq_num =
1340 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
1341
1342 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1343 assert(s->txq_num <= VMXNET3_DEVICE_MAX_TX_QUEUES);
1344
1345 qdescr_table_pa =
1346 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA);
1347 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1348
1349 /*
1350 * Worst-case scenario is a packet that holds all TX rings space so
1351 * we calculate total size of all TX rings for max TX fragments number
1352 */
1353 s->max_tx_frags = 0;
1354
1355 /* TX queues */
1356 for (i = 0; i < s->txq_num; i++) {
1357 hwaddr qdescr_pa =
1358 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1359
1360 /* Read interrupt number for this TX queue */
1361 s->txq_descr[i].intr_idx =
1362 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);
1363
1364 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1365
1366 /* Read rings memory locations for TX queues */
1367 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA);
1368 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize);
1369
1370 vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size,
1371 sizeof(struct Vmxnet3_TxDesc), false);
1372 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1373
1374 s->max_tx_frags += size;
1375
1376 /* TXC ring */
1377 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA);
1378 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize);
1379 vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size,
1380 sizeof(struct Vmxnet3_TxCompDesc), true);
1381 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1382
1383 s->txq_descr[i].tx_stats_pa =
1384 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1385
1386 memset(&s->txq_descr[i].txq_stats, 0,
1387 sizeof(s->txq_descr[i].txq_stats));
1388
1389 /* Fill device-managed parameters for queues */
1390 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa,
1391 ctrl.txThreshold,
1392 VMXNET3_DEF_TX_THRESHOLD);
1393 }
1394
1395 /* Preallocate TX packet wrapper */
1396 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1397 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
1398 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
1399
1400 /* Read rings memory locations for RX queues */
1401 for (i = 0; i < s->rxq_num; i++) {
1402 int j;
1403 hwaddr qd_pa =
1404 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1405 i * sizeof(struct Vmxnet3_RxQueueDesc);
1406
1407 /* Read interrupt number for this RX queue */
1408 s->rxq_descr[i].intr_idx =
1409 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx);
1410
1411 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1412
1413 /* Read rings memory locations */
1414 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1415 /* RX rings */
1416 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.rxRingBasePA[j]);
1417 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.rxRingSize[j]);
1418 vmxnet3_ring_init(&s->rxq_descr[i].rx_ring[j], pa, size,
1419 sizeof(struct Vmxnet3_RxDesc), false);
1420 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1421 i, j, pa, size);
1422 }
1423
1424 /* RXC ring */
1425 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.compRingBasePA);
1426 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.compRingSize);
1427 vmxnet3_ring_init(&s->rxq_descr[i].comp_ring, pa, size,
1428 sizeof(struct Vmxnet3_RxCompDesc), true);
1429 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1430
1431 s->rxq_descr[i].rx_stats_pa =
1432 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1433 memset(&s->rxq_descr[i].rxq_stats, 0,
1434 sizeof(s->rxq_descr[i].rxq_stats));
1435 }
1436
1437 /* Make sure everything is in place before device activation */
1438 smp_wmb();
1439
1440 vmxnet3_reset_mac(s);
1441
1442 s->device_active = true;
1443 }
1444
1445 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1446 {
1447 s->last_command = cmd;
1448
1449 switch (cmd) {
1450 case VMXNET3_CMD_GET_PERM_MAC_HI:
1451 VMW_CBPRN("Set: Get upper part of permanent MAC");
1452 break;
1453
1454 case VMXNET3_CMD_GET_PERM_MAC_LO:
1455 VMW_CBPRN("Set: Get lower part of permanent MAC");
1456 break;
1457
1458 case VMXNET3_CMD_GET_STATS:
1459 VMW_CBPRN("Set: Get device statistics");
1460 vmxnet3_fill_stats(s);
1461 break;
1462
1463 case VMXNET3_CMD_ACTIVATE_DEV:
1464 VMW_CBPRN("Set: Activating vmxnet3 device");
1465 vmxnet3_activate_device(s);
1466 break;
1467
1468 case VMXNET3_CMD_UPDATE_RX_MODE:
1469 VMW_CBPRN("Set: Update rx mode");
1470 vmxnet3_update_rx_mode(s);
1471 break;
1472
1473 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1474 VMW_CBPRN("Set: Update VLAN filters");
1475 vmxnet3_update_vlan_filters(s);
1476 break;
1477
1478 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1479 VMW_CBPRN("Set: Update MAC filters");
1480 vmxnet3_update_mcast_filters(s);
1481 break;
1482
1483 case VMXNET3_CMD_UPDATE_FEATURE:
1484 VMW_CBPRN("Set: Update features");
1485 vmxnet3_update_features(s);
1486 break;
1487
1488 case VMXNET3_CMD_UPDATE_PMCFG:
1489 VMW_CBPRN("Set: Update power management config");
1490 vmxnet3_update_pm_state(s);
1491 break;
1492
1493 case VMXNET3_CMD_GET_LINK:
1494 VMW_CBPRN("Set: Get link");
1495 break;
1496
1497 case VMXNET3_CMD_RESET_DEV:
1498 VMW_CBPRN("Set: Reset device");
1499 vmxnet3_reset(s);
1500 break;
1501
1502 case VMXNET3_CMD_QUIESCE_DEV:
1503 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
1504 vmxnet3_deactivate_device(s);
1505 break;
1506
1507 case VMXNET3_CMD_GET_CONF_INTR:
1508 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1509 break;
1510
1511 default:
1512 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1513 break;
1514 }
1515 }
1516
1517 static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1518 {
1519 uint64_t ret;
1520
1521 switch (s->last_command) {
1522 case VMXNET3_CMD_ACTIVATE_DEV:
1523 ret = (s->device_active) ? 0 : -1;
1524 VMW_CFPRN("Device active: %" PRIx64, ret);
1525 break;
1526
1527 case VMXNET3_CMD_GET_LINK:
1528 ret = s->link_status_and_speed;
1529 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1530 break;
1531
1532 case VMXNET3_CMD_GET_PERM_MAC_LO:
1533 ret = vmxnet3_get_mac_low(&s->perm_mac);
1534 break;
1535
1536 case VMXNET3_CMD_GET_PERM_MAC_HI:
1537 ret = vmxnet3_get_mac_high(&s->perm_mac);
1538 break;
1539
1540 case VMXNET3_CMD_GET_CONF_INTR:
1541 ret = vmxnet3_get_interrupt_config(s);
1542 break;
1543
1544 default:
1545 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1546 ret = -1;
1547 break;
1548 }
1549
1550 return ret;
1551 }
1552
1553 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1554 {
1555 uint32_t events;
1556
1557 VMW_CBPRN("Setting events: 0x%x", val);
1558 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
1559 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1560 }
1561
1562 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1563 {
1564 uint32_t events;
1565
1566 VMW_CBPRN("Clearing events: 0x%x", val);
1567 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
1568 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1569 }
1570
1571 static void
1572 vmxnet3_io_bar1_write(void *opaque,
1573 hwaddr addr,
1574 uint64_t val,
1575 unsigned size)
1576 {
1577 VMXNET3State *s = opaque;
1578
1579 switch (addr) {
1580 /* Vmxnet3 Revision Report Selection */
1581 case VMXNET3_REG_VRRS:
1582 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1583 val, size);
1584 break;
1585
1586 /* UPT Version Report Selection */
1587 case VMXNET3_REG_UVRS:
1588 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1589 val, size);
1590 break;
1591
1592 /* Driver Shared Address Low */
1593 case VMXNET3_REG_DSAL:
1594 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1595 val, size);
1596 /*
1597 * Guest driver will first write the low part of the shared
1598 * memory address. We save it to temp variable and set the
1599 * shared address only after we get the high part
1600 */
1601 if (0 == val) {
1602 s->device_active = false;
1603 }
1604 s->temp_shared_guest_driver_memory = val;
1605 s->drv_shmem = 0;
1606 break;
1607
1608 /* Driver Shared Address High */
1609 case VMXNET3_REG_DSAH:
1610 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1611 val, size);
1612 /*
1613 * Set the shared memory between guest driver and device.
1614 * We already should have low address part.
1615 */
1616 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1617 break;
1618
1619 /* Command */
1620 case VMXNET3_REG_CMD:
1621 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1622 val, size);
1623 vmxnet3_handle_command(s, val);
1624 break;
1625
1626 /* MAC Address Low */
1627 case VMXNET3_REG_MACL:
1628 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1629 val, size);
1630 s->temp_mac = val;
1631 break;
1632
1633 /* MAC Address High */
1634 case VMXNET3_REG_MACH:
1635 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1636 val, size);
1637 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1638 break;
1639
1640 /* Interrupt Cause Register */
1641 case VMXNET3_REG_ICR:
1642 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1643 val, size);
1644 assert(false);
1645 break;
1646
1647 /* Event Cause Register */
1648 case VMXNET3_REG_ECR:
1649 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1650 val, size);
1651 vmxnet3_ack_events(s, val);
1652 break;
1653
1654 default:
1655 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1656 addr, val, size);
1657 break;
1658 }
1659 }
1660
1661 static uint64_t
1662 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1663 {
1664 VMXNET3State *s = opaque;
1665 uint64_t ret = 0;
1666
1667 switch (addr) {
1668 /* Vmxnet3 Revision Report Selection */
1669 case VMXNET3_REG_VRRS:
1670 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1671 ret = VMXNET3_DEVICE_REVISION;
1672 break;
1673
1674 /* UPT Version Report Selection */
1675 case VMXNET3_REG_UVRS:
1676 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1677 ret = VMXNET3_DEVICE_VERSION;
1678 break;
1679
1680 /* Command */
1681 case VMXNET3_REG_CMD:
1682 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1683 ret = vmxnet3_get_command_status(s);
1684 break;
1685
1686 /* MAC Address Low */
1687 case VMXNET3_REG_MACL:
1688 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1689 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1690 break;
1691
1692 /* MAC Address High */
1693 case VMXNET3_REG_MACH:
1694 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1695 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1696 break;
1697
1698 /*
1699 * Interrupt Cause Register
1700 * Used for legacy interrupts only so interrupt index always 0
1701 */
1702 case VMXNET3_REG_ICR:
1703 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1704 if (vmxnet3_interrupt_asserted(s, 0)) {
1705 vmxnet3_clear_interrupt(s, 0);
1706 ret = true;
1707 } else {
1708 ret = false;
1709 }
1710 break;
1711
1712 default:
1713 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1714 break;
1715 }
1716
1717 return ret;
1718 }
1719
1720 static int
1721 vmxnet3_can_receive(NetClientState *nc)
1722 {
1723 VMXNET3State *s = qemu_get_nic_opaque(nc);
1724 return s->device_active &&
1725 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1726 }
1727
1728 static inline bool
1729 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1730 {
1731 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1732 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1733 return true;
1734 }
1735
1736 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1737 }
1738
1739 static bool
1740 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1741 {
1742 int i;
1743 for (i = 0; i < s->mcast_list_len; i++) {
1744 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1745 return true;
1746 }
1747 }
1748 return false;
1749 }
1750
1751 static bool
1752 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1753 size_t size)
1754 {
1755 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1756
1757 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1758 return true;
1759 }
1760
1761 if (!vmxnet3_is_registered_vlan(s, data)) {
1762 return false;
1763 }
1764
1765 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
1766 case ETH_PKT_UCAST:
1767 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1768 return false;
1769 }
1770 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1771 return false;
1772 }
1773 break;
1774
1775 case ETH_PKT_BCAST:
1776 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1777 return false;
1778 }
1779 break;
1780
1781 case ETH_PKT_MCAST:
1782 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1783 return true;
1784 }
1785 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1786 return false;
1787 }
1788 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1789 return false;
1790 }
1791 break;
1792
1793 default:
1794 assert(false);
1795 }
1796
1797 return true;
1798 }
1799
1800 static ssize_t
1801 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1802 {
1803 VMXNET3State *s = qemu_get_nic_opaque(nc);
1804 size_t bytes_indicated;
1805
1806 if (!vmxnet3_can_receive(nc)) {
1807 VMW_PKPRN("Cannot receive now");
1808 return -1;
1809 }
1810
1811 if (s->peer_has_vhdr) {
1812 vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
1813 buf += sizeof(struct virtio_net_hdr);
1814 size -= sizeof(struct virtio_net_hdr);
1815 }
1816
1817 vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
1818 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1819
1820 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
1821 vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
1822 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
1823 if (bytes_indicated < size) {
1824 VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated, size);
1825 }
1826 } else {
1827 VMW_PKPRN("Packet dropped by RX filter");
1828 bytes_indicated = size;
1829 }
1830
1831 assert(size > 0);
1832 assert(bytes_indicated != 0);
1833 return bytes_indicated;
1834 }
1835
1836 static void vmxnet3_cleanup(NetClientState *nc)
1837 {
1838 VMXNET3State *s = qemu_get_nic_opaque(nc);
1839 s->nic = NULL;
1840 }
1841
1842 static void vmxnet3_set_link_status(NetClientState *nc)
1843 {
1844 VMXNET3State *s = qemu_get_nic_opaque(nc);
1845
1846 if (nc->link_down) {
1847 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
1848 } else {
1849 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
1850 }
1851
1852 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
1853 vmxnet3_trigger_interrupt(s, s->event_int_idx);
1854 }
1855
1856 static NetClientInfo net_vmxnet3_info = {
1857 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1858 .size = sizeof(NICState),
1859 .can_receive = vmxnet3_can_receive,
1860 .receive = vmxnet3_receive,
1861 .cleanup = vmxnet3_cleanup,
1862 .link_status_changed = vmxnet3_set_link_status,
1863 };
1864
1865 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
1866 {
1867 NetClientState *peer = qemu_get_queue(s->nic)->peer;
1868
1869 if ((NULL != peer) &&
1870 (peer->info->type == NET_CLIENT_OPTIONS_KIND_TAP) &&
1871 tap_has_vnet_hdr(peer)) {
1872 return true;
1873 }
1874
1875 VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
1876 return false;
1877 }
1878
1879 static void vmxnet3_net_uninit(VMXNET3State *s)
1880 {
1881 g_free(s->mcast_list);
1882 vmxnet_tx_pkt_reset(s->tx_pkt);
1883 vmxnet_tx_pkt_uninit(s->tx_pkt);
1884 vmxnet_rx_pkt_uninit(s->rx_pkt);
1885 qemu_del_net_client(qemu_get_queue(s->nic));
1886 }
1887
1888 static void vmxnet3_net_init(VMXNET3State *s)
1889 {
1890 DeviceState *d = DEVICE(s);
1891
1892 VMW_CBPRN("vmxnet3_net_init called...");
1893
1894 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1895
1896 /* Windows guest will query the address that was set on init */
1897 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
1898
1899 s->mcast_list = NULL;
1900 s->mcast_list_len = 0;
1901
1902 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
1903
1904 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
1905
1906 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
1907 object_get_typename(OBJECT(s)),
1908 d->id, s);
1909
1910 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
1911 s->tx_sop = true;
1912 s->skip_current_tx_pkt = false;
1913 s->tx_pkt = NULL;
1914 s->rx_pkt = NULL;
1915 s->rx_vlan_stripping = false;
1916 s->lro_supported = false;
1917
1918 if (s->peer_has_vhdr) {
1919 tap_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
1920 sizeof(struct virtio_net_hdr));
1921
1922 tap_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
1923 }
1924
1925 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1926 }
1927
1928 static void
1929 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
1930 {
1931 PCIDevice *d = PCI_DEVICE(s);
1932 int i;
1933 for (i = 0; i < num_vectors; i++) {
1934 msix_vector_unuse(d, i);
1935 }
1936 }
1937
1938 static bool
1939 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
1940 {
1941 PCIDevice *d = PCI_DEVICE(s);
1942 int i;
1943 for (i = 0; i < num_vectors; i++) {
1944 int res = msix_vector_use(d, i);
1945 if (0 > res) {
1946 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
1947 vmxnet3_unuse_msix_vectors(s, i);
1948 return false;
1949 }
1950 }
1951 return true;
1952 }
1953
1954 static bool
1955 vmxnet3_init_msix(VMXNET3State *s)
1956 {
1957 PCIDevice *d = PCI_DEVICE(s);
1958 int res = msix_init(d, VMXNET3_MAX_INTRS,
1959 &s->msix_bar,
1960 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
1961 &s->msix_bar,
1962 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
1963 0);
1964
1965 if (0 > res) {
1966 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
1967 s->msix_used = false;
1968 } else {
1969 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
1970 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
1971 msix_uninit(d, &s->msix_bar, &s->msix_bar);
1972 s->msix_used = false;
1973 } else {
1974 s->msix_used = true;
1975 }
1976 }
1977 return s->msix_used;
1978 }
1979
1980 static void
1981 vmxnet3_cleanup_msix(VMXNET3State *s)
1982 {
1983 PCIDevice *d = PCI_DEVICE(s);
1984
1985 if (s->msix_used) {
1986 msix_vector_unuse(d, VMXNET3_MAX_INTRS);
1987 msix_uninit(d, &s->msix_bar, &s->msix_bar);
1988 }
1989 }
1990
1991 #define VMXNET3_MSI_NUM_VECTORS (1)
1992 #define VMXNET3_MSI_OFFSET (0x50)
1993 #define VMXNET3_USE_64BIT (true)
1994 #define VMXNET3_PER_VECTOR_MASK (false)
1995
1996 static bool
1997 vmxnet3_init_msi(VMXNET3State *s)
1998 {
1999 PCIDevice *d = PCI_DEVICE(s);
2000 int res;
2001
2002 res = msi_init(d, VMXNET3_MSI_OFFSET, VMXNET3_MSI_NUM_VECTORS,
2003 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK);
2004 if (0 > res) {
2005 VMW_WRPRN("Failed to initialize MSI, error %d", res);
2006 s->msi_used = false;
2007 } else {
2008 s->msi_used = true;
2009 }
2010
2011 return s->msi_used;
2012 }
2013
2014 static void
2015 vmxnet3_cleanup_msi(VMXNET3State *s)
2016 {
2017 PCIDevice *d = PCI_DEVICE(s);
2018
2019 if (s->msi_used) {
2020 msi_uninit(d);
2021 }
2022 }
2023
2024 static void
2025 vmxnet3_msix_save(QEMUFile *f, void *opaque)
2026 {
2027 PCIDevice *d = PCI_DEVICE(opaque);
2028 msix_save(d, f);
2029 }
2030
2031 static int
2032 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
2033 {
2034 PCIDevice *d = PCI_DEVICE(opaque);
2035 msix_load(d, f);
2036 return 0;
2037 }
2038
2039 static const MemoryRegionOps b0_ops = {
2040 .read = vmxnet3_io_bar0_read,
2041 .write = vmxnet3_io_bar0_write,
2042 .endianness = DEVICE_LITTLE_ENDIAN,
2043 .impl = {
2044 .min_access_size = 4,
2045 .max_access_size = 4,
2046 },
2047 };
2048
2049 static const MemoryRegionOps b1_ops = {
2050 .read = vmxnet3_io_bar1_read,
2051 .write = vmxnet3_io_bar1_write,
2052 .endianness = DEVICE_LITTLE_ENDIAN,
2053 .impl = {
2054 .min_access_size = 4,
2055 .max_access_size = 4,
2056 },
2057 };
2058
2059 static int vmxnet3_pci_init(PCIDevice *pci_dev)
2060 {
2061 DeviceState *dev = DEVICE(pci_dev);
2062 VMXNET3State *s = VMXNET3(pci_dev);
2063
2064 VMW_CBPRN("Starting init...");
2065
2066 memory_region_init_io(&s->bar0, &b0_ops, s,
2067 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2068 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2069 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2070
2071 memory_region_init_io(&s->bar1, &b1_ops, s,
2072 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2073 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2074 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2075
2076 memory_region_init(&s->msix_bar, "vmxnet3-msix-bar",
2077 VMXNET3_MSIX_BAR_SIZE);
2078 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2079 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2080
2081 vmxnet3_reset_interrupt_states(s);
2082
2083 /* Interrupt pin A */
2084 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2085
2086 if (!vmxnet3_init_msix(s)) {
2087 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2088 }
2089
2090 if (!vmxnet3_init_msi(s)) {
2091 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2092 }
2093
2094 vmxnet3_net_init(s);
2095
2096 register_savevm(dev, "vmxnet3-msix", -1, 1,
2097 vmxnet3_msix_save, vmxnet3_msix_load, s);
2098
2099 add_boot_device_path(s->conf.bootindex, dev, "/ethernet-phy@0");
2100
2101 return 0;
2102 }
2103
2104
2105 static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2106 {
2107 DeviceState *dev = DEVICE(pci_dev);
2108 VMXNET3State *s = VMXNET3(pci_dev);
2109
2110 VMW_CBPRN("Starting uninit...");
2111
2112 unregister_savevm(dev, "vmxnet3-msix", s);
2113
2114 vmxnet3_net_uninit(s);
2115
2116 vmxnet3_cleanup_msix(s);
2117
2118 vmxnet3_cleanup_msi(s);
2119
2120 memory_region_destroy(&s->bar0);
2121 memory_region_destroy(&s->bar1);
2122 memory_region_destroy(&s->msix_bar);
2123 }
2124
2125 static void vmxnet3_qdev_reset(DeviceState *dev)
2126 {
2127 PCIDevice *d = PCI_DEVICE(dev);
2128 VMXNET3State *s = VMXNET3(d);
2129
2130 VMW_CBPRN("Starting QDEV reset...");
2131 vmxnet3_reset(s);
2132 }
2133
2134 static bool vmxnet3_mc_list_needed(void *opaque)
2135 {
2136 return true;
2137 }
2138
2139 static int vmxnet3_mcast_list_pre_load(void *opaque)
2140 {
2141 VMXNET3State *s = opaque;
2142
2143 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2144
2145 return 0;
2146 }
2147
2148
2149 static void vmxnet3_pre_save(void *opaque)
2150 {
2151 VMXNET3State *s = opaque;
2152
2153 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2154 }
2155
2156 static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2157 .name = "vmxnet3/mcast_list",
2158 .version_id = 1,
2159 .minimum_version_id = 1,
2160 .minimum_version_id_old = 1,
2161 .pre_load = vmxnet3_mcast_list_pre_load,
2162 .fields = (VMStateField[]) {
2163 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 0,
2164 mcast_list_buff_size),
2165 VMSTATE_END_OF_LIST()
2166 }
2167 };
2168
2169 static void vmxnet3_get_ring_from_file(QEMUFile *f, Vmxnet3Ring *r)
2170 {
2171 r->pa = qemu_get_be64(f);
2172 r->size = qemu_get_be32(f);
2173 r->cell_size = qemu_get_be32(f);
2174 r->next = qemu_get_be32(f);
2175 r->gen = qemu_get_byte(f);
2176 }
2177
2178 static void vmxnet3_put_ring_to_file(QEMUFile *f, Vmxnet3Ring *r)
2179 {
2180 qemu_put_be64(f, r->pa);
2181 qemu_put_be32(f, r->size);
2182 qemu_put_be32(f, r->cell_size);
2183 qemu_put_be32(f, r->next);
2184 qemu_put_byte(f, r->gen);
2185 }
2186
2187 static void vmxnet3_get_tx_stats_from_file(QEMUFile *f,
2188 struct UPT1_TxStats *tx_stat)
2189 {
2190 tx_stat->TSOPktsTxOK = qemu_get_be64(f);
2191 tx_stat->TSOBytesTxOK = qemu_get_be64(f);
2192 tx_stat->ucastPktsTxOK = qemu_get_be64(f);
2193 tx_stat->ucastBytesTxOK = qemu_get_be64(f);
2194 tx_stat->mcastPktsTxOK = qemu_get_be64(f);
2195 tx_stat->mcastBytesTxOK = qemu_get_be64(f);
2196 tx_stat->bcastPktsTxOK = qemu_get_be64(f);
2197 tx_stat->bcastBytesTxOK = qemu_get_be64(f);
2198 tx_stat->pktsTxError = qemu_get_be64(f);
2199 tx_stat->pktsTxDiscard = qemu_get_be64(f);
2200 }
2201
2202 static void vmxnet3_put_tx_stats_to_file(QEMUFile *f,
2203 struct UPT1_TxStats *tx_stat)
2204 {
2205 qemu_put_be64(f, tx_stat->TSOPktsTxOK);
2206 qemu_put_be64(f, tx_stat->TSOBytesTxOK);
2207 qemu_put_be64(f, tx_stat->ucastPktsTxOK);
2208 qemu_put_be64(f, tx_stat->ucastBytesTxOK);
2209 qemu_put_be64(f, tx_stat->mcastPktsTxOK);
2210 qemu_put_be64(f, tx_stat->mcastBytesTxOK);
2211 qemu_put_be64(f, tx_stat->bcastPktsTxOK);
2212 qemu_put_be64(f, tx_stat->bcastBytesTxOK);
2213 qemu_put_be64(f, tx_stat->pktsTxError);
2214 qemu_put_be64(f, tx_stat->pktsTxDiscard);
2215 }
2216
2217 static int vmxnet3_get_txq_descr(QEMUFile *f, void *pv, size_t size)
2218 {
2219 Vmxnet3TxqDescr *r = pv;
2220
2221 vmxnet3_get_ring_from_file(f, &r->tx_ring);
2222 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2223 r->intr_idx = qemu_get_byte(f);
2224 r->tx_stats_pa = qemu_get_be64(f);
2225
2226 vmxnet3_get_tx_stats_from_file(f, &r->txq_stats);
2227
2228 return 0;
2229 }
2230
2231 static void vmxnet3_put_txq_descr(QEMUFile *f, void *pv, size_t size)
2232 {
2233 Vmxnet3TxqDescr *r = pv;
2234
2235 vmxnet3_put_ring_to_file(f, &r->tx_ring);
2236 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2237 qemu_put_byte(f, r->intr_idx);
2238 qemu_put_be64(f, r->tx_stats_pa);
2239 vmxnet3_put_tx_stats_to_file(f, &r->txq_stats);
2240 }
2241
2242 const VMStateInfo txq_descr_info = {
2243 .name = "txq_descr",
2244 .get = vmxnet3_get_txq_descr,
2245 .put = vmxnet3_put_txq_descr
2246 };
2247
2248 static void vmxnet3_get_rx_stats_from_file(QEMUFile *f,
2249 struct UPT1_RxStats *rx_stat)
2250 {
2251 rx_stat->LROPktsRxOK = qemu_get_be64(f);
2252 rx_stat->LROBytesRxOK = qemu_get_be64(f);
2253 rx_stat->ucastPktsRxOK = qemu_get_be64(f);
2254 rx_stat->ucastBytesRxOK = qemu_get_be64(f);
2255 rx_stat->mcastPktsRxOK = qemu_get_be64(f);
2256 rx_stat->mcastBytesRxOK = qemu_get_be64(f);
2257 rx_stat->bcastPktsRxOK = qemu_get_be64(f);
2258 rx_stat->bcastBytesRxOK = qemu_get_be64(f);
2259 rx_stat->pktsRxOutOfBuf = qemu_get_be64(f);
2260 rx_stat->pktsRxError = qemu_get_be64(f);
2261 }
2262
2263 static void vmxnet3_put_rx_stats_to_file(QEMUFile *f,
2264 struct UPT1_RxStats *rx_stat)
2265 {
2266 qemu_put_be64(f, rx_stat->LROPktsRxOK);
2267 qemu_put_be64(f, rx_stat->LROBytesRxOK);
2268 qemu_put_be64(f, rx_stat->ucastPktsRxOK);
2269 qemu_put_be64(f, rx_stat->ucastBytesRxOK);
2270 qemu_put_be64(f, rx_stat->mcastPktsRxOK);
2271 qemu_put_be64(f, rx_stat->mcastBytesRxOK);
2272 qemu_put_be64(f, rx_stat->bcastPktsRxOK);
2273 qemu_put_be64(f, rx_stat->bcastBytesRxOK);
2274 qemu_put_be64(f, rx_stat->pktsRxOutOfBuf);
2275 qemu_put_be64(f, rx_stat->pktsRxError);
2276 }
2277
2278 static int vmxnet3_get_rxq_descr(QEMUFile *f, void *pv, size_t size)
2279 {
2280 Vmxnet3RxqDescr *r = pv;
2281 int i;
2282
2283 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2284 vmxnet3_get_ring_from_file(f, &r->rx_ring[i]);
2285 }
2286
2287 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2288 r->intr_idx = qemu_get_byte(f);
2289 r->rx_stats_pa = qemu_get_be64(f);
2290
2291 vmxnet3_get_rx_stats_from_file(f, &r->rxq_stats);
2292
2293 return 0;
2294 }
2295
2296 static void vmxnet3_put_rxq_descr(QEMUFile *f, void *pv, size_t size)
2297 {
2298 Vmxnet3RxqDescr *r = pv;
2299 int i;
2300
2301 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2302 vmxnet3_put_ring_to_file(f, &r->rx_ring[i]);
2303 }
2304
2305 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2306 qemu_put_byte(f, r->intr_idx);
2307 qemu_put_be64(f, r->rx_stats_pa);
2308 vmxnet3_put_rx_stats_to_file(f, &r->rxq_stats);
2309 }
2310
2311 static int vmxnet3_post_load(void *opaque, int version_id)
2312 {
2313 VMXNET3State *s = opaque;
2314 PCIDevice *d = PCI_DEVICE(s);
2315
2316 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
2317 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
2318
2319 if (s->msix_used) {
2320 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2321 VMW_WRPRN("Failed to re-use MSI-X vectors");
2322 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2323 s->msix_used = false;
2324 return -1;
2325 }
2326 }
2327
2328 return 0;
2329 }
2330
2331 const VMStateInfo rxq_descr_info = {
2332 .name = "rxq_descr",
2333 .get = vmxnet3_get_rxq_descr,
2334 .put = vmxnet3_put_rxq_descr
2335 };
2336
2337 static int vmxnet3_get_int_state(QEMUFile *f, void *pv, size_t size)
2338 {
2339 Vmxnet3IntState *r = pv;
2340
2341 r->is_masked = qemu_get_byte(f);
2342 r->is_pending = qemu_get_byte(f);
2343 r->is_asserted = qemu_get_byte(f);
2344
2345 return 0;
2346 }
2347
2348 static void vmxnet3_put_int_state(QEMUFile *f, void *pv, size_t size)
2349 {
2350 Vmxnet3IntState *r = pv;
2351
2352 qemu_put_byte(f, r->is_masked);
2353 qemu_put_byte(f, r->is_pending);
2354 qemu_put_byte(f, r->is_asserted);
2355 }
2356
2357 const VMStateInfo int_state_info = {
2358 .name = "int_state",
2359 .get = vmxnet3_get_int_state,
2360 .put = vmxnet3_put_int_state
2361 };
2362
2363 static const VMStateDescription vmstate_vmxnet3 = {
2364 .name = "vmxnet3",
2365 .version_id = 1,
2366 .minimum_version_id = 1,
2367 .minimum_version_id_old = 1,
2368 .pre_save = vmxnet3_pre_save,
2369 .post_load = vmxnet3_post_load,
2370 .fields = (VMStateField[]) {
2371 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
2372 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2373 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2374 VMSTATE_BOOL(lro_supported, VMXNET3State),
2375 VMSTATE_UINT32(rx_mode, VMXNET3State),
2376 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2377 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2378 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2379 VMSTATE_UINT32(mtu, VMXNET3State),
2380 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2381 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2382 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2383 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2384 VMSTATE_UINT8(txq_num, VMXNET3State),
2385 VMSTATE_UINT8(rxq_num, VMXNET3State),
2386 VMSTATE_UINT32(device_active, VMXNET3State),
2387 VMSTATE_UINT32(last_command, VMXNET3State),
2388 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2389 VMSTATE_UINT32(temp_mac, VMXNET3State),
2390 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2391 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2392
2393 VMSTATE_ARRAY(txq_descr, VMXNET3State,
2394 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, txq_descr_info,
2395 Vmxnet3TxqDescr),
2396 VMSTATE_ARRAY(rxq_descr, VMXNET3State,
2397 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, rxq_descr_info,
2398 Vmxnet3RxqDescr),
2399 VMSTATE_ARRAY(interrupt_states, VMXNET3State, VMXNET3_MAX_INTRS,
2400 0, int_state_info, Vmxnet3IntState),
2401
2402 VMSTATE_END_OF_LIST()
2403 },
2404 .subsections = (VMStateSubsection[]) {
2405 {
2406 .vmsd = &vmxstate_vmxnet3_mcast_list,
2407 .needed = vmxnet3_mc_list_needed
2408 },
2409 {
2410 /* empty element. */
2411 }
2412 }
2413 };
2414
2415 static void
2416 vmxnet3_write_config(PCIDevice *pci_dev, uint32_t addr, uint32_t val, int len)
2417 {
2418 pci_default_write_config(pci_dev, addr, val, len);
2419 msix_write_config(pci_dev, addr, val, len);
2420 msi_write_config(pci_dev, addr, val, len);
2421 }
2422
2423 static Property vmxnet3_properties[] = {
2424 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2425 DEFINE_PROP_END_OF_LIST(),
2426 };
2427
2428 static void vmxnet3_class_init(ObjectClass *class, void *data)
2429 {
2430 DeviceClass *dc = DEVICE_CLASS(class);
2431 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2432
2433 c->init = vmxnet3_pci_init;
2434 c->exit = vmxnet3_pci_uninit;
2435 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2436 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2437 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2438 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2439 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2440 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2441 c->config_write = vmxnet3_write_config,
2442 dc->desc = "VMWare Paravirtualized Ethernet v3";
2443 dc->reset = vmxnet3_qdev_reset;
2444 dc->vmsd = &vmstate_vmxnet3;
2445 dc->props = vmxnet3_properties;
2446 }
2447
2448 static const TypeInfo vmxnet3_info = {
2449 .name = TYPE_VMXNET3,
2450 .parent = TYPE_PCI_DEVICE,
2451 .instance_size = sizeof(VMXNET3State),
2452 .class_init = vmxnet3_class_init,
2453 };
2454
2455 static void vmxnet3_register_types(void)
2456 {
2457 VMW_CBPRN("vmxnet3_register_types called...");
2458 type_register_static(&vmxnet3_info);
2459 }
2460
2461 type_init(vmxnet3_register_types)