linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / vt82c686.c
1 /*
2 * VT82C686B south bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "hw.h"
14 #include "pc.h"
15 #include "vt82c686.h"
16 #include "i2c.h"
17 #include "smbus.h"
18 #include "pci.h"
19 #include "isa.h"
20 #include "sysbus.h"
21 #include "mips.h"
22 #include "apm.h"
23 #include "acpi.h"
24 #include "pm_smbus.h"
25 #include "sysemu.h"
26 #include "qemu-timer.h"
27
28 typedef uint32_t pci_addr_t;
29 #include "pci_host.h"
30 //#define DEBUG_VT82C686B
31
32 #ifdef DEBUG_VT82C686B
33 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
34 #else
35 #define DPRINTF(fmt, ...)
36 #endif
37
38 typedef struct SuperIOConfig
39 {
40 uint8_t config[0xff];
41 uint8_t index;
42 uint8_t data;
43 } SuperIOConfig;
44
45 typedef struct VT82C686BState {
46 PCIDevice dev;
47 SuperIOConfig superio_conf;
48 } VT82C686BState;
49
50 static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
51 {
52 int can_write;
53 SuperIOConfig *superio_conf = opaque;
54
55 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
56 if (addr == 0x3f0) {
57 superio_conf->index = data & 0xff;
58 } else {
59 /* 0x3f1 */
60 switch (superio_conf->index) {
61 case 0x00 ... 0xdf:
62 case 0xe4:
63 case 0xe5:
64 case 0xe9 ... 0xed:
65 case 0xf3:
66 case 0xf5:
67 case 0xf7:
68 case 0xf9 ... 0xfb:
69 case 0xfd ... 0xff:
70 can_write = 0;
71 break;
72 default:
73 can_write = 1;
74
75 if (can_write) {
76 switch (superio_conf->index) {
77 case 0xe7:
78 if ((data & 0xff) != 0xfe) {
79 DPRINTF("chage uart 1 base. unsupported yet\n");
80 }
81 break;
82 case 0xe8:
83 if ((data & 0xff) != 0xbe) {
84 DPRINTF("chage uart 2 base. unsupported yet\n");
85 }
86 break;
87
88 default:
89 superio_conf->config[superio_conf->index] = data & 0xff;
90 }
91 }
92 }
93 superio_conf->config[superio_conf->index] = data & 0xff;
94 }
95 }
96
97 static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
98 {
99 SuperIOConfig *superio_conf = opaque;
100
101 DPRINTF("superio_ioport_readb address 0x%x\n", addr);
102 return (superio_conf->config[superio_conf->index]);
103 }
104
105 static void vt82c686b_reset(void * opaque)
106 {
107 PCIDevice *d = opaque;
108 uint8_t *pci_conf = d->config;
109 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
110
111 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
112 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
113 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
114 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
115
116 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
117 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
118 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
119 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
120 pci_conf[0x59] = 0x04;
121 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
122 pci_conf[0x5f] = 0x04;
123 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
124
125 vt82c->superio_conf.config[0xe0] = 0x3c;
126 vt82c->superio_conf.config[0xe2] = 0x03;
127 vt82c->superio_conf.config[0xe3] = 0xfc;
128 vt82c->superio_conf.config[0xe6] = 0xde;
129 vt82c->superio_conf.config[0xe7] = 0xfe;
130 vt82c->superio_conf.config[0xe8] = 0xbe;
131 }
132
133 /* write config pci function0 registers. PCI-ISA bridge */
134 static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
135 uint32_t val, int len)
136 {
137 VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
138
139 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
140 address, val, len);
141
142 pci_default_write_config(d, address, val, len);
143 if (address == 0x85) { /* enable or disable super IO configure */
144 if (val & 0x2) {
145 /* floppy also uses 0x3f0 and 0x3f1.
146 * But we do not emulate flopy,so just set it here. */
147 isa_unassign_ioport(0x3f0, 2);
148 register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
149 &vt686->superio_conf);
150 register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
151 &vt686->superio_conf);
152 } else {
153 isa_unassign_ioport(0x3f0, 2);
154 }
155 }
156 }
157
158 #define ACPI_DBG_IO_ADDR 0xb044
159
160 typedef struct VT686PMState {
161 PCIDevice dev;
162 ACPIPM1EVT pm1a;
163 ACPIPM1CNT pm1_cnt;
164 APMState apm;
165 ACPIPMTimer tmr;
166 PMSMBus smb;
167 uint32_t smb_io_base;
168 } VT686PMState;
169
170 typedef struct VT686AC97State {
171 PCIDevice dev;
172 } VT686AC97State;
173
174 typedef struct VT686MC97State {
175 PCIDevice dev;
176 } VT686MC97State;
177
178 static void pm_update_sci(VT686PMState *s)
179 {
180 int sci_level, pmsts;
181
182 pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
183 sci_level = (((pmsts & s->pm1a.en) &
184 (ACPI_BITMASK_RT_CLOCK_ENABLE |
185 ACPI_BITMASK_POWER_BUTTON_ENABLE |
186 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
187 ACPI_BITMASK_TIMER_ENABLE)) != 0);
188 qemu_set_irq(s->dev.irq[0], sci_level);
189 /* schedule a timer interruption if needed */
190 acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
191 !(pmsts & ACPI_BITMASK_TIMER_STATUS));
192 }
193
194 static void pm_tmr_timer(ACPIPMTimer *tmr)
195 {
196 VT686PMState *s = container_of(tmr, VT686PMState, tmr);
197 pm_update_sci(s);
198 }
199
200 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
201 {
202 VT686PMState *s = opaque;
203
204 addr &= 0x0f;
205 switch (addr) {
206 case 0x00:
207 acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
208 pm_update_sci(s);
209 break;
210 case 0x02:
211 s->pm1a.en = val;
212 pm_update_sci(s);
213 break;
214 case 0x04:
215 acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
216 break;
217 default:
218 break;
219 }
220 DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
221 }
222
223 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
224 {
225 VT686PMState *s = opaque;
226 uint32_t val;
227
228 addr &= 0x0f;
229 switch (addr) {
230 case 0x00:
231 val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
232 break;
233 case 0x02:
234 val = s->pm1a.en;
235 break;
236 case 0x04:
237 val = s->pm1_cnt.cnt;
238 break;
239 default:
240 val = 0;
241 break;
242 }
243 DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
244 return val;
245 }
246
247 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
248 {
249 addr &= 0x0f;
250 DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
251 }
252
253 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
254 {
255 VT686PMState *s = opaque;
256 uint32_t val;
257
258 addr &= 0x0f;
259 switch (addr) {
260 case 0x08:
261 val = acpi_pm_tmr_get(&s->tmr);
262 break;
263 default:
264 val = 0;
265 break;
266 }
267 DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
268 return val;
269 }
270
271 static void pm_io_space_update(VT686PMState *s)
272 {
273 uint32_t pm_io_base;
274
275 if (s->dev.config[0x80] & 1) {
276 pm_io_base = pci_get_long(s->dev.config + 0x40);
277 pm_io_base &= 0xffc0;
278
279 /* XXX: need to improve memory and ioport allocation */
280 DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
281 register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
282 register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
283 register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
284 register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
285 }
286 }
287
288 static void pm_write_config(PCIDevice *d,
289 uint32_t address, uint32_t val, int len)
290 {
291 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
292 address, val, len);
293 pci_default_write_config(d, address, val, len);
294 }
295
296 static int vmstate_acpi_post_load(void *opaque, int version_id)
297 {
298 VT686PMState *s = opaque;
299
300 pm_io_space_update(s);
301 return 0;
302 }
303
304 static const VMStateDescription vmstate_acpi = {
305 .name = "vt82c686b_pm",
306 .version_id = 1,
307 .minimum_version_id = 1,
308 .minimum_version_id_old = 1,
309 .post_load = vmstate_acpi_post_load,
310 .fields = (VMStateField []) {
311 VMSTATE_PCI_DEVICE(dev, VT686PMState),
312 VMSTATE_UINT16(pm1a.sts, VT686PMState),
313 VMSTATE_UINT16(pm1a.en, VT686PMState),
314 VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState),
315 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
316 VMSTATE_TIMER(tmr.timer, VT686PMState),
317 VMSTATE_INT64(tmr.overflow_time, VT686PMState),
318 VMSTATE_END_OF_LIST()
319 }
320 };
321
322 /*
323 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
324 * just register a PCI device now, functionalities will be implemented later.
325 */
326
327 static int vt82c686b_ac97_initfn(PCIDevice *dev)
328 {
329 VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
330 uint8_t *pci_conf = s->dev.config;
331
332 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
333 PCI_COMMAND_PARITY);
334 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
335 PCI_STATUS_DEVSEL_MEDIUM);
336 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
337
338 return 0;
339 }
340
341 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
342 {
343 PCIDevice *dev;
344
345 dev = pci_create(bus, devfn, "VT82C686B_AC97");
346 qdev_init_nofail(&dev->qdev);
347 }
348
349 static void via_ac97_class_init(ObjectClass *klass, void *data)
350 {
351 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
352
353 k->init = vt82c686b_ac97_initfn;
354 k->vendor_id = PCI_VENDOR_ID_VIA;
355 k->device_id = PCI_DEVICE_ID_VIA_AC97;
356 k->revision = 0x50;
357 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
358 }
359
360 static DeviceInfo via_ac97_info = {
361 .name = "VT82C686B_AC97",
362 .desc = "AC97",
363 .size = sizeof(VT686AC97State),
364 .class_init = via_ac97_class_init,
365 };
366
367 static void vt82c686b_ac97_register(void)
368 {
369 pci_qdev_register(&via_ac97_info);
370 }
371
372 device_init(vt82c686b_ac97_register);
373
374 static int vt82c686b_mc97_initfn(PCIDevice *dev)
375 {
376 VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
377 uint8_t *pci_conf = s->dev.config;
378
379 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
380 PCI_COMMAND_VGA_PALETTE);
381 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
382 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
383
384 return 0;
385 }
386
387 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
388 {
389 PCIDevice *dev;
390
391 dev = pci_create(bus, devfn, "VT82C686B_MC97");
392 qdev_init_nofail(&dev->qdev);
393 }
394
395 static void via_mc97_class_init(ObjectClass *klass, void *data)
396 {
397 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
398
399 k->init = vt82c686b_mc97_initfn;
400 k->vendor_id = PCI_VENDOR_ID_VIA;
401 k->device_id = PCI_DEVICE_ID_VIA_MC97;
402 k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
403 k->revision = 0x30;
404 }
405
406 static DeviceInfo via_mc97_info = {
407 .name = "VT82C686B_MC97",
408 .desc = "MC97",
409 .size = sizeof(VT686MC97State),
410 .class_init = via_mc97_class_init,
411 };
412
413 static void vt82c686b_mc97_register(void)
414 {
415 pci_qdev_register(&via_mc97_info);
416 }
417
418 device_init(vt82c686b_mc97_register);
419
420 /* vt82c686 pm init */
421 static int vt82c686b_pm_initfn(PCIDevice *dev)
422 {
423 VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
424 uint8_t *pci_conf;
425
426 pci_conf = s->dev.config;
427 pci_set_word(pci_conf + PCI_COMMAND, 0);
428 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
429 PCI_STATUS_DEVSEL_MEDIUM);
430
431 /* 0x48-0x4B is Power Management I/O Base */
432 pci_set_long(pci_conf + 0x48, 0x00000001);
433
434 /* SMB ports:0xeee0~0xeeef */
435 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
436 pci_conf[0x90] = s->smb_io_base | 1;
437 pci_conf[0x91] = s->smb_io_base >> 8;
438 pci_conf[0xd2] = 0x90;
439 register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
440 register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
441
442 apm_init(&s->apm, NULL, s);
443
444 acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
445 acpi_pm1_cnt_init(&s->pm1_cnt, NULL);
446
447 pm_smbus_init(&s->dev.qdev, &s->smb);
448
449 return 0;
450 }
451
452 i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
453 qemu_irq sci_irq)
454 {
455 PCIDevice *dev;
456 VT686PMState *s;
457
458 dev = pci_create(bus, devfn, "VT82C686B_PM");
459 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
460
461 s = DO_UPCAST(VT686PMState, dev, dev);
462
463 qdev_init_nofail(&dev->qdev);
464
465 return s->smb.smbus;
466 }
467
468 static Property via_pm_properties[] = {
469 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
470 DEFINE_PROP_END_OF_LIST(),
471 };
472
473 static void via_pm_class_init(ObjectClass *klass, void *data)
474 {
475 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
476
477 k->init = vt82c686b_pm_initfn;
478 k->config_write = pm_write_config;
479 k->vendor_id = PCI_VENDOR_ID_VIA;
480 k->device_id = PCI_DEVICE_ID_VIA_ACPI;
481 k->class_id = PCI_CLASS_BRIDGE_OTHER;
482 k->revision = 0x40;
483 }
484
485 static DeviceInfo via_pm_info = {
486 .name = "VT82C686B_PM",
487 .desc = "PM",
488 .size = sizeof(VT686PMState),
489 .vmsd = &vmstate_acpi,
490 .props = via_pm_properties,
491 .class_init = via_pm_class_init,
492 };
493
494 static void vt82c686b_pm_register(void)
495 {
496 pci_qdev_register(&via_pm_info);
497 }
498
499 device_init(vt82c686b_pm_register);
500
501 static const VMStateDescription vmstate_via = {
502 .name = "vt82c686b",
503 .version_id = 1,
504 .minimum_version_id = 1,
505 .minimum_version_id_old = 1,
506 .fields = (VMStateField []) {
507 VMSTATE_PCI_DEVICE(dev, VT82C686BState),
508 VMSTATE_END_OF_LIST()
509 }
510 };
511
512 /* init the PCI-to-ISA bridge */
513 static int vt82c686b_initfn(PCIDevice *d)
514 {
515 uint8_t *pci_conf;
516 uint8_t *wmask;
517 int i;
518
519 isa_bus_new(&d->qdev, pci_address_space_io(d));
520
521 pci_conf = d->config;
522 pci_config_set_prog_interface(pci_conf, 0x0);
523
524 wmask = d->wmask;
525 for (i = 0x00; i < 0xff; i++) {
526 if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
527 wmask[i] = 0x00;
528 }
529 }
530
531 qemu_register_reset(vt82c686b_reset, d);
532
533 return 0;
534 }
535
536 ISABus *vt82c686b_init(PCIBus *bus, int devfn)
537 {
538 PCIDevice *d;
539
540 d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
541
542 return DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0"));
543 }
544
545 static void via_class_init(ObjectClass *klass, void *data)
546 {
547 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
548
549 k->init = vt82c686b_initfn;
550 k->config_write = vt82c686b_write_config;
551 k->vendor_id = PCI_VENDOR_ID_VIA;
552 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
553 k->class_id = PCI_CLASS_BRIDGE_ISA;
554 k->revision = 0x40;
555 }
556
557 static DeviceInfo via_info = {
558 .name = "VT82C686B",
559 .desc = "ISA bridge",
560 .size = sizeof(VT82C686BState),
561 .vmsd = &vmstate_via,
562 .no_user = 1,
563 .class_init = via_class_init,
564 };
565
566 static void vt82c686b_register(void)
567 {
568 pci_qdev_register(&via_info);
569 }
570 device_init(vt82c686b_register);