capstone: Update to upstream "next" branch
[qemu.git] / hw / watchdog / cmsdk-apb-watchdog.c
1 /*
2 * ARM CMSDK APB watchdog emulation
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /*
13 * This is a model of the "APB watchdog" which is part of the Cortex-M
14 * System Design Kit (CMSDK) and documented in the Cortex-M System
15 * Design Kit Technical Reference Manual (ARM DDI0479C):
16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
17 *
18 * We also support the variant of this device found in the TI
19 * Stellaris/Luminary boards and documented in:
20 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/log.h"
25 #include "trace.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "sysemu/watchdog.h"
29 #include "hw/sysbus.h"
30 #include "hw/irq.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/registerfields.h"
33 #include "hw/watchdog/cmsdk-apb-watchdog.h"
34 #include "migration/vmstate.h"
35
36 REG32(WDOGLOAD, 0x0)
37 REG32(WDOGVALUE, 0x4)
38 REG32(WDOGCONTROL, 0x8)
39 FIELD(WDOGCONTROL, INTEN, 0, 1)
40 FIELD(WDOGCONTROL, RESEN, 1, 1)
41 #define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \
42 R_WDOGCONTROL_RESEN_MASK)
43 REG32(WDOGINTCLR, 0xc)
44 REG32(WDOGRIS, 0x10)
45 FIELD(WDOGRIS, INT, 0, 1)
46 REG32(WDOGMIS, 0x14)
47 REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */
48 REG32(WDOGLOCK, 0xc00)
49 #define WDOG_UNLOCK_VALUE 0x1ACCE551
50 REG32(WDOGITCR, 0xf00)
51 FIELD(WDOGITCR, ENABLE, 0, 1)
52 #define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK
53 REG32(WDOGITOP, 0xf04)
54 FIELD(WDOGITOP, WDOGRES, 0, 1)
55 FIELD(WDOGITOP, WDOGINT, 1, 1)
56 #define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \
57 R_WDOGITOP_WDOGINT_MASK)
58 REG32(PID4, 0xfd0)
59 REG32(PID5, 0xfd4)
60 REG32(PID6, 0xfd8)
61 REG32(PID7, 0xfdc)
62 REG32(PID0, 0xfe0)
63 REG32(PID1, 0xfe4)
64 REG32(PID2, 0xfe8)
65 REG32(PID3, 0xfec)
66 REG32(CID0, 0xff0)
67 REG32(CID1, 0xff4)
68 REG32(CID2, 0xff8)
69 REG32(CID3, 0xffc)
70
71 /* PID/CID values */
72 static const uint32_t cmsdk_apb_watchdog_id[] = {
73 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
74 0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
75 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
76 };
77
78 static const uint32_t luminary_watchdog_id[] = {
79 0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */
80 0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */
81 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
82 };
83
84 static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)
85 {
86 /* Return masked interrupt status */
87 return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK);
88 }
89
90 static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s)
91 {
92 /* Return masked reset status */
93 return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK);
94 }
95
96 static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)
97 {
98 bool wdogint;
99 bool wdogres;
100
101 if (s->itcr) {
102 /*
103 * Not checking that !s->is_luminary since s->itcr can't be written
104 * when s->is_luminary in the first place.
105 */
106 wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;
107 wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;
108 } else {
109 wdogint = cmsdk_apb_watchdog_intstatus(s);
110 wdogres = cmsdk_apb_watchdog_resetstatus(s);
111 }
112
113 qemu_set_irq(s->wdogint, wdogint);
114 if (wdogres) {
115 watchdog_perform_action();
116 }
117 }
118
119 static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,
120 unsigned size)
121 {
122 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
123 uint64_t r;
124
125 switch (offset) {
126 case A_WDOGLOAD:
127 r = ptimer_get_limit(s->timer);
128 break;
129 case A_WDOGVALUE:
130 r = ptimer_get_count(s->timer);
131 break;
132 case A_WDOGCONTROL:
133 r = s->control;
134 break;
135 case A_WDOGRIS:
136 r = s->intstatus;
137 break;
138 case A_WDOGMIS:
139 r = cmsdk_apb_watchdog_intstatus(s);
140 break;
141 case A_WDOGLOCK:
142 r = s->lock;
143 break;
144 case A_WDOGITCR:
145 if (s->is_luminary) {
146 goto bad_offset;
147 }
148 r = s->itcr;
149 break;
150 case A_PID4 ... A_CID3:
151 r = s->id[(offset - A_PID4) / 4];
152 break;
153 case A_WDOGINTCLR:
154 case A_WDOGITOP:
155 if (s->is_luminary) {
156 goto bad_offset;
157 }
158 qemu_log_mask(LOG_GUEST_ERROR,
159 "CMSDK APB watchdog read: read of WO offset %x\n",
160 (int)offset);
161 r = 0;
162 break;
163 case A_WDOGTEST:
164 if (!s->is_luminary) {
165 goto bad_offset;
166 }
167 qemu_log_mask(LOG_UNIMP,
168 "Luminary watchdog read: stall not implemented\n");
169 r = 0;
170 break;
171 default:
172 bad_offset:
173 qemu_log_mask(LOG_GUEST_ERROR,
174 "CMSDK APB watchdog read: bad offset %x\n", (int)offset);
175 r = 0;
176 break;
177 }
178 trace_cmsdk_apb_watchdog_read(offset, r, size);
179 return r;
180 }
181
182 static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
183 uint64_t value, unsigned size)
184 {
185 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
186
187 trace_cmsdk_apb_watchdog_write(offset, value, size);
188
189 if (s->lock && offset != A_WDOGLOCK) {
190 /* Write access is disabled via WDOGLOCK */
191 qemu_log_mask(LOG_GUEST_ERROR,
192 "CMSDK APB watchdog write: write to locked watchdog\n");
193 return;
194 }
195
196 switch (offset) {
197 case A_WDOGLOAD:
198 /*
199 * Reset the load value and the current count, and make sure
200 * we're counting.
201 */
202 ptimer_transaction_begin(s->timer);
203 ptimer_set_limit(s->timer, value, 1);
204 ptimer_run(s->timer, 0);
205 ptimer_transaction_commit(s->timer);
206 break;
207 case A_WDOGCONTROL:
208 if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) {
209 /*
210 * The Luminary version of this device ignores writes to
211 * this register after the guest has enabled interrupts
212 * (so they can only be disabled again via reset).
213 */
214 break;
215 }
216 s->control = value & R_WDOGCONTROL_VALID_MASK;
217 cmsdk_apb_watchdog_update(s);
218 break;
219 case A_WDOGINTCLR:
220 s->intstatus = 0;
221 ptimer_transaction_begin(s->timer);
222 ptimer_set_count(s->timer, ptimer_get_limit(s->timer));
223 ptimer_transaction_commit(s->timer);
224 cmsdk_apb_watchdog_update(s);
225 break;
226 case A_WDOGLOCK:
227 s->lock = (value != WDOG_UNLOCK_VALUE);
228 trace_cmsdk_apb_watchdog_lock(s->lock);
229 break;
230 case A_WDOGITCR:
231 if (s->is_luminary) {
232 goto bad_offset;
233 }
234 s->itcr = value & R_WDOGITCR_VALID_MASK;
235 cmsdk_apb_watchdog_update(s);
236 break;
237 case A_WDOGITOP:
238 if (s->is_luminary) {
239 goto bad_offset;
240 }
241 s->itop = value & R_WDOGITOP_VALID_MASK;
242 cmsdk_apb_watchdog_update(s);
243 break;
244 case A_WDOGVALUE:
245 case A_WDOGRIS:
246 case A_WDOGMIS:
247 case A_PID4 ... A_CID3:
248 qemu_log_mask(LOG_GUEST_ERROR,
249 "CMSDK APB watchdog write: write to RO offset 0x%x\n",
250 (int)offset);
251 break;
252 case A_WDOGTEST:
253 if (!s->is_luminary) {
254 goto bad_offset;
255 }
256 qemu_log_mask(LOG_UNIMP,
257 "Luminary watchdog write: stall not implemented\n");
258 break;
259 default:
260 bad_offset:
261 qemu_log_mask(LOG_GUEST_ERROR,
262 "CMSDK APB watchdog write: bad offset 0x%x\n",
263 (int)offset);
264 break;
265 }
266 }
267
268 static const MemoryRegionOps cmsdk_apb_watchdog_ops = {
269 .read = cmsdk_apb_watchdog_read,
270 .write = cmsdk_apb_watchdog_write,
271 .endianness = DEVICE_LITTLE_ENDIAN,
272 /* byte/halfword accesses are just zero-padded on reads and writes */
273 .impl.min_access_size = 4,
274 .impl.max_access_size = 4,
275 .valid.min_access_size = 1,
276 .valid.max_access_size = 4,
277 };
278
279 static void cmsdk_apb_watchdog_tick(void *opaque)
280 {
281 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
282
283 if (!s->intstatus) {
284 /* Count expired for the first time: raise interrupt */
285 s->intstatus = R_WDOGRIS_INT_MASK;
286 } else {
287 /* Count expired for the second time: raise reset and stop clock */
288 s->resetstatus = 1;
289 ptimer_stop(s->timer);
290 }
291 cmsdk_apb_watchdog_update(s);
292 }
293
294 static void cmsdk_apb_watchdog_reset(DeviceState *dev)
295 {
296 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
297
298 trace_cmsdk_apb_watchdog_reset();
299 s->control = 0;
300 s->intstatus = 0;
301 s->lock = 0;
302 s->itcr = 0;
303 s->itop = 0;
304 s->resetstatus = 0;
305 /* Set the limit and the count */
306 ptimer_transaction_begin(s->timer);
307 ptimer_set_limit(s->timer, 0xffffffff, 1);
308 ptimer_run(s->timer, 0);
309 ptimer_transaction_commit(s->timer);
310 }
311
312 static void cmsdk_apb_watchdog_init(Object *obj)
313 {
314 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
315 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
316
317 memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops,
318 s, "cmsdk-apb-watchdog", 0x1000);
319 sysbus_init_mmio(sbd, &s->iomem);
320 sysbus_init_irq(sbd, &s->wdogint);
321
322 s->is_luminary = false;
323 s->id = cmsdk_apb_watchdog_id;
324 }
325
326 static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
327 {
328 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
329
330 if (s->wdogclk_frq == 0) {
331 error_setg(errp,
332 "CMSDK APB watchdog: wdogclk-frq property must be set");
333 return;
334 }
335
336 s->timer = ptimer_init(cmsdk_apb_watchdog_tick, s,
337 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
338 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
339 PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
340 PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
341
342 ptimer_transaction_begin(s->timer);
343 ptimer_set_freq(s->timer, s->wdogclk_frq);
344 ptimer_transaction_commit(s->timer);
345 }
346
347 static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
348 .name = "cmsdk-apb-watchdog",
349 .version_id = 1,
350 .minimum_version_id = 1,
351 .fields = (VMStateField[]) {
352 VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
353 VMSTATE_UINT32(control, CMSDKAPBWatchdog),
354 VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
355 VMSTATE_UINT32(lock, CMSDKAPBWatchdog),
356 VMSTATE_UINT32(itcr, CMSDKAPBWatchdog),
357 VMSTATE_UINT32(itop, CMSDKAPBWatchdog),
358 VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog),
359 VMSTATE_END_OF_LIST()
360 }
361 };
362
363 static Property cmsdk_apb_watchdog_properties[] = {
364 DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
365 DEFINE_PROP_END_OF_LIST(),
366 };
367
368 static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
369 {
370 DeviceClass *dc = DEVICE_CLASS(klass);
371
372 dc->realize = cmsdk_apb_watchdog_realize;
373 dc->vmsd = &cmsdk_apb_watchdog_vmstate;
374 dc->reset = cmsdk_apb_watchdog_reset;
375 device_class_set_props(dc, cmsdk_apb_watchdog_properties);
376 }
377
378 static const TypeInfo cmsdk_apb_watchdog_info = {
379 .name = TYPE_CMSDK_APB_WATCHDOG,
380 .parent = TYPE_SYS_BUS_DEVICE,
381 .instance_size = sizeof(CMSDKAPBWatchdog),
382 .instance_init = cmsdk_apb_watchdog_init,
383 .class_init = cmsdk_apb_watchdog_class_init,
384 };
385
386 static void luminary_watchdog_init(Object *obj)
387 {
388 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
389
390 s->is_luminary = true;
391 s->id = luminary_watchdog_id;
392 }
393
394 static const TypeInfo luminary_watchdog_info = {
395 .name = TYPE_LUMINARY_WATCHDOG,
396 .parent = TYPE_CMSDK_APB_WATCHDOG,
397 .instance_init = luminary_watchdog_init
398 };
399
400 static void cmsdk_apb_watchdog_register_types(void)
401 {
402 type_register_static(&cmsdk_apb_watchdog_info);
403 type_register_static(&luminary_watchdog_info);
404 }
405
406 type_init(cmsdk_apb_watchdog_register_types);