PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / wdt_i6300esb.c
1 /*
2 * Virtual hardware watchdog.
3 *
4 * Copyright (C) 2009 Red Hat Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 * By Richard W.M. Jones (rjones@redhat.com).
20 */
21
22 #include <inttypes.h>
23
24 #include "qemu-common.h"
25 #include "qemu-timer.h"
26 #include "watchdog.h"
27 #include "hw.h"
28 #include "pci.h"
29
30 /*#define I6300ESB_DEBUG 1*/
31
32 #ifdef I6300ESB_DEBUG
33 #define i6300esb_debug(fs,...) \
34 fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
35 #else
36 #define i6300esb_debug(fs,...)
37 #endif
38
39 /* PCI configuration registers */
40 #define ESB_CONFIG_REG 0x60 /* Config register */
41 #define ESB_LOCK_REG 0x68 /* WDT lock register */
42
43 /* Memory mapped registers (offset from base address) */
44 #define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
45 #define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
46 #define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
47 #define ESB_RELOAD_REG 0x0c /* Reload register */
48
49 /* Lock register bits */
50 #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
51 #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
52 #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
53
54 /* Config register bits */
55 #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
56 #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
57 #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
58
59 /* Reload register bits */
60 #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
61
62 /* Magic constants */
63 #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
64 #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
65
66 /* Device state. */
67 struct I6300State {
68 PCIDevice dev;
69 MemoryRegion io_mem;
70
71 int reboot_enabled; /* "Reboot" on timer expiry. The real action
72 * performed depends on the -watchdog-action
73 * param passed on QEMU command line.
74 */
75 int clock_scale; /* Clock scale. */
76 #define CLOCK_SCALE_1KHZ 0
77 #define CLOCK_SCALE_1MHZ 1
78
79 int int_type; /* Interrupt type generated. */
80 #define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
81 #define INT_TYPE_SMI 2
82 #define INT_TYPE_DISABLED 3
83
84 int free_run; /* If true, reload timer on expiry. */
85 int locked; /* If true, enabled field cannot be changed. */
86 int enabled; /* If true, watchdog is enabled. */
87
88 QEMUTimer *timer; /* The actual watchdog timer. */
89
90 uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
91 uint32_t timer2_preload;
92 int stage; /* Stage (1 or 2). */
93
94 int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
95 * registers, and we transition through
96 * states 0 -> 1 -> 2 when this happens.
97 */
98
99 int previous_reboot_flag; /* If the watchdog caused the previous
100 * reboot, this flag will be set.
101 */
102 };
103
104 typedef struct I6300State I6300State;
105
106 /* This function is called when the watchdog has either been enabled
107 * (hence it starts counting down) or has been keep-alived.
108 */
109 static void i6300esb_restart_timer(I6300State *d, int stage)
110 {
111 int64_t timeout;
112
113 if (!d->enabled)
114 return;
115
116 d->stage = stage;
117
118 if (d->stage <= 1)
119 timeout = d->timer1_preload;
120 else
121 timeout = d->timer2_preload;
122
123 if (d->clock_scale == CLOCK_SCALE_1KHZ)
124 timeout <<= 15;
125 else
126 timeout <<= 5;
127
128 /* Get the timeout in units of ticks_per_sec. */
129 timeout = get_ticks_per_sec() * timeout / 33000000;
130
131 i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
132
133 qemu_mod_timer(d->timer, qemu_get_clock_ns(vm_clock) + timeout);
134 }
135
136 /* This is called when the guest disables the watchdog. */
137 static void i6300esb_disable_timer(I6300State *d)
138 {
139 i6300esb_debug("timer disabled\n");
140
141 qemu_del_timer(d->timer);
142 }
143
144 static void i6300esb_reset(DeviceState *dev)
145 {
146 PCIDevice *pdev = PCI_DEVICE(dev);
147 I6300State *d = DO_UPCAST(I6300State, dev, pdev);
148
149 i6300esb_debug("I6300State = %p\n", d);
150
151 i6300esb_disable_timer(d);
152
153 /* NB: Don't change d->previous_reboot_flag in this function. */
154
155 d->reboot_enabled = 1;
156 d->clock_scale = CLOCK_SCALE_1KHZ;
157 d->int_type = INT_TYPE_IRQ;
158 d->free_run = 0;
159 d->locked = 0;
160 d->enabled = 0;
161 d->timer1_preload = 0xfffff;
162 d->timer2_preload = 0xfffff;
163 d->stage = 1;
164 d->unlock_state = 0;
165 }
166
167 /* This function is called when the watchdog expires. Note that
168 * the hardware has two timers, and so expiry happens in two stages.
169 * If d->stage == 1 then we perform the first stage action (usually,
170 * sending an interrupt) and then restart the timer again for the
171 * second stage. If the second stage expires then the watchdog
172 * really has run out.
173 */
174 static void i6300esb_timer_expired(void *vp)
175 {
176 I6300State *d = vp;
177
178 i6300esb_debug("stage %d\n", d->stage);
179
180 if (d->stage == 1) {
181 /* What to do at the end of stage 1? */
182 switch (d->int_type) {
183 case INT_TYPE_IRQ:
184 fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
185 break;
186 case INT_TYPE_SMI:
187 fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
188 break;
189 }
190
191 /* Start the second stage. */
192 i6300esb_restart_timer(d, 2);
193 } else {
194 /* Second stage expired, reboot for real. */
195 if (d->reboot_enabled) {
196 d->previous_reboot_flag = 1;
197 watchdog_perform_action(); /* This reboots, exits, etc */
198 i6300esb_reset(&d->dev.qdev);
199 }
200
201 /* In "free running mode" we start stage 1 again. */
202 if (d->free_run)
203 i6300esb_restart_timer(d, 1);
204 }
205 }
206
207 static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
208 uint32_t data, int len)
209 {
210 I6300State *d = DO_UPCAST(I6300State, dev, dev);
211 int old;
212
213 i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
214
215 if (addr == ESB_CONFIG_REG && len == 2) {
216 d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
217 d->clock_scale =
218 (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
219 d->int_type = (data & ESB_WDT_INTTYPE);
220 } else if (addr == ESB_LOCK_REG && len == 1) {
221 if (!d->locked) {
222 d->locked = (data & ESB_WDT_LOCK) != 0;
223 d->free_run = (data & ESB_WDT_FUNC) != 0;
224 old = d->enabled;
225 d->enabled = (data & ESB_WDT_ENABLE) != 0;
226 if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
227 i6300esb_restart_timer(d, 1);
228 else if (!d->enabled)
229 i6300esb_disable_timer(d);
230 }
231 } else {
232 pci_default_write_config(dev, addr, data, len);
233 }
234 }
235
236 static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
237 {
238 I6300State *d = DO_UPCAST(I6300State, dev, dev);
239 uint32_t data;
240
241 i6300esb_debug ("addr = %x, len = %d\n", addr, len);
242
243 if (addr == ESB_CONFIG_REG && len == 2) {
244 data =
245 (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
246 (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
247 d->int_type;
248 return data;
249 } else if (addr == ESB_LOCK_REG && len == 1) {
250 data =
251 (d->free_run ? ESB_WDT_FUNC : 0) |
252 (d->locked ? ESB_WDT_LOCK : 0) |
253 (d->enabled ? ESB_WDT_ENABLE : 0);
254 return data;
255 } else {
256 return pci_default_read_config(dev, addr, len);
257 }
258 }
259
260 static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
261 {
262 i6300esb_debug ("addr = %x\n", (int) addr);
263
264 return 0;
265 }
266
267 static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
268 {
269 uint32_t data = 0;
270 I6300State *d = vp;
271
272 i6300esb_debug("addr = %x\n", (int) addr);
273
274 if (addr == 0xc) {
275 /* The previous reboot flag is really bit 9, but there is
276 * a bug in the Linux driver where it thinks it's bit 12.
277 * Set both.
278 */
279 data = d->previous_reboot_flag ? 0x1200 : 0;
280 }
281
282 return data;
283 }
284
285 static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
286 {
287 i6300esb_debug("addr = %x\n", (int) addr);
288
289 return 0;
290 }
291
292 static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
293 {
294 I6300State *d = vp;
295
296 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
297
298 if (addr == 0xc && val == 0x80)
299 d->unlock_state = 1;
300 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
301 d->unlock_state = 2;
302 }
303
304 static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
305 {
306 I6300State *d = vp;
307
308 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
309
310 if (addr == 0xc && val == 0x80)
311 d->unlock_state = 1;
312 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
313 d->unlock_state = 2;
314 else {
315 if (d->unlock_state == 2) {
316 if (addr == 0xc) {
317 if ((val & 0x100) != 0)
318 /* This is the "ping" from the userspace watchdog in
319 * the guest ...
320 */
321 i6300esb_restart_timer(d, 1);
322
323 /* Setting bit 9 resets the previous reboot flag.
324 * There's a bug in the Linux driver where it sets
325 * bit 12 instead.
326 */
327 if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
328 d->previous_reboot_flag = 0;
329 }
330 }
331
332 d->unlock_state = 0;
333 }
334 }
335 }
336
337 static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
338 {
339 I6300State *d = vp;
340
341 i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
342
343 if (addr == 0xc && val == 0x80)
344 d->unlock_state = 1;
345 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
346 d->unlock_state = 2;
347 else {
348 if (d->unlock_state == 2) {
349 if (addr == 0)
350 d->timer1_preload = val & 0xfffff;
351 else if (addr == 4)
352 d->timer2_preload = val & 0xfffff;
353
354 d->unlock_state = 0;
355 }
356 }
357 }
358
359 static const MemoryRegionOps i6300esb_ops = {
360 .old_mmio = {
361 .read = {
362 i6300esb_mem_readb,
363 i6300esb_mem_readw,
364 i6300esb_mem_readl,
365 },
366 .write = {
367 i6300esb_mem_writeb,
368 i6300esb_mem_writew,
369 i6300esb_mem_writel,
370 },
371 },
372 .endianness = DEVICE_NATIVE_ENDIAN,
373 };
374
375 static const VMStateDescription vmstate_i6300esb = {
376 .name = "i6300esb_wdt",
377 .version_id = sizeof(I6300State),
378 .minimum_version_id = sizeof(I6300State),
379 .minimum_version_id_old = sizeof(I6300State),
380 .fields = (VMStateField []) {
381 VMSTATE_PCI_DEVICE(dev, I6300State),
382 VMSTATE_INT32(reboot_enabled, I6300State),
383 VMSTATE_INT32(clock_scale, I6300State),
384 VMSTATE_INT32(int_type, I6300State),
385 VMSTATE_INT32(free_run, I6300State),
386 VMSTATE_INT32(locked, I6300State),
387 VMSTATE_INT32(enabled, I6300State),
388 VMSTATE_TIMER(timer, I6300State),
389 VMSTATE_UINT32(timer1_preload, I6300State),
390 VMSTATE_UINT32(timer2_preload, I6300State),
391 VMSTATE_INT32(stage, I6300State),
392 VMSTATE_INT32(unlock_state, I6300State),
393 VMSTATE_INT32(previous_reboot_flag, I6300State),
394 VMSTATE_END_OF_LIST()
395 }
396 };
397
398 static int i6300esb_init(PCIDevice *dev)
399 {
400 I6300State *d = DO_UPCAST(I6300State, dev, dev);
401
402 i6300esb_debug("I6300State = %p\n", d);
403
404 d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
405 d->previous_reboot_flag = 0;
406
407 memory_region_init_io(&d->io_mem, &i6300esb_ops, d, "i6300esb", 0x10);
408 pci_register_bar(&d->dev, 0, 0, &d->io_mem);
409 /* qemu_register_coalesced_mmio (addr, 0x10); ? */
410
411 return 0;
412 }
413
414 static int i6300esb_exit(PCIDevice *dev)
415 {
416 I6300State *d = DO_UPCAST(I6300State, dev, dev);
417
418 memory_region_destroy(&d->io_mem);
419
420 return 0;
421 }
422
423 static WatchdogTimerModel model = {
424 .wdt_name = "i6300esb",
425 .wdt_description = "Intel 6300ESB",
426 };
427
428 static void i6300esb_class_init(ObjectClass *klass, void *data)
429 {
430 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
431
432 k->config_read = i6300esb_config_read;
433 k->config_write = i6300esb_config_write;
434 k->init = i6300esb_init;
435 k->exit = i6300esb_exit;
436 k->vendor_id = PCI_VENDOR_ID_INTEL;
437 k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
438 k->class_id = PCI_CLASS_SYSTEM_OTHER;
439 }
440
441 static DeviceInfo i6300esb_info = {
442 .name = "i6300esb",
443 .size = sizeof(I6300State),
444 .vmsd = &vmstate_i6300esb,
445 .reset = i6300esb_reset,
446 .class_init = i6300esb_class_init,
447 };
448
449 static void i6300esb_register_devices(void)
450 {
451 watchdog_add_model(&model);
452 pci_qdev_register(&i6300esb_info);
453 }
454
455 device_init(i6300esb_register_devices);