xen: properly gate host writes of modified PCI CFG contents
[qemu.git] / hw / xen / xen_pt.c
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
15 /*
16 * Interrupt Disable policy:
17 *
18 * INTx interrupt:
19 * Initialize(register_real_device)
20 * Map INTx(xc_physdev_map_pirq):
21 * <fail>
22 * - Set real Interrupt Disable bit to '1'.
23 * - Set machine_irq and assigned_device->machine_irq to '0'.
24 * * Don't bind INTx.
25 *
26 * Bind INTx(xc_domain_bind_pt_pci_irq):
27 * <fail>
28 * - Set real Interrupt Disable bit to '1'.
29 * - Unmap INTx.
30 * - Decrement xen_pt_mapped_machine_irq[machine_irq]
31 * - Set assigned_device->machine_irq to '0'.
32 *
33 * Write to Interrupt Disable bit by guest software(xen_pt_cmd_reg_write)
34 * Write '0'
35 * - Set real bit to '0' if assigned_device->machine_irq isn't '0'.
36 *
37 * Write '1'
38 * - Set real bit to '1'.
39 *
40 * MSI interrupt:
41 * Initialize MSI register(xen_pt_msi_setup, xen_pt_msi_update)
42 * Bind MSI(xc_domain_update_msi_irq)
43 * <fail>
44 * - Unmap MSI.
45 * - Set dev->msi->pirq to '-1'.
46 *
47 * MSI-X interrupt:
48 * Initialize MSI-X register(xen_pt_msix_update_one)
49 * Bind MSI-X(xc_domain_update_msi_irq)
50 * <fail>
51 * - Unmap MSI-X.
52 * - Set entry->pirq to '-1'.
53 */
54
55 #include <sys/ioctl.h>
56
57 #include "hw/pci/pci.h"
58 #include "hw/xen/xen.h"
59 #include "hw/xen/xen_backend.h"
60 #include "xen_pt.h"
61 #include "qemu/range.h"
62 #include "exec/address-spaces.h"
63
64 #define XEN_PT_NR_IRQS (256)
65 static uint8_t xen_pt_mapped_machine_irq[XEN_PT_NR_IRQS] = {0};
66
67 void xen_pt_log(const PCIDevice *d, const char *f, ...)
68 {
69 va_list ap;
70
71 va_start(ap, f);
72 if (d) {
73 fprintf(stderr, "[%02x:%02x.%d] ", pci_bus_num(d->bus),
74 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
75 }
76 vfprintf(stderr, f, ap);
77 va_end(ap);
78 }
79
80 /* Config Space */
81
82 static int xen_pt_pci_config_access_check(PCIDevice *d, uint32_t addr, int len)
83 {
84 /* check offset range */
85 if (addr >= 0xFF) {
86 XEN_PT_ERR(d, "Failed to access register with offset exceeding 0xFF. "
87 "(addr: 0x%02x, len: %d)\n", addr, len);
88 return -1;
89 }
90
91 /* check read size */
92 if ((len != 1) && (len != 2) && (len != 4)) {
93 XEN_PT_ERR(d, "Failed to access register with invalid access length. "
94 "(addr: 0x%02x, len: %d)\n", addr, len);
95 return -1;
96 }
97
98 /* check offset alignment */
99 if (addr & (len - 1)) {
100 XEN_PT_ERR(d, "Failed to access register with invalid access size "
101 "alignment. (addr: 0x%02x, len: %d)\n", addr, len);
102 return -1;
103 }
104
105 return 0;
106 }
107
108 int xen_pt_bar_offset_to_index(uint32_t offset)
109 {
110 int index = 0;
111
112 /* check Exp ROM BAR */
113 if (offset == PCI_ROM_ADDRESS) {
114 return PCI_ROM_SLOT;
115 }
116
117 /* calculate BAR index */
118 index = (offset - PCI_BASE_ADDRESS_0) >> 2;
119 if (index >= PCI_NUM_REGIONS) {
120 return -1;
121 }
122
123 return index;
124 }
125
126 static uint32_t xen_pt_pci_read_config(PCIDevice *d, uint32_t addr, int len)
127 {
128 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d);
129 uint32_t val = 0;
130 XenPTRegGroup *reg_grp_entry = NULL;
131 XenPTReg *reg_entry = NULL;
132 int rc = 0;
133 int emul_len = 0;
134 uint32_t find_addr = addr;
135
136 if (xen_pt_pci_config_access_check(d, addr, len)) {
137 goto exit;
138 }
139
140 /* find register group entry */
141 reg_grp_entry = xen_pt_find_reg_grp(s, addr);
142 if (reg_grp_entry) {
143 /* check 0-Hardwired register group */
144 if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) {
145 /* no need to emulate, just return 0 */
146 val = 0;
147 goto exit;
148 }
149 }
150
151 /* read I/O device register value */
152 rc = xen_host_pci_get_block(&s->real_device, addr, (uint8_t *)&val, len);
153 if (rc < 0) {
154 XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc);
155 memset(&val, 0xff, len);
156 }
157
158 /* just return the I/O device register value for
159 * passthrough type register group */
160 if (reg_grp_entry == NULL) {
161 goto exit;
162 }
163
164 /* adjust the read value to appropriate CFC-CFF window */
165 val <<= (addr & 3) << 3;
166 emul_len = len;
167
168 /* loop around the guest requested size */
169 while (emul_len > 0) {
170 /* find register entry to be emulated */
171 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr);
172 if (reg_entry) {
173 XenPTRegInfo *reg = reg_entry->reg;
174 uint32_t real_offset = reg_grp_entry->base_offset + reg->offset;
175 uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3);
176 uint8_t *ptr_val = NULL;
177
178 valid_mask <<= (find_addr - real_offset) << 3;
179 ptr_val = (uint8_t *)&val + (real_offset & 3);
180
181 /* do emulation based on register size */
182 switch (reg->size) {
183 case 1:
184 if (reg->u.b.read) {
185 rc = reg->u.b.read(s, reg_entry, ptr_val, valid_mask);
186 }
187 break;
188 case 2:
189 if (reg->u.w.read) {
190 rc = reg->u.w.read(s, reg_entry,
191 (uint16_t *)ptr_val, valid_mask);
192 }
193 break;
194 case 4:
195 if (reg->u.dw.read) {
196 rc = reg->u.dw.read(s, reg_entry,
197 (uint32_t *)ptr_val, valid_mask);
198 }
199 break;
200 }
201
202 if (rc < 0) {
203 xen_shutdown_fatal_error("Internal error: Invalid read "
204 "emulation. (%s, rc: %d)\n",
205 __func__, rc);
206 return 0;
207 }
208
209 /* calculate next address to find */
210 emul_len -= reg->size;
211 if (emul_len > 0) {
212 find_addr = real_offset + reg->size;
213 }
214 } else {
215 /* nothing to do with passthrough type register,
216 * continue to find next byte */
217 emul_len--;
218 find_addr++;
219 }
220 }
221
222 /* need to shift back before returning them to pci bus emulator */
223 val >>= ((addr & 3) << 3);
224
225 exit:
226 XEN_PT_LOG_CONFIG(d, addr, val, len);
227 return val;
228 }
229
230 static void xen_pt_pci_write_config(PCIDevice *d, uint32_t addr,
231 uint32_t val, int len)
232 {
233 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d);
234 int index = 0;
235 XenPTRegGroup *reg_grp_entry = NULL;
236 int rc = 0;
237 uint32_t read_val = 0, wb_mask;
238 int emul_len = 0;
239 XenPTReg *reg_entry = NULL;
240 uint32_t find_addr = addr;
241 XenPTRegInfo *reg = NULL;
242
243 if (xen_pt_pci_config_access_check(d, addr, len)) {
244 return;
245 }
246
247 XEN_PT_LOG_CONFIG(d, addr, val, len);
248
249 /* check unused BAR register */
250 index = xen_pt_bar_offset_to_index(addr);
251 if ((index >= 0) && (val > 0 && val < XEN_PT_BAR_ALLF) &&
252 (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED)) {
253 XEN_PT_WARN(d, "Guest attempt to set address to unused Base Address "
254 "Register. (addr: 0x%02x, len: %d)\n", addr, len);
255 }
256
257 /* find register group entry */
258 reg_grp_entry = xen_pt_find_reg_grp(s, addr);
259 if (reg_grp_entry) {
260 /* check 0-Hardwired register group */
261 if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) {
262 /* ignore silently */
263 XEN_PT_WARN(d, "Access to 0-Hardwired register. "
264 "(addr: 0x%02x, len: %d)\n", addr, len);
265 return;
266 }
267 }
268
269 rc = xen_host_pci_get_block(&s->real_device, addr,
270 (uint8_t *)&read_val, len);
271 if (rc < 0) {
272 XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc);
273 memset(&read_val, 0xff, len);
274 wb_mask = 0;
275 } else {
276 wb_mask = 0xFFFFFFFF >> ((4 - len) << 3);
277 }
278
279 /* pass directly to the real device for passthrough type register group */
280 if (reg_grp_entry == NULL) {
281 goto out;
282 }
283
284 memory_region_transaction_begin();
285 pci_default_write_config(d, addr, val, len);
286
287 /* adjust the read and write value to appropriate CFC-CFF window */
288 read_val <<= (addr & 3) << 3;
289 val <<= (addr & 3) << 3;
290 emul_len = len;
291
292 /* loop around the guest requested size */
293 while (emul_len > 0) {
294 /* find register entry to be emulated */
295 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr);
296 if (reg_entry) {
297 reg = reg_entry->reg;
298 uint32_t real_offset = reg_grp_entry->base_offset + reg->offset;
299 uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3);
300 uint8_t *ptr_val = NULL;
301
302 valid_mask <<= (find_addr - real_offset) << 3;
303 ptr_val = (uint8_t *)&val + (real_offset & 3);
304 if (reg->emu_mask == (0xFFFFFFFF >> ((4 - reg->size) << 3))) {
305 wb_mask &= ~((reg->emu_mask
306 >> ((find_addr - real_offset) << 3))
307 << ((len - emul_len) << 3));
308 }
309
310 /* do emulation based on register size */
311 switch (reg->size) {
312 case 1:
313 if (reg->u.b.write) {
314 rc = reg->u.b.write(s, reg_entry, ptr_val,
315 read_val >> ((real_offset & 3) << 3),
316 valid_mask);
317 }
318 break;
319 case 2:
320 if (reg->u.w.write) {
321 rc = reg->u.w.write(s, reg_entry, (uint16_t *)ptr_val,
322 (read_val >> ((real_offset & 3) << 3)),
323 valid_mask);
324 }
325 break;
326 case 4:
327 if (reg->u.dw.write) {
328 rc = reg->u.dw.write(s, reg_entry, (uint32_t *)ptr_val,
329 (read_val >> ((real_offset & 3) << 3)),
330 valid_mask);
331 }
332 break;
333 }
334
335 if (rc < 0) {
336 xen_shutdown_fatal_error("Internal error: Invalid write"
337 " emulation. (%s, rc: %d)\n",
338 __func__, rc);
339 return;
340 }
341
342 /* calculate next address to find */
343 emul_len -= reg->size;
344 if (emul_len > 0) {
345 find_addr = real_offset + reg->size;
346 }
347 } else {
348 /* nothing to do with passthrough type register,
349 * continue to find next byte */
350 emul_len--;
351 find_addr++;
352 }
353 }
354
355 /* need to shift back before passing them to xen_host_pci_device */
356 val >>= (addr & 3) << 3;
357
358 memory_region_transaction_commit();
359
360 out:
361 for (index = 0; wb_mask; index += len) {
362 /* unknown regs are passed through */
363 while (!(wb_mask & 0xff)) {
364 index++;
365 wb_mask >>= 8;
366 }
367 len = 0;
368 do {
369 len++;
370 wb_mask >>= 8;
371 } while (wb_mask & 0xff);
372 rc = xen_host_pci_set_block(&s->real_device, addr + index,
373 (uint8_t *)&val + index, len);
374
375 if (rc < 0) {
376 XEN_PT_ERR(d, "pci_write_block failed. return value: %d.\n", rc);
377 }
378 }
379 }
380
381 /* register regions */
382
383 static uint64_t xen_pt_bar_read(void *o, hwaddr addr,
384 unsigned size)
385 {
386 PCIDevice *d = o;
387 /* if this function is called, that probably means that there is a
388 * misconfiguration of the IOMMU. */
389 XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n",
390 addr);
391 return 0;
392 }
393 static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val,
394 unsigned size)
395 {
396 PCIDevice *d = o;
397 /* Same comment as xen_pt_bar_read function */
398 XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n",
399 addr);
400 }
401
402 static const MemoryRegionOps ops = {
403 .endianness = DEVICE_NATIVE_ENDIAN,
404 .read = xen_pt_bar_read,
405 .write = xen_pt_bar_write,
406 };
407
408 static int xen_pt_register_regions(XenPCIPassthroughState *s, uint16_t *cmd)
409 {
410 int i = 0;
411 XenHostPCIDevice *d = &s->real_device;
412
413 /* Register PIO/MMIO BARs */
414 for (i = 0; i < PCI_ROM_SLOT; i++) {
415 XenHostPCIIORegion *r = &d->io_regions[i];
416 uint8_t type;
417
418 if (r->base_addr == 0 || r->size == 0) {
419 continue;
420 }
421
422 s->bases[i].access.u = r->base_addr;
423
424 if (r->type & XEN_HOST_PCI_REGION_TYPE_IO) {
425 type = PCI_BASE_ADDRESS_SPACE_IO;
426 *cmd |= PCI_COMMAND_IO;
427 } else {
428 type = PCI_BASE_ADDRESS_SPACE_MEMORY;
429 if (r->type & XEN_HOST_PCI_REGION_TYPE_PREFETCH) {
430 type |= PCI_BASE_ADDRESS_MEM_PREFETCH;
431 }
432 if (r->type & XEN_HOST_PCI_REGION_TYPE_MEM_64) {
433 type |= PCI_BASE_ADDRESS_MEM_TYPE_64;
434 }
435 *cmd |= PCI_COMMAND_MEMORY;
436 }
437
438 memory_region_init_io(&s->bar[i], OBJECT(s), &ops, &s->dev,
439 "xen-pci-pt-bar", r->size);
440 pci_register_bar(&s->dev, i, type, &s->bar[i]);
441
442 XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%08"PRIx64
443 " base_addr=0x%08"PRIx64" type: %#x)\n",
444 i, r->size, r->base_addr, type);
445 }
446
447 /* Register expansion ROM address */
448 if (d->rom.base_addr && d->rom.size) {
449 uint32_t bar_data = 0;
450
451 /* Re-set BAR reported by OS, otherwise ROM can't be read. */
452 if (xen_host_pci_get_long(d, PCI_ROM_ADDRESS, &bar_data)) {
453 return 0;
454 }
455 if ((bar_data & PCI_ROM_ADDRESS_MASK) == 0) {
456 bar_data |= d->rom.base_addr & PCI_ROM_ADDRESS_MASK;
457 xen_host_pci_set_long(d, PCI_ROM_ADDRESS, bar_data);
458 }
459
460 s->bases[PCI_ROM_SLOT].access.maddr = d->rom.base_addr;
461
462 memory_region_init_io(&s->rom, OBJECT(s), &ops, &s->dev,
463 "xen-pci-pt-rom", d->rom.size);
464 pci_register_bar(&s->dev, PCI_ROM_SLOT, PCI_BASE_ADDRESS_MEM_PREFETCH,
465 &s->rom);
466
467 XEN_PT_LOG(&s->dev, "Expansion ROM registered (size=0x%08"PRIx64
468 " base_addr=0x%08"PRIx64")\n",
469 d->rom.size, d->rom.base_addr);
470 }
471
472 return 0;
473 }
474
475 /* region mapping */
476
477 static int xen_pt_bar_from_region(XenPCIPassthroughState *s, MemoryRegion *mr)
478 {
479 int i = 0;
480
481 for (i = 0; i < PCI_NUM_REGIONS - 1; i++) {
482 if (mr == &s->bar[i]) {
483 return i;
484 }
485 }
486 if (mr == &s->rom) {
487 return PCI_ROM_SLOT;
488 }
489 return -1;
490 }
491
492 /*
493 * This function checks if an io_region overlaps an io_region from another
494 * device. The io_region to check is provided with (addr, size and type)
495 * A callback can be provided and will be called for every region that is
496 * overlapped.
497 * The return value indicates if the region is overlappsed */
498 struct CheckBarArgs {
499 XenPCIPassthroughState *s;
500 pcibus_t addr;
501 pcibus_t size;
502 uint8_t type;
503 bool rc;
504 };
505 static void xen_pt_check_bar_overlap(PCIBus *bus, PCIDevice *d, void *opaque)
506 {
507 struct CheckBarArgs *arg = opaque;
508 XenPCIPassthroughState *s = arg->s;
509 uint8_t type = arg->type;
510 int i;
511
512 if (d->devfn == s->dev.devfn) {
513 return;
514 }
515
516 /* xxx: This ignores bridges. */
517 for (i = 0; i < PCI_NUM_REGIONS; i++) {
518 const PCIIORegion *r = &d->io_regions[i];
519
520 if (!r->size) {
521 continue;
522 }
523 if ((type & PCI_BASE_ADDRESS_SPACE_IO)
524 != (r->type & PCI_BASE_ADDRESS_SPACE_IO)) {
525 continue;
526 }
527
528 if (ranges_overlap(arg->addr, arg->size, r->addr, r->size)) {
529 XEN_PT_WARN(&s->dev,
530 "Overlapped to device [%02x:%02x.%d] Region: %i"
531 " (addr: %#"FMT_PCIBUS", len: %#"FMT_PCIBUS")\n",
532 pci_bus_num(bus), PCI_SLOT(d->devfn),
533 PCI_FUNC(d->devfn), i, r->addr, r->size);
534 arg->rc = true;
535 }
536 }
537 }
538
539 static void xen_pt_region_update(XenPCIPassthroughState *s,
540 MemoryRegionSection *sec, bool adding)
541 {
542 PCIDevice *d = &s->dev;
543 MemoryRegion *mr = sec->mr;
544 int bar = -1;
545 int rc;
546 int op = adding ? DPCI_ADD_MAPPING : DPCI_REMOVE_MAPPING;
547 struct CheckBarArgs args = {
548 .s = s,
549 .addr = sec->offset_within_address_space,
550 .size = int128_get64(sec->size),
551 .rc = false,
552 };
553
554 bar = xen_pt_bar_from_region(s, mr);
555 if (bar == -1 && (!s->msix || &s->msix->mmio != mr)) {
556 return;
557 }
558
559 if (s->msix && &s->msix->mmio == mr) {
560 if (adding) {
561 s->msix->mmio_base_addr = sec->offset_within_address_space;
562 rc = xen_pt_msix_update_remap(s, s->msix->bar_index);
563 }
564 return;
565 }
566
567 args.type = d->io_regions[bar].type;
568 pci_for_each_device(d->bus, pci_bus_num(d->bus),
569 xen_pt_check_bar_overlap, &args);
570 if (args.rc) {
571 XEN_PT_WARN(d, "Region: %d (addr: %#"FMT_PCIBUS
572 ", len: %#"FMT_PCIBUS") is overlapped.\n",
573 bar, sec->offset_within_address_space,
574 int128_get64(sec->size));
575 }
576
577 if (d->io_regions[bar].type & PCI_BASE_ADDRESS_SPACE_IO) {
578 uint32_t guest_port = sec->offset_within_address_space;
579 uint32_t machine_port = s->bases[bar].access.pio_base;
580 uint32_t size = int128_get64(sec->size);
581 rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
582 guest_port, machine_port, size,
583 op);
584 if (rc) {
585 XEN_PT_ERR(d, "%s ioport mapping failed! (rc: %i)\n",
586 adding ? "create new" : "remove old", rc);
587 }
588 } else {
589 pcibus_t guest_addr = sec->offset_within_address_space;
590 pcibus_t machine_addr = s->bases[bar].access.maddr
591 + sec->offset_within_region;
592 pcibus_t size = int128_get64(sec->size);
593 rc = xc_domain_memory_mapping(xen_xc, xen_domid,
594 XEN_PFN(guest_addr + XC_PAGE_SIZE - 1),
595 XEN_PFN(machine_addr + XC_PAGE_SIZE - 1),
596 XEN_PFN(size + XC_PAGE_SIZE - 1),
597 op);
598 if (rc) {
599 XEN_PT_ERR(d, "%s mem mapping failed! (rc: %i)\n",
600 adding ? "create new" : "remove old", rc);
601 }
602 }
603 }
604
605 static void xen_pt_region_add(MemoryListener *l, MemoryRegionSection *sec)
606 {
607 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
608 memory_listener);
609
610 memory_region_ref(sec->mr);
611 xen_pt_region_update(s, sec, true);
612 }
613
614 static void xen_pt_region_del(MemoryListener *l, MemoryRegionSection *sec)
615 {
616 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
617 memory_listener);
618
619 xen_pt_region_update(s, sec, false);
620 memory_region_unref(sec->mr);
621 }
622
623 static void xen_pt_io_region_add(MemoryListener *l, MemoryRegionSection *sec)
624 {
625 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
626 io_listener);
627
628 memory_region_ref(sec->mr);
629 xen_pt_region_update(s, sec, true);
630 }
631
632 static void xen_pt_io_region_del(MemoryListener *l, MemoryRegionSection *sec)
633 {
634 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
635 io_listener);
636
637 xen_pt_region_update(s, sec, false);
638 memory_region_unref(sec->mr);
639 }
640
641 static const MemoryListener xen_pt_memory_listener = {
642 .region_add = xen_pt_region_add,
643 .region_del = xen_pt_region_del,
644 .priority = 10,
645 };
646
647 static const MemoryListener xen_pt_io_listener = {
648 .region_add = xen_pt_io_region_add,
649 .region_del = xen_pt_io_region_del,
650 .priority = 10,
651 };
652
653 /* init */
654
655 static int xen_pt_initfn(PCIDevice *d)
656 {
657 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d);
658 int rc = 0;
659 uint8_t machine_irq = 0;
660 uint16_t cmd = 0;
661 int pirq = XEN_PT_UNASSIGNED_PIRQ;
662
663 /* register real device */
664 XEN_PT_LOG(d, "Assigning real physical device %02x:%02x.%d"
665 " to devfn %#x\n",
666 s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function,
667 s->dev.devfn);
668
669 rc = xen_host_pci_device_get(&s->real_device,
670 s->hostaddr.domain, s->hostaddr.bus,
671 s->hostaddr.slot, s->hostaddr.function);
672 if (rc) {
673 XEN_PT_ERR(d, "Failed to \"open\" the real pci device. rc: %i\n", rc);
674 return -1;
675 }
676
677 s->is_virtfn = s->real_device.is_virtfn;
678 if (s->is_virtfn) {
679 XEN_PT_LOG(d, "%04x:%02x:%02x.%d is a SR-IOV Virtual Function\n",
680 s->real_device.domain, s->real_device.bus,
681 s->real_device.dev, s->real_device.func);
682 }
683
684 /* Initialize virtualized PCI configuration (Extended 256 Bytes) */
685 if (xen_host_pci_get_block(&s->real_device, 0, d->config,
686 PCI_CONFIG_SPACE_SIZE) == -1) {
687 xen_host_pci_device_put(&s->real_device);
688 return -1;
689 }
690
691 s->memory_listener = xen_pt_memory_listener;
692 s->io_listener = xen_pt_io_listener;
693
694 /* Handle real device's MMIO/PIO BARs */
695 xen_pt_register_regions(s, &cmd);
696
697 /* reinitialize each config register to be emulated */
698 if (xen_pt_config_init(s)) {
699 XEN_PT_ERR(d, "PCI Config space initialisation failed.\n");
700 xen_host_pci_device_put(&s->real_device);
701 return -1;
702 }
703
704 /* Bind interrupt */
705 if (!s->dev.config[PCI_INTERRUPT_PIN]) {
706 XEN_PT_LOG(d, "no pin interrupt\n");
707 goto out;
708 }
709
710 machine_irq = s->real_device.irq;
711 rc = xc_physdev_map_pirq(xen_xc, xen_domid, machine_irq, &pirq);
712
713 if (rc < 0) {
714 XEN_PT_ERR(d, "Mapping machine irq %u to pirq %i failed, (rc: %d)\n",
715 machine_irq, pirq, rc);
716
717 /* Disable PCI intx assertion (turn on bit10 of devctl) */
718 xen_host_pci_set_word(&s->real_device,
719 PCI_COMMAND,
720 pci_get_word(s->dev.config + PCI_COMMAND)
721 | PCI_COMMAND_INTX_DISABLE);
722 machine_irq = 0;
723 s->machine_irq = 0;
724 } else {
725 machine_irq = pirq;
726 s->machine_irq = pirq;
727 xen_pt_mapped_machine_irq[machine_irq]++;
728 }
729
730 /* bind machine_irq to device */
731 if (machine_irq != 0) {
732 uint8_t e_intx = xen_pt_pci_intx(s);
733
734 rc = xc_domain_bind_pt_pci_irq(xen_xc, xen_domid, machine_irq,
735 pci_bus_num(d->bus),
736 PCI_SLOT(d->devfn),
737 e_intx);
738 if (rc < 0) {
739 XEN_PT_ERR(d, "Binding of interrupt %i failed! (rc: %d)\n",
740 e_intx, rc);
741
742 /* Disable PCI intx assertion (turn on bit10 of devctl) */
743 xen_host_pci_set_word(&s->real_device, PCI_COMMAND,
744 *(uint16_t *)(&s->dev.config[PCI_COMMAND])
745 | PCI_COMMAND_INTX_DISABLE);
746 xen_pt_mapped_machine_irq[machine_irq]--;
747
748 if (xen_pt_mapped_machine_irq[machine_irq] == 0) {
749 if (xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq)) {
750 XEN_PT_ERR(d, "Unmapping of machine interrupt %i failed!"
751 " (rc: %d)\n", machine_irq, rc);
752 }
753 }
754 s->machine_irq = 0;
755 }
756 }
757
758 out:
759 if (cmd) {
760 xen_host_pci_set_word(&s->real_device, PCI_COMMAND,
761 pci_get_word(d->config + PCI_COMMAND) | cmd);
762 }
763
764 memory_listener_register(&s->memory_listener, &s->dev.bus_master_as);
765 memory_listener_register(&s->io_listener, &address_space_io);
766 XEN_PT_LOG(d,
767 "Real physical device %02x:%02x.%d registered successfully!\n",
768 s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function);
769
770 return 0;
771 }
772
773 static void xen_pt_unregister_device(PCIDevice *d)
774 {
775 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d);
776 uint8_t machine_irq = s->machine_irq;
777 uint8_t intx = xen_pt_pci_intx(s);
778 int rc;
779
780 if (machine_irq) {
781 rc = xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq,
782 PT_IRQ_TYPE_PCI,
783 pci_bus_num(d->bus),
784 PCI_SLOT(s->dev.devfn),
785 intx,
786 0 /* isa_irq */);
787 if (rc < 0) {
788 XEN_PT_ERR(d, "unbinding of interrupt INT%c failed."
789 " (machine irq: %i, rc: %d)"
790 " But bravely continuing on..\n",
791 'a' + intx, machine_irq, rc);
792 }
793 }
794
795 if (s->msi) {
796 xen_pt_msi_disable(s);
797 }
798 if (s->msix) {
799 xen_pt_msix_disable(s);
800 }
801
802 if (machine_irq) {
803 xen_pt_mapped_machine_irq[machine_irq]--;
804
805 if (xen_pt_mapped_machine_irq[machine_irq] == 0) {
806 rc = xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq);
807
808 if (rc < 0) {
809 XEN_PT_ERR(d, "unmapping of interrupt %i failed. (rc: %d)"
810 " But bravely continuing on..\n",
811 machine_irq, rc);
812 }
813 }
814 }
815
816 /* delete all emulated config registers */
817 xen_pt_config_delete(s);
818
819 memory_listener_unregister(&s->memory_listener);
820 memory_listener_unregister(&s->io_listener);
821
822 xen_host_pci_device_put(&s->real_device);
823 }
824
825 static Property xen_pci_passthrough_properties[] = {
826 DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr),
827 DEFINE_PROP_END_OF_LIST(),
828 };
829
830 static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data)
831 {
832 DeviceClass *dc = DEVICE_CLASS(klass);
833 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
834
835 k->init = xen_pt_initfn;
836 k->exit = xen_pt_unregister_device;
837 k->config_read = xen_pt_pci_read_config;
838 k->config_write = xen_pt_pci_write_config;
839 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
840 dc->desc = "Assign an host PCI device with Xen";
841 dc->props = xen_pci_passthrough_properties;
842 };
843
844 static const TypeInfo xen_pci_passthrough_info = {
845 .name = "xen-pci-passthrough",
846 .parent = TYPE_PCI_DEVICE,
847 .instance_size = sizeof(XenPCIPassthroughState),
848 .class_init = xen_pci_passthrough_class_init,
849 };
850
851 static void xen_pci_passthrough_register_types(void)
852 {
853 type_register_static(&xen_pci_passthrough_info);
854 }
855
856 type_init(xen_pci_passthrough_register_types)