xen: properly gate host writes of modified PCI CFG contents
[qemu.git] / hw / xen / xen_pt.h
1 #ifndef XEN_PT_H
2 #define XEN_PT_H
3
4 #include "qemu-common.h"
5 #include "hw/xen/xen_common.h"
6 #include "hw/pci/pci.h"
7 #include "xen-host-pci-device.h"
8
9 void xen_pt_log(const PCIDevice *d, const char *f, ...) GCC_FMT_ATTR(2, 3);
10
11 #define XEN_PT_ERR(d, _f, _a...) xen_pt_log(d, "%s: Error: "_f, __func__, ##_a)
12
13 #ifdef XEN_PT_LOGGING_ENABLED
14 # define XEN_PT_LOG(d, _f, _a...) xen_pt_log(d, "%s: " _f, __func__, ##_a)
15 # define XEN_PT_WARN(d, _f, _a...) \
16 xen_pt_log(d, "%s: Warning: "_f, __func__, ##_a)
17 #else
18 # define XEN_PT_LOG(d, _f, _a...)
19 # define XEN_PT_WARN(d, _f, _a...)
20 #endif
21
22 #ifdef XEN_PT_DEBUG_PCI_CONFIG_ACCESS
23 # define XEN_PT_LOG_CONFIG(d, addr, val, len) \
24 xen_pt_log(d, "%s: address=0x%04x val=0x%08x len=%d\n", \
25 __func__, addr, val, len)
26 #else
27 # define XEN_PT_LOG_CONFIG(d, addr, val, len)
28 #endif
29
30
31 /* Helper */
32 #define XEN_PFN(x) ((x) >> XC_PAGE_SHIFT)
33
34 typedef struct XenPTRegInfo XenPTRegInfo;
35 typedef struct XenPTReg XenPTReg;
36
37 typedef struct XenPCIPassthroughState XenPCIPassthroughState;
38
39 /* function type for config reg */
40 typedef int (*xen_pt_conf_reg_init)
41 (XenPCIPassthroughState *, XenPTRegInfo *, uint32_t real_offset,
42 uint32_t *data);
43 typedef int (*xen_pt_conf_dword_write)
44 (XenPCIPassthroughState *, XenPTReg *cfg_entry,
45 uint32_t *val, uint32_t dev_value, uint32_t valid_mask);
46 typedef int (*xen_pt_conf_word_write)
47 (XenPCIPassthroughState *, XenPTReg *cfg_entry,
48 uint16_t *val, uint16_t dev_value, uint16_t valid_mask);
49 typedef int (*xen_pt_conf_byte_write)
50 (XenPCIPassthroughState *, XenPTReg *cfg_entry,
51 uint8_t *val, uint8_t dev_value, uint8_t valid_mask);
52 typedef int (*xen_pt_conf_dword_read)
53 (XenPCIPassthroughState *, XenPTReg *cfg_entry,
54 uint32_t *val, uint32_t valid_mask);
55 typedef int (*xen_pt_conf_word_read)
56 (XenPCIPassthroughState *, XenPTReg *cfg_entry,
57 uint16_t *val, uint16_t valid_mask);
58 typedef int (*xen_pt_conf_byte_read)
59 (XenPCIPassthroughState *, XenPTReg *cfg_entry,
60 uint8_t *val, uint8_t valid_mask);
61
62 #define XEN_PT_BAR_ALLF 0xFFFFFFFF
63 #define XEN_PT_BAR_UNMAPPED (-1)
64
65 #define PCI_CAP_MAX 48
66
67
68 typedef enum {
69 XEN_PT_GRP_TYPE_HARDWIRED = 0, /* 0 Hardwired reg group */
70 XEN_PT_GRP_TYPE_EMU, /* emul reg group */
71 } XenPTRegisterGroupType;
72
73 typedef enum {
74 XEN_PT_BAR_FLAG_MEM = 0, /* Memory type BAR */
75 XEN_PT_BAR_FLAG_IO, /* I/O type BAR */
76 XEN_PT_BAR_FLAG_UPPER, /* upper 64bit BAR */
77 XEN_PT_BAR_FLAG_UNUSED, /* unused BAR */
78 } XenPTBarFlag;
79
80
81 typedef struct XenPTRegion {
82 /* BAR flag */
83 XenPTBarFlag bar_flag;
84 /* Translation of the emulated address */
85 union {
86 uint64_t maddr;
87 uint64_t pio_base;
88 uint64_t u;
89 } access;
90 } XenPTRegion;
91
92 /* XenPTRegInfo declaration
93 * - only for emulated register (either a part or whole bit).
94 * - for passthrough register that need special behavior (like interacting with
95 * other component), set emu_mask to all 0 and specify r/w func properly.
96 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
97 */
98
99 /* emulated register information */
100 struct XenPTRegInfo {
101 uint32_t offset;
102 uint32_t size;
103 uint32_t init_val;
104 /* reg read only field mask (ON:RO/ROS, OFF:other) */
105 uint32_t ro_mask;
106 /* reg emulate field mask (ON:emu, OFF:passthrough) */
107 uint32_t emu_mask;
108 xen_pt_conf_reg_init init;
109 /* read/write function pointer
110 * for double_word/word/byte size */
111 union {
112 struct {
113 xen_pt_conf_dword_write write;
114 xen_pt_conf_dword_read read;
115 } dw;
116 struct {
117 xen_pt_conf_word_write write;
118 xen_pt_conf_word_read read;
119 } w;
120 struct {
121 xen_pt_conf_byte_write write;
122 xen_pt_conf_byte_read read;
123 } b;
124 } u;
125 };
126
127 /* emulated register management */
128 struct XenPTReg {
129 QLIST_ENTRY(XenPTReg) entries;
130 XenPTRegInfo *reg;
131 uint32_t data; /* emulated value */
132 };
133
134 typedef struct XenPTRegGroupInfo XenPTRegGroupInfo;
135
136 /* emul reg group size initialize method */
137 typedef int (*xen_pt_reg_size_init_fn)
138 (XenPCIPassthroughState *, const XenPTRegGroupInfo *,
139 uint32_t base_offset, uint8_t *size);
140
141 /* emulated register group information */
142 struct XenPTRegGroupInfo {
143 uint8_t grp_id;
144 XenPTRegisterGroupType grp_type;
145 uint8_t grp_size;
146 xen_pt_reg_size_init_fn size_init;
147 XenPTRegInfo *emu_regs;
148 };
149
150 /* emul register group management table */
151 typedef struct XenPTRegGroup {
152 QLIST_ENTRY(XenPTRegGroup) entries;
153 const XenPTRegGroupInfo *reg_grp;
154 uint32_t base_offset;
155 uint8_t size;
156 QLIST_HEAD(, XenPTReg) reg_tbl_list;
157 } XenPTRegGroup;
158
159
160 #define XEN_PT_UNASSIGNED_PIRQ (-1)
161 typedef struct XenPTMSI {
162 uint16_t flags;
163 uint32_t addr_lo; /* guest message address */
164 uint32_t addr_hi; /* guest message upper address */
165 uint16_t data; /* guest message data */
166 uint32_t ctrl_offset; /* saved control offset */
167 int pirq; /* guest pirq corresponding */
168 bool initialized; /* when guest MSI is initialized */
169 bool mapped; /* when pirq is mapped */
170 } XenPTMSI;
171
172 typedef struct XenPTMSIXEntry {
173 int pirq;
174 uint64_t addr;
175 uint32_t data;
176 uint32_t vector_ctrl;
177 bool updated; /* indicate whether MSI ADDR or DATA is updated */
178 } XenPTMSIXEntry;
179 typedef struct XenPTMSIX {
180 uint32_t ctrl_offset;
181 bool enabled;
182 int total_entries;
183 int bar_index;
184 uint64_t table_base;
185 uint32_t table_offset_adjust; /* page align mmap */
186 uint64_t mmio_base_addr;
187 MemoryRegion mmio;
188 void *phys_iomem_base;
189 XenPTMSIXEntry msix_entry[0];
190 } XenPTMSIX;
191
192 struct XenPCIPassthroughState {
193 PCIDevice dev;
194
195 PCIHostDeviceAddress hostaddr;
196 bool is_virtfn;
197 XenHostPCIDevice real_device;
198 XenPTRegion bases[PCI_NUM_REGIONS]; /* Access regions */
199 QLIST_HEAD(, XenPTRegGroup) reg_grps;
200
201 uint32_t machine_irq;
202
203 XenPTMSI *msi;
204 XenPTMSIX *msix;
205
206 MemoryRegion bar[PCI_NUM_REGIONS - 1];
207 MemoryRegion rom;
208
209 MemoryListener memory_listener;
210 MemoryListener io_listener;
211 };
212
213 int xen_pt_config_init(XenPCIPassthroughState *s);
214 void xen_pt_config_delete(XenPCIPassthroughState *s);
215 XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address);
216 XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address);
217 int xen_pt_bar_offset_to_index(uint32_t offset);
218
219 static inline pcibus_t xen_pt_get_emul_size(XenPTBarFlag flag, pcibus_t r_size)
220 {
221 /* align resource size (memory type only) */
222 if (flag == XEN_PT_BAR_FLAG_MEM) {
223 return (r_size + XC_PAGE_SIZE - 1) & XC_PAGE_MASK;
224 } else {
225 return r_size;
226 }
227 }
228
229 /* INTx */
230 /* The PCI Local Bus Specification, Rev. 3.0,
231 * Section 6.2.4 Miscellaneous Registers, pp 223
232 * outlines 5 valid values for the interrupt pin (intx).
233 * 0: For devices (or device functions) that don't use an interrupt in
234 * 1: INTA#
235 * 2: INTB#
236 * 3: INTC#
237 * 4: INTD#
238 *
239 * Xen uses the following 4 values for intx
240 * 0: INTA#
241 * 1: INTB#
242 * 2: INTC#
243 * 3: INTD#
244 *
245 * Observing that these list of values are not the same, xen_pt_pci_read_intx()
246 * uses the following mapping from hw to xen values.
247 * This seems to reflect the current usage within Xen.
248 *
249 * PCI hardware | Xen | Notes
250 * ----------------+-----+----------------------------------------------------
251 * 0 | 0 | No interrupt
252 * 1 | 0 | INTA#
253 * 2 | 1 | INTB#
254 * 3 | 2 | INTC#
255 * 4 | 3 | INTD#
256 * any other value | 0 | This should never happen, log error message
257 */
258
259 static inline uint8_t xen_pt_pci_read_intx(XenPCIPassthroughState *s)
260 {
261 uint8_t v = 0;
262 xen_host_pci_get_byte(&s->real_device, PCI_INTERRUPT_PIN, &v);
263 return v;
264 }
265
266 static inline uint8_t xen_pt_pci_intx(XenPCIPassthroughState *s)
267 {
268 uint8_t r_val = xen_pt_pci_read_intx(s);
269
270 XEN_PT_LOG(&s->dev, "intx=%i\n", r_val);
271 if (r_val < 1 || r_val > 4) {
272 XEN_PT_LOG(&s->dev, "Interrupt pin read from hardware is out of range:"
273 " value=%i, acceptable range is 1 - 4\n", r_val);
274 r_val = 0;
275 } else {
276 r_val -= 1;
277 }
278
279 return r_val;
280 }
281
282 /* MSI/MSI-X */
283 int xen_pt_msi_set_enable(XenPCIPassthroughState *s, bool en);
284 int xen_pt_msi_setup(XenPCIPassthroughState *s);
285 int xen_pt_msi_update(XenPCIPassthroughState *d);
286 void xen_pt_msi_disable(XenPCIPassthroughState *s);
287
288 int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base);
289 void xen_pt_msix_delete(XenPCIPassthroughState *s);
290 int xen_pt_msix_update(XenPCIPassthroughState *s);
291 int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index);
292 void xen_pt_msix_disable(XenPCIPassthroughState *s);
293
294 static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
295 {
296 return s->msix && s->msix->bar_index == bar;
297 }
298
299
300 #endif /* !XEN_PT_H */