PPC: e500mc: add missing IVORs to bitmap
[qemu.git] / hw / xilinx_axienet.c
1 /*
2 * QEMU model of Xilinx AXI-Ethernet.
3 *
4 * Copyright (c) 2011 Edgar E. Iglesias.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "sysbus.h"
26 #include "qemu-char.h"
27 #include "qemu-log.h"
28 #include "net.h"
29 #include "net/checksum.h"
30
31 #include "xilinx_axidma.h"
32
33 #define DPHY(x)
34
35 /* Advertisement control register. */
36 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
37 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
38 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
39 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
40
41 struct PHY {
42 uint32_t regs[32];
43
44 int link;
45
46 unsigned int (*read)(struct PHY *phy, unsigned int req);
47 void (*write)(struct PHY *phy, unsigned int req,
48 unsigned int data);
49 };
50
51 static unsigned int tdk_read(struct PHY *phy, unsigned int req)
52 {
53 int regnum;
54 unsigned r = 0;
55
56 regnum = req & 0x1f;
57
58 switch (regnum) {
59 case 1:
60 if (!phy->link) {
61 break;
62 }
63 /* MR1. */
64 /* Speeds and modes. */
65 r |= (1 << 13) | (1 << 14);
66 r |= (1 << 11) | (1 << 12);
67 r |= (1 << 5); /* Autoneg complete. */
68 r |= (1 << 3); /* Autoneg able. */
69 r |= (1 << 2); /* link. */
70 r |= (1 << 1); /* link. */
71 break;
72 case 5:
73 /* Link partner ability.
74 We are kind; always agree with whatever best mode
75 the guest advertises. */
76 r = 1 << 14; /* Success. */
77 /* Copy advertised modes. */
78 r |= phy->regs[4] & (15 << 5);
79 /* Autoneg support. */
80 r |= 1;
81 break;
82 case 17:
83 /* Marvel PHY on many xilinx boards. */
84 r = 0x8000; /* 1000Mb */
85 break;
86 case 18:
87 {
88 /* Diagnostics reg. */
89 int duplex = 0;
90 int speed_100 = 0;
91
92 if (!phy->link) {
93 break;
94 }
95
96 /* Are we advertising 100 half or 100 duplex ? */
97 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
98 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
99
100 /* Are we advertising 10 duplex or 100 duplex ? */
101 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
102 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
103 r = (speed_100 << 10) | (duplex << 11);
104 }
105 break;
106
107 default:
108 r = phy->regs[regnum];
109 break;
110 }
111 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
112 return r;
113 }
114
115 static void
116 tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
117 {
118 int regnum;
119
120 regnum = req & 0x1f;
121 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
122 switch (regnum) {
123 default:
124 phy->regs[regnum] = data;
125 break;
126 }
127 }
128
129 static void
130 tdk_init(struct PHY *phy)
131 {
132 phy->regs[0] = 0x3100;
133 /* PHY Id. */
134 phy->regs[2] = 0x0300;
135 phy->regs[3] = 0xe400;
136 /* Autonegotiation advertisement reg. */
137 phy->regs[4] = 0x01E1;
138 phy->link = 1;
139
140 phy->read = tdk_read;
141 phy->write = tdk_write;
142 }
143
144 struct MDIOBus {
145 /* bus. */
146 int mdc;
147 int mdio;
148
149 /* decoder. */
150 enum {
151 PREAMBLE,
152 SOF,
153 OPC,
154 ADDR,
155 REQ,
156 TURNAROUND,
157 DATA
158 } state;
159 unsigned int drive;
160
161 unsigned int cnt;
162 unsigned int addr;
163 unsigned int opc;
164 unsigned int req;
165 unsigned int data;
166
167 struct PHY *devs[32];
168 };
169
170 static void
171 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
172 {
173 bus->devs[addr & 0x1f] = phy;
174 }
175
176 #ifdef USE_THIS_DEAD_CODE
177 static void
178 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
179 {
180 bus->devs[addr & 0x1f] = NULL;
181 }
182 #endif
183
184 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
185 unsigned int reg)
186 {
187 struct PHY *phy;
188 uint16_t data;
189
190 phy = bus->devs[addr];
191 if (phy && phy->read) {
192 data = phy->read(phy, reg);
193 } else {
194 data = 0xffff;
195 }
196 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
197 return data;
198 }
199
200 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
201 unsigned int reg, uint16_t data)
202 {
203 struct PHY *phy;
204
205 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
206 phy = bus->devs[addr];
207 if (phy && phy->write) {
208 phy->write(phy, reg, data);
209 }
210 }
211
212 #define DENET(x)
213
214 #define R_RAF (0x000 / 4)
215 enum {
216 RAF_MCAST_REJ = (1 << 1),
217 RAF_BCAST_REJ = (1 << 2),
218 RAF_EMCF_EN = (1 << 12),
219 RAF_NEWFUNC_EN = (1 << 11)
220 };
221
222 #define R_IS (0x00C / 4)
223 enum {
224 IS_HARD_ACCESS_COMPLETE = 1,
225 IS_AUTONEG = (1 << 1),
226 IS_RX_COMPLETE = (1 << 2),
227 IS_RX_REJECT = (1 << 3),
228 IS_TX_COMPLETE = (1 << 5),
229 IS_RX_DCM_LOCK = (1 << 6),
230 IS_MGM_RDY = (1 << 7),
231 IS_PHY_RST_DONE = (1 << 8),
232 };
233
234 #define R_IP (0x010 / 4)
235 #define R_IE (0x014 / 4)
236 #define R_UAWL (0x020 / 4)
237 #define R_UAWU (0x024 / 4)
238 #define R_PPST (0x030 / 4)
239 enum {
240 PPST_LINKSTATUS = (1 << 0),
241 PPST_PHY_LINKSTATUS = (1 << 7),
242 };
243
244 #define R_STATS_RX_BYTESL (0x200 / 4)
245 #define R_STATS_RX_BYTESH (0x204 / 4)
246 #define R_STATS_TX_BYTESL (0x208 / 4)
247 #define R_STATS_TX_BYTESH (0x20C / 4)
248 #define R_STATS_RXL (0x290 / 4)
249 #define R_STATS_RXH (0x294 / 4)
250 #define R_STATS_RX_BCASTL (0x2a0 / 4)
251 #define R_STATS_RX_BCASTH (0x2a4 / 4)
252 #define R_STATS_RX_MCASTL (0x2a8 / 4)
253 #define R_STATS_RX_MCASTH (0x2ac / 4)
254
255 #define R_RCW0 (0x400 / 4)
256 #define R_RCW1 (0x404 / 4)
257 enum {
258 RCW1_VLAN = (1 << 27),
259 RCW1_RX = (1 << 28),
260 RCW1_FCS = (1 << 29),
261 RCW1_JUM = (1 << 30),
262 RCW1_RST = (1 << 31),
263 };
264
265 #define R_TC (0x408 / 4)
266 enum {
267 TC_VLAN = (1 << 27),
268 TC_TX = (1 << 28),
269 TC_FCS = (1 << 29),
270 TC_JUM = (1 << 30),
271 TC_RST = (1 << 31),
272 };
273
274 #define R_EMMC (0x410 / 4)
275 enum {
276 EMMC_LINKSPEED_10MB = (0 << 30),
277 EMMC_LINKSPEED_100MB = (1 << 30),
278 EMMC_LINKSPEED_1000MB = (2 << 30),
279 };
280
281 #define R_PHYC (0x414 / 4)
282
283 #define R_MC (0x500 / 4)
284 #define MC_EN (1 << 6)
285
286 #define R_MCR (0x504 / 4)
287 #define R_MWD (0x508 / 4)
288 #define R_MRD (0x50c / 4)
289 #define R_MIS (0x600 / 4)
290 #define R_MIP (0x620 / 4)
291 #define R_MIE (0x640 / 4)
292 #define R_MIC (0x640 / 4)
293
294 #define R_UAW0 (0x700 / 4)
295 #define R_UAW1 (0x704 / 4)
296 #define R_FMI (0x708 / 4)
297 #define R_AF0 (0x710 / 4)
298 #define R_AF1 (0x714 / 4)
299 #define R_MAX (0x34 / 4)
300
301 /* Indirect registers. */
302 struct TEMAC {
303 struct MDIOBus mdio_bus;
304 struct PHY phy;
305
306 void *parent;
307 };
308
309 struct XilinxAXIEnet {
310 SysBusDevice busdev;
311 MemoryRegion iomem;
312 qemu_irq irq;
313 void *dmach;
314 NICState *nic;
315 NICConf conf;
316
317
318 uint32_t c_rxmem;
319 uint32_t c_txmem;
320 uint32_t c_phyaddr;
321
322 struct TEMAC TEMAC;
323
324 /* MII regs. */
325 union {
326 uint32_t regs[4];
327 struct {
328 uint32_t mc;
329 uint32_t mcr;
330 uint32_t mwd;
331 uint32_t mrd;
332 };
333 } mii;
334
335 struct {
336 uint64_t rx_bytes;
337 uint64_t tx_bytes;
338
339 uint64_t rx;
340 uint64_t rx_bcast;
341 uint64_t rx_mcast;
342 } stats;
343
344 /* Receive configuration words. */
345 uint32_t rcw[2];
346 /* Transmit config. */
347 uint32_t tc;
348 uint32_t emmc;
349 uint32_t phyc;
350
351 /* Unicast Address Word. */
352 uint32_t uaw[2];
353 /* Unicast address filter used with extended mcast. */
354 uint32_t ext_uaw[2];
355 uint32_t fmi;
356
357 uint32_t regs[R_MAX];
358
359 /* Multicast filter addrs. */
360 uint32_t maddr[4][2];
361 /* 32K x 1 lookup filter. */
362 uint32_t ext_mtable[1024];
363
364
365 uint8_t *rxmem;
366 };
367
368 static void axienet_rx_reset(struct XilinxAXIEnet *s)
369 {
370 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
371 }
372
373 static void axienet_tx_reset(struct XilinxAXIEnet *s)
374 {
375 s->tc = TC_JUM | TC_TX | TC_VLAN;
376 }
377
378 static inline int axienet_rx_resetting(struct XilinxAXIEnet *s)
379 {
380 return s->rcw[1] & RCW1_RST;
381 }
382
383 static inline int axienet_rx_enabled(struct XilinxAXIEnet *s)
384 {
385 return s->rcw[1] & RCW1_RX;
386 }
387
388 static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s)
389 {
390 return !!(s->regs[R_RAF] & RAF_EMCF_EN);
391 }
392
393 static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s)
394 {
395 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
396 }
397
398 static void axienet_reset(struct XilinxAXIEnet *s)
399 {
400 axienet_rx_reset(s);
401 axienet_tx_reset(s);
402
403 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
404 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
405
406 s->emmc = EMMC_LINKSPEED_100MB;
407 }
408
409 static void enet_update_irq(struct XilinxAXIEnet *s)
410 {
411 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
412 qemu_set_irq(s->irq, !!s->regs[R_IP]);
413 }
414
415 static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
416 {
417 struct XilinxAXIEnet *s = opaque;
418 uint32_t r = 0;
419 addr >>= 2;
420
421 switch (addr) {
422 case R_RCW0:
423 case R_RCW1:
424 r = s->rcw[addr & 1];
425 break;
426
427 case R_TC:
428 r = s->tc;
429 break;
430
431 case R_EMMC:
432 r = s->emmc;
433 break;
434
435 case R_PHYC:
436 r = s->phyc;
437 break;
438
439 case R_MCR:
440 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */
441 break;
442
443 case R_STATS_RX_BYTESL:
444 case R_STATS_RX_BYTESH:
445 r = s->stats.rx_bytes >> (32 * (addr & 1));
446 break;
447
448 case R_STATS_TX_BYTESL:
449 case R_STATS_TX_BYTESH:
450 r = s->stats.tx_bytes >> (32 * (addr & 1));
451 break;
452
453 case R_STATS_RXL:
454 case R_STATS_RXH:
455 r = s->stats.rx >> (32 * (addr & 1));
456 break;
457 case R_STATS_RX_BCASTL:
458 case R_STATS_RX_BCASTH:
459 r = s->stats.rx_bcast >> (32 * (addr & 1));
460 break;
461 case R_STATS_RX_MCASTL:
462 case R_STATS_RX_MCASTH:
463 r = s->stats.rx_mcast >> (32 * (addr & 1));
464 break;
465
466 case R_MC:
467 case R_MWD:
468 case R_MRD:
469 r = s->mii.regs[addr & 3];
470 break;
471
472 case R_UAW0:
473 case R_UAW1:
474 r = s->uaw[addr & 1];
475 break;
476
477 case R_UAWU:
478 case R_UAWL:
479 r = s->ext_uaw[addr & 1];
480 break;
481
482 case R_FMI:
483 r = s->fmi;
484 break;
485
486 case R_AF0:
487 case R_AF1:
488 r = s->maddr[s->fmi & 3][addr & 1];
489 break;
490
491 case 0x8000 ... 0x83ff:
492 r = s->ext_mtable[addr - 0x8000];
493 break;
494
495 default:
496 if (addr < ARRAY_SIZE(s->regs)) {
497 r = s->regs[addr];
498 }
499 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
500 __func__, addr * 4, r));
501 break;
502 }
503 return r;
504 }
505
506 static void enet_write(void *opaque, target_phys_addr_t addr,
507 uint64_t value, unsigned size)
508 {
509 struct XilinxAXIEnet *s = opaque;
510 struct TEMAC *t = &s->TEMAC;
511
512 addr >>= 2;
513 switch (addr) {
514 case R_RCW0:
515 case R_RCW1:
516 s->rcw[addr & 1] = value;
517 if ((addr & 1) && value & RCW1_RST) {
518 axienet_rx_reset(s);
519 }
520 break;
521
522 case R_TC:
523 s->tc = value;
524 if (value & TC_RST) {
525 axienet_tx_reset(s);
526 }
527 break;
528
529 case R_EMMC:
530 s->emmc = value;
531 break;
532
533 case R_PHYC:
534 s->phyc = value;
535 break;
536
537 case R_MC:
538 value &= ((1 < 7) - 1);
539
540 /* Enable the MII. */
541 if (value & MC_EN) {
542 unsigned int miiclkdiv = value & ((1 << 6) - 1);
543 if (!miiclkdiv) {
544 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
545 }
546 }
547 s->mii.mc = value;
548 break;
549
550 case R_MCR: {
551 unsigned int phyaddr = (value >> 24) & 0x1f;
552 unsigned int regaddr = (value >> 16) & 0x1f;
553 unsigned int op = (value >> 14) & 3;
554 unsigned int initiate = (value >> 11) & 1;
555
556 if (initiate) {
557 if (op == 1) {
558 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
559 } else if (op == 2) {
560 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
561 } else {
562 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
563 }
564 }
565 s->mii.mcr = value;
566 break;
567 }
568
569 case R_MWD:
570 case R_MRD:
571 s->mii.regs[addr & 3] = value;
572 break;
573
574
575 case R_UAW0:
576 case R_UAW1:
577 s->uaw[addr & 1] = value;
578 break;
579
580 case R_UAWL:
581 case R_UAWU:
582 s->ext_uaw[addr & 1] = value;
583 break;
584
585 case R_FMI:
586 s->fmi = value;
587 break;
588
589 case R_AF0:
590 case R_AF1:
591 s->maddr[s->fmi & 3][addr & 1] = value;
592 break;
593
594 case 0x8000 ... 0x83ff:
595 s->ext_mtable[addr - 0x8000] = value;
596 break;
597
598 default:
599 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
600 __func__, addr * 4, (unsigned)value));
601 if (addr < ARRAY_SIZE(s->regs)) {
602 s->regs[addr] = value;
603 }
604 break;
605 }
606 enet_update_irq(s);
607 }
608
609 static const MemoryRegionOps enet_ops = {
610 .read = enet_read,
611 .write = enet_write,
612 .endianness = DEVICE_LITTLE_ENDIAN,
613 };
614
615 static int eth_can_rx(VLANClientState *nc)
616 {
617 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
618
619 /* RX enabled? */
620 return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
621 }
622
623 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
624 {
625 int match = 1;
626
627 if (memcmp(buf, &f0, 4)) {
628 match = 0;
629 }
630
631 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
632 match = 0;
633 }
634
635 return match;
636 }
637
638 static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
639 {
640 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
641 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
642 0xff, 0xff, 0xff};
643 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
644 uint32_t app[6] = {0};
645 int promisc = s->fmi & (1 << 31);
646 int unicast, broadcast, multicast, ip_multicast = 0;
647 uint32_t csum32;
648 uint16_t csum16;
649 int i;
650
651 s = s;
652 DENET(qemu_log("%s: %zd bytes\n", __func__, size));
653
654 unicast = ~buf[0] & 0x1;
655 broadcast = memcmp(buf, sa_bcast, 6) == 0;
656 multicast = !unicast && !broadcast;
657 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
658 ip_multicast = 1;
659 }
660
661 /* Jumbo or vlan sizes ? */
662 if (!(s->rcw[1] & RCW1_JUM)) {
663 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
664 return size;
665 }
666 }
667
668 /* Basic Address filters. If you want to use the extended filters
669 you'll generally have to place the ethernet mac into promiscuous mode
670 to avoid the basic filtering from dropping most frames. */
671 if (!promisc) {
672 if (unicast) {
673 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
674 return size;
675 }
676 } else {
677 if (broadcast) {
678 /* Broadcast. */
679 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
680 return size;
681 }
682 } else {
683 int drop = 1;
684
685 /* Multicast. */
686 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
687 return size;
688 }
689
690 for (i = 0; i < 4; i++) {
691 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
692 drop = 0;
693 break;
694 }
695 }
696
697 if (drop) {
698 return size;
699 }
700 }
701 }
702 }
703
704 /* Extended mcast filtering enabled? */
705 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
706 if (unicast) {
707 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
708 return size;
709 }
710 } else {
711 if (broadcast) {
712 /* Broadcast. ??? */
713 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
714 return size;
715 }
716 } else {
717 int idx, bit;
718
719 /* Multicast. */
720 if (!memcmp(buf, sa_ipmcast, 3)) {
721 return size;
722 }
723
724 idx = (buf[4] & 0x7f) << 8;
725 idx |= buf[5];
726
727 bit = 1 << (idx & 0x1f);
728 idx >>= 5;
729
730 if (!(s->ext_mtable[idx] & bit)) {
731 return size;
732 }
733 }
734 }
735 }
736
737 if (size < 12) {
738 s->regs[R_IS] |= IS_RX_REJECT;
739 enet_update_irq(s);
740 return -1;
741 }
742
743 if (size > (s->c_rxmem - 4)) {
744 size = s->c_rxmem - 4;
745 }
746
747 memcpy(s->rxmem, buf, size);
748 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */
749
750 if (s->rcw[1] & RCW1_FCS) {
751 size += 4; /* fcs is inband. */
752 }
753
754 app[0] = 5 << 28;
755 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
756 /* Fold it once. */
757 csum32 = (csum32 & 0xffff) + (csum32 >> 16);
758 /* And twice to get rid of possible carries. */
759 csum16 = (csum32 & 0xffff) + (csum32 >> 16);
760 app[3] = csum16;
761 app[4] = size & 0xffff;
762
763 s->stats.rx_bytes += size;
764 s->stats.rx++;
765 if (multicast) {
766 s->stats.rx_mcast++;
767 app[2] |= 1 | (ip_multicast << 1);
768 } else if (broadcast) {
769 s->stats.rx_bcast++;
770 app[2] |= 1 << 3;
771 }
772
773 /* Good frame. */
774 app[2] |= 1 << 6;
775
776 xlx_dma_push_to_dma(s->dmach, (void *)s->rxmem, size, app);
777
778 s->regs[R_IS] |= IS_RX_COMPLETE;
779 enet_update_irq(s);
780 return size;
781 }
782
783 static void eth_cleanup(VLANClientState *nc)
784 {
785 /* FIXME. */
786 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
787 g_free(s->rxmem);
788 g_free(s);
789 }
790
791 static void
792 axienet_stream_push(void *opaque, uint8_t *buf, size_t size, uint32_t *hdr)
793 {
794 struct XilinxAXIEnet *s = opaque;
795
796 /* TX enable ? */
797 if (!(s->tc & TC_TX)) {
798 return;
799 }
800
801 /* Jumbo or vlan sizes ? */
802 if (!(s->tc & TC_JUM)) {
803 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
804 return;
805 }
806 }
807
808 if (hdr[0] & 1) {
809 unsigned int start_off = hdr[1] >> 16;
810 unsigned int write_off = hdr[1] & 0xffff;
811 uint32_t tmp_csum;
812 uint16_t csum;
813
814 tmp_csum = net_checksum_add(size - start_off,
815 (uint8_t *)buf + start_off);
816 /* Accumulate the seed. */
817 tmp_csum += hdr[2] & 0xffff;
818
819 /* Fold the 32bit partial checksum. */
820 csum = net_checksum_finish(tmp_csum);
821
822 /* Writeback. */
823 buf[write_off] = csum >> 8;
824 buf[write_off + 1] = csum & 0xff;
825 }
826
827 qemu_send_packet(&s->nic->nc, buf, size);
828
829 s->stats.tx_bytes += size;
830 s->regs[R_IS] |= IS_TX_COMPLETE;
831 enet_update_irq(s);
832 }
833
834 static NetClientInfo net_xilinx_enet_info = {
835 .type = NET_CLIENT_TYPE_NIC,
836 .size = sizeof(NICState),
837 .can_receive = eth_can_rx,
838 .receive = eth_rx,
839 .cleanup = eth_cleanup,
840 };
841
842 static int xilinx_enet_init(SysBusDevice *dev)
843 {
844 struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
845
846 sysbus_init_irq(dev, &s->irq);
847
848 if (!s->dmach) {
849 hw_error("Unconnected Xilinx Ethernet MAC.\n");
850 }
851
852 xlx_dma_connect_client(s->dmach, s, axienet_stream_push);
853
854 memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000);
855 sysbus_init_mmio(dev, &s->iomem);
856
857 qemu_macaddr_default_if_unset(&s->conf.macaddr);
858 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
859 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
860 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
861
862 tdk_init(&s->TEMAC.phy);
863 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
864
865 s->TEMAC.parent = s;
866
867 s->rxmem = g_malloc(s->c_rxmem);
868 axienet_reset(s);
869
870 return 0;
871 }
872
873 static Property xilinx_enet_properties[] = {
874 DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7),
875 DEFINE_PROP_UINT32("c_rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000),
876 DEFINE_PROP_UINT32("c_txmem", struct XilinxAXIEnet, c_txmem, 0x1000),
877 DEFINE_PROP_PTR("dmach", struct XilinxAXIEnet, dmach),
878 DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf),
879 DEFINE_PROP_END_OF_LIST(),
880 };
881
882 static void xilinx_enet_class_init(ObjectClass *klass, void *data)
883 {
884 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
885
886 k->init = xilinx_enet_init;
887 }
888
889 static DeviceInfo xilinx_enet_info = {
890 .name = "xilinx,axienet",
891 .size = sizeof(struct XilinxAXIEnet),
892 .props = xilinx_enet_properties,
893 .class_init = xilinx_enet_class_init,
894 };
895 static void xilinx_enet_register(void)
896 {
897 sysbus_register_withprop(&xilinx_enet_info);
898 }
899
900 device_init(xilinx_enet_register)