cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / hw / xtensa / pic_cpu.c
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include "hw/hw.h"
29 #include "qemu/log.h"
30 #include "qemu/timer.h"
31
32 void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
33 {
34 uint32_t old_ccount = env->sregs[CCOUNT];
35
36 env->sregs[CCOUNT] += d;
37
38 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
39 int i;
40 for (i = 0; i < env->config->nccompare; ++i) {
41 if (env->sregs[CCOMPARE + i] - old_ccount <= d) {
42 xtensa_timer_irq(env, i, 1);
43 }
44 }
45 }
46 }
47
48 void check_interrupts(CPUXtensaState *env)
49 {
50 CPUState *cs = CPU(xtensa_env_get_cpu(env));
51 int minlevel = xtensa_get_cintlevel(env);
52 uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
53 int level;
54
55 /* If the CPU is halted advance CCOUNT according to the vm_clock time
56 * elapsed since the moment when it was advanced last time.
57 */
58 if (cs->halted) {
59 int64_t now = qemu_get_clock_ns(vm_clock);
60
61 xtensa_advance_ccount(env,
62 muldiv64(now - env->halt_clock,
63 env->config->clock_freq_khz, 1000000));
64 env->halt_clock = now;
65 }
66 for (level = env->config->nlevel; level > minlevel; --level) {
67 if (env->config->level_mask[level] & int_set_enabled) {
68 env->pending_irq_level = level;
69 cpu_interrupt(env, CPU_INTERRUPT_HARD);
70 qemu_log_mask(CPU_LOG_INT,
71 "%s level = %d, cintlevel = %d, "
72 "pc = %08x, a0 = %08x, ps = %08x, "
73 "intset = %08x, intenable = %08x, "
74 "ccount = %08x\n",
75 __func__, level, xtensa_get_cintlevel(env),
76 env->pc, env->regs[0], env->sregs[PS],
77 env->sregs[INTSET], env->sregs[INTENABLE],
78 env->sregs[CCOUNT]);
79 return;
80 }
81 }
82 env->pending_irq_level = 0;
83 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
84 }
85
86 static void xtensa_set_irq(void *opaque, int irq, int active)
87 {
88 CPUXtensaState *env = opaque;
89
90 if (irq >= env->config->ninterrupt) {
91 qemu_log("%s: bad IRQ %d\n", __func__, irq);
92 } else {
93 uint32_t irq_bit = 1 << irq;
94
95 if (active) {
96 env->sregs[INTSET] |= irq_bit;
97 } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
98 env->sregs[INTSET] &= ~irq_bit;
99 }
100
101 check_interrupts(env);
102 }
103 }
104
105 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
106 {
107 qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
108 }
109
110 void xtensa_rearm_ccompare_timer(CPUXtensaState *env)
111 {
112 int i;
113 uint32_t wake_ccount = env->sregs[CCOUNT] - 1;
114
115 for (i = 0; i < env->config->nccompare; ++i) {
116 if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] <
117 wake_ccount - env->sregs[CCOUNT]) {
118 wake_ccount = env->sregs[CCOMPARE + i];
119 }
120 }
121 env->wake_ccount = wake_ccount;
122 qemu_mod_timer(env->ccompare_timer, env->halt_clock +
123 muldiv64(wake_ccount - env->sregs[CCOUNT],
124 1000000, env->config->clock_freq_khz));
125 }
126
127 static void xtensa_ccompare_cb(void *opaque)
128 {
129 XtensaCPU *cpu = opaque;
130 CPUXtensaState *env = &cpu->env;
131 CPUState *cs = CPU(cpu);
132
133 if (cs->halted) {
134 env->halt_clock = qemu_get_clock_ns(vm_clock);
135 xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]);
136 if (!cpu_has_work(cs)) {
137 env->sregs[CCOUNT] = env->wake_ccount + 1;
138 xtensa_rearm_ccompare_timer(env);
139 }
140 }
141 }
142
143 void xtensa_irq_init(CPUXtensaState *env)
144 {
145 XtensaCPU *cpu = xtensa_env_get_cpu(env);
146
147 env->irq_inputs = (void **)qemu_allocate_irqs(
148 xtensa_set_irq, env, env->config->ninterrupt);
149 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&
150 env->config->nccompare > 0) {
151 env->ccompare_timer =
152 qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, cpu);
153 }
154 }
155
156 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
157 {
158 if (extint < env->config->nextint) {
159 unsigned irq = env->config->extint[extint];
160 return env->irq_inputs[irq];
161 } else {
162 qemu_log("%s: trying to acquire invalid external interrupt %d\n",
163 __func__, extint);
164 return NULL;
165 }
166 }