linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / zaurus.c
1 /*
2 * Copyright (c) 2006-2008 Openedhand Ltd.
3 * Written by Andrzej Zaborowski <balrog@zabor.org>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 or
8 * (at your option) version 3 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18 #include "hw.h"
19 #include "sharpsl.h"
20 #include "sysbus.h"
21
22 #undef REG_FMT
23 #define REG_FMT "0x%02lx"
24
25 /* SCOOP devices */
26
27 typedef struct ScoopInfo ScoopInfo;
28 struct ScoopInfo {
29 SysBusDevice busdev;
30 qemu_irq handler[16];
31 MemoryRegion iomem;
32 uint16_t status;
33 uint16_t power;
34 uint32_t gpio_level;
35 uint32_t gpio_dir;
36 uint32_t prev_level;
37
38 uint16_t mcr;
39 uint16_t cdr;
40 uint16_t ccr;
41 uint16_t irr;
42 uint16_t imr;
43 uint16_t isr;
44 };
45
46 #define SCOOP_MCR 0x00
47 #define SCOOP_CDR 0x04
48 #define SCOOP_CSR 0x08
49 #define SCOOP_CPR 0x0c
50 #define SCOOP_CCR 0x10
51 #define SCOOP_IRR_IRM 0x14
52 #define SCOOP_IMR 0x18
53 #define SCOOP_ISR 0x1c
54 #define SCOOP_GPCR 0x20
55 #define SCOOP_GPWR 0x24
56 #define SCOOP_GPRR 0x28
57
58 static inline void scoop_gpio_handler_update(ScoopInfo *s) {
59 uint32_t level, diff;
60 int bit;
61 level = s->gpio_level & s->gpio_dir;
62
63 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
64 bit = ffs(diff) - 1;
65 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
66 }
67
68 s->prev_level = level;
69 }
70
71 static uint64_t scoop_read(void *opaque, target_phys_addr_t addr,
72 unsigned size)
73 {
74 ScoopInfo *s = (ScoopInfo *) opaque;
75
76 switch (addr & 0x3f) {
77 case SCOOP_MCR:
78 return s->mcr;
79 case SCOOP_CDR:
80 return s->cdr;
81 case SCOOP_CSR:
82 return s->status;
83 case SCOOP_CPR:
84 return s->power;
85 case SCOOP_CCR:
86 return s->ccr;
87 case SCOOP_IRR_IRM:
88 return s->irr;
89 case SCOOP_IMR:
90 return s->imr;
91 case SCOOP_ISR:
92 return s->isr;
93 case SCOOP_GPCR:
94 return s->gpio_dir;
95 case SCOOP_GPWR:
96 case SCOOP_GPRR:
97 return s->gpio_level;
98 default:
99 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
100 }
101
102 return 0;
103 }
104
105 static void scoop_write(void *opaque, target_phys_addr_t addr,
106 uint64_t value, unsigned size)
107 {
108 ScoopInfo *s = (ScoopInfo *) opaque;
109 value &= 0xffff;
110
111 switch (addr & 0x3f) {
112 case SCOOP_MCR:
113 s->mcr = value;
114 break;
115 case SCOOP_CDR:
116 s->cdr = value;
117 break;
118 case SCOOP_CPR:
119 s->power = value;
120 if (value & 0x80)
121 s->power |= 0x8040;
122 break;
123 case SCOOP_CCR:
124 s->ccr = value;
125 break;
126 case SCOOP_IRR_IRM:
127 s->irr = value;
128 break;
129 case SCOOP_IMR:
130 s->imr = value;
131 break;
132 case SCOOP_ISR:
133 s->isr = value;
134 break;
135 case SCOOP_GPCR:
136 s->gpio_dir = value;
137 scoop_gpio_handler_update(s);
138 break;
139 case SCOOP_GPWR:
140 case SCOOP_GPRR: /* GPRR is probably R/O in real HW */
141 s->gpio_level = value & s->gpio_dir;
142 scoop_gpio_handler_update(s);
143 break;
144 default:
145 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
146 }
147 }
148
149 static const MemoryRegionOps scoop_ops = {
150 .read = scoop_read,
151 .write = scoop_write,
152 .endianness = DEVICE_NATIVE_ENDIAN,
153 };
154
155 static void scoop_gpio_set(void *opaque, int line, int level)
156 {
157 ScoopInfo *s = (ScoopInfo *) opaque;
158
159 if (level)
160 s->gpio_level |= (1 << line);
161 else
162 s->gpio_level &= ~(1 << line);
163 }
164
165 static int scoop_init(SysBusDevice *dev)
166 {
167 ScoopInfo *s = FROM_SYSBUS(ScoopInfo, dev);
168
169 s->status = 0x02;
170 qdev_init_gpio_out(&s->busdev.qdev, s->handler, 16);
171 qdev_init_gpio_in(&s->busdev.qdev, scoop_gpio_set, 16);
172 memory_region_init_io(&s->iomem, &scoop_ops, s, "scoop", 0x1000);
173
174 sysbus_init_mmio(dev, &s->iomem);
175
176 return 0;
177 }
178
179 static int scoop_post_load(void *opaque, int version_id)
180 {
181 ScoopInfo *s = (ScoopInfo *) opaque;
182 int i;
183 uint32_t level;
184
185 level = s->gpio_level & s->gpio_dir;
186
187 for (i = 0; i < 16; i++) {
188 qemu_set_irq(s->handler[i], (level >> i) & 1);
189 }
190
191 s->prev_level = level;
192
193 return 0;
194 }
195
196 static bool is_version_0 (void *opaque, int version_id)
197 {
198 return version_id == 0;
199 }
200
201 static const VMStateDescription vmstate_scoop_regs = {
202 .name = "scoop",
203 .version_id = 1,
204 .minimum_version_id = 0,
205 .minimum_version_id_old = 0,
206 .post_load = scoop_post_load,
207 .fields = (VMStateField []) {
208 VMSTATE_UINT16(status, ScoopInfo),
209 VMSTATE_UINT16(power, ScoopInfo),
210 VMSTATE_UINT32(gpio_level, ScoopInfo),
211 VMSTATE_UINT32(gpio_dir, ScoopInfo),
212 VMSTATE_UINT32(prev_level, ScoopInfo),
213 VMSTATE_UINT16(mcr, ScoopInfo),
214 VMSTATE_UINT16(cdr, ScoopInfo),
215 VMSTATE_UINT16(ccr, ScoopInfo),
216 VMSTATE_UINT16(irr, ScoopInfo),
217 VMSTATE_UINT16(imr, ScoopInfo),
218 VMSTATE_UINT16(isr, ScoopInfo),
219 VMSTATE_UNUSED_TEST(is_version_0, 2),
220 VMSTATE_END_OF_LIST(),
221 },
222 };
223
224 static Property scoop_sysbus_properties[] = {
225 DEFINE_PROP_END_OF_LIST(),
226 };
227
228 static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
229 {
230 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
231
232 k->init = scoop_init;
233 }
234
235 static DeviceInfo scoop_sysbus_info = {
236 .name = "scoop",
237 .desc = "Scoop2 Sharp custom ASIC",
238 .size = sizeof(ScoopInfo),
239 .vmsd = &vmstate_scoop_regs,
240 .props = scoop_sysbus_properties,
241 .class_init = scoop_sysbus_class_init,
242 };
243
244 static void scoop_register(void)
245 {
246 sysbus_register_withprop(&scoop_sysbus_info);
247 }
248 device_init(scoop_register);
249
250 /* Write the bootloader parameters memory area. */
251
252 #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
253
254 static struct QEMU_PACKED sl_param_info {
255 uint32_t comadj_keyword;
256 int32_t comadj;
257
258 uint32_t uuid_keyword;
259 char uuid[16];
260
261 uint32_t touch_keyword;
262 int32_t touch_xp;
263 int32_t touch_yp;
264 int32_t touch_xd;
265 int32_t touch_yd;
266
267 uint32_t adadj_keyword;
268 int32_t adadj;
269
270 uint32_t phad_keyword;
271 int32_t phadadj;
272 } zaurus_bootparam = {
273 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
274 .comadj = 125,
275 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
276 .uuid = { -1 },
277 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
278 .touch_xp = -1,
279 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
280 .adadj = -1,
281 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
282 .phadadj = 0x01,
283 };
284
285 void sl_bootparam_write(target_phys_addr_t ptr)
286 {
287 cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
288 sizeof(struct sl_param_info));
289 }