linux-user: add open() hijack infrastructure
[qemu.git] / ia64-dis.c
1 /* ia64-dis.c -- Disassemble ia64 instructions
2 Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, see
19 <http://www.gnu.org/licenses/>. */
20
21 #include <assert.h>
22 #include <string.h>
23
24 #include "dis-asm.h"
25
26 /* ia64.h -- Header file for ia64 opcode table
27 Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
28 Free Software Foundation, Inc.
29 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
30
31 #include <sys/types.h>
32
33 typedef uint64_t ia64_insn;
34
35 enum ia64_insn_type
36 {
37 IA64_TYPE_NIL = 0, /* illegal type */
38 IA64_TYPE_A, /* integer alu (I- or M-unit) */
39 IA64_TYPE_I, /* non-alu integer (I-unit) */
40 IA64_TYPE_M, /* memory (M-unit) */
41 IA64_TYPE_B, /* branch (B-unit) */
42 IA64_TYPE_F, /* floating-point (F-unit) */
43 IA64_TYPE_X, /* long encoding (X-unit) */
44 IA64_TYPE_DYN, /* Dynamic opcode */
45 IA64_NUM_TYPES
46 };
47
48 enum ia64_unit
49 {
50 IA64_UNIT_NIL = 0, /* illegal unit */
51 IA64_UNIT_I, /* integer unit */
52 IA64_UNIT_M, /* memory unit */
53 IA64_UNIT_B, /* branching unit */
54 IA64_UNIT_F, /* floating-point unit */
55 IA64_UNIT_L, /* long "unit" */
56 IA64_UNIT_X, /* may be integer or branch unit */
57 IA64_NUM_UNITS
58 };
59
60 /* Changes to this enumeration must be propagated to the operand table in
61 bfd/cpu-ia64-opc.c
62 */
63 enum ia64_opnd
64 {
65 IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
66
67 /* constants */
68 IA64_OPND_AR_CSD, /* application register csd (ar.csd) */
69 IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
70 IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
71 IA64_OPND_C1, /* the constant 1 */
72 IA64_OPND_C8, /* the constant 8 */
73 IA64_OPND_C16, /* the constant 16 */
74 IA64_OPND_GR0, /* gr0 */
75 IA64_OPND_IP, /* instruction pointer (ip) */
76 IA64_OPND_PR, /* predicate register (pr) */
77 IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
78 IA64_OPND_PSR, /* processor status register (psr) */
79 IA64_OPND_PSR_L, /* processor status register L (psr.l) */
80 IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
81
82 /* register operands: */
83 IA64_OPND_AR3, /* third application register # (bits 20-26) */
84 IA64_OPND_B1, /* branch register # (bits 6-8) */
85 IA64_OPND_B2, /* branch register # (bits 13-15) */
86 IA64_OPND_CR3, /* third control register # (bits 20-26) */
87 IA64_OPND_F1, /* first floating-point register # */
88 IA64_OPND_F2, /* second floating-point register # */
89 IA64_OPND_F3, /* third floating-point register # */
90 IA64_OPND_F4, /* fourth floating-point register # */
91 IA64_OPND_P1, /* first predicate # */
92 IA64_OPND_P2, /* second predicate # */
93 IA64_OPND_R1, /* first register # */
94 IA64_OPND_R2, /* second register # */
95 IA64_OPND_R3, /* third register # */
96 IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
97
98 /* memory operands: */
99 IA64_OPND_MR3, /* memory at addr of third register # */
100
101 /* indirect operands: */
102 IA64_OPND_CPUID_R3, /* cpuid[reg] */
103 IA64_OPND_DBR_R3, /* dbr[reg] */
104 IA64_OPND_DTR_R3, /* dtr[reg] */
105 IA64_OPND_ITR_R3, /* itr[reg] */
106 IA64_OPND_IBR_R3, /* ibr[reg] */
107 IA64_OPND_MSR_R3, /* msr[reg] */
108 IA64_OPND_PKR_R3, /* pkr[reg] */
109 IA64_OPND_PMC_R3, /* pmc[reg] */
110 IA64_OPND_PMD_R3, /* pmd[reg] */
111 IA64_OPND_RR_R3, /* rr[reg] */
112
113 /* immediate operands: */
114 IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
115 IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
116 IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
117 IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
118 IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
119 IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
120 IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
121 IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
122 IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
123 IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
124 IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
125 IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */
126 IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
127 IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
128 IA64_OPND_SOF, /* 8-bit stack frame size */
129 IA64_OPND_SOL, /* 8-bit size of locals */
130 IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
131 IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
132 IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
133 IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
134 IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
135 IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
136 IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
137 IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
138 IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
139 IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
140 IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
141 IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
142 IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
143 IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
144 IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
145 IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
146 IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
147 IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
148 IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
149 IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
150 IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
151 IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
152 IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
153 IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
154 IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
155 IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
156 IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
157 IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
158 IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
159 IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */
160
161 IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
162 };
163
164 enum ia64_dependency_mode
165 {
166 IA64_DV_RAW,
167 IA64_DV_WAW,
168 IA64_DV_WAR,
169 };
170
171 enum ia64_dependency_semantics
172 {
173 IA64_DVS_NONE,
174 IA64_DVS_IMPLIED,
175 IA64_DVS_IMPLIEDF,
176 IA64_DVS_DATA,
177 IA64_DVS_INSTR,
178 IA64_DVS_SPECIFIC,
179 IA64_DVS_STOP,
180 IA64_DVS_OTHER,
181 };
182
183 enum ia64_resource_specifier
184 {
185 IA64_RS_ANY,
186 IA64_RS_AR_K,
187 IA64_RS_AR_UNAT,
188 IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
189 IA64_RS_ARb, /* 48-63, 112-127 */
190 IA64_RS_BR,
191 IA64_RS_CFM,
192 IA64_RS_CPUID,
193 IA64_RS_CR_IRR,
194 IA64_RS_CR_LRR,
195 IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
196 IA64_RS_DBR,
197 IA64_RS_FR,
198 IA64_RS_FRb,
199 IA64_RS_GR0,
200 IA64_RS_GR,
201 IA64_RS_IBR,
202 IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
203 IA64_RS_MSR,
204 IA64_RS_PKR,
205 IA64_RS_PMC,
206 IA64_RS_PMD,
207 IA64_RS_PR, /* non-rotating, 1-15 */
208 IA64_RS_PRr, /* rotating, 16-62 */
209 IA64_RS_PR63,
210 IA64_RS_RR,
211
212 IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
213 IA64_RS_CRX, /* CRs not in RS_CR */
214 IA64_RS_PSR, /* PSR bits */
215 IA64_RS_RSE, /* implementation-specific RSE resources */
216 IA64_RS_AR_FPSR,
217 };
218
219 enum ia64_rse_resource
220 {
221 IA64_RSE_N_STACKED_PHYS,
222 IA64_RSE_BOF,
223 IA64_RSE_STORE_REG,
224 IA64_RSE_LOAD_REG,
225 IA64_RSE_BSPLOAD,
226 IA64_RSE_RNATBITINDEX,
227 IA64_RSE_CFLE,
228 IA64_RSE_NDIRTY,
229 };
230
231 /* Information about a given resource dependency */
232 struct ia64_dependency
233 {
234 /* Name of the resource */
235 const char *name;
236 /* Does this dependency need further specification? */
237 enum ia64_resource_specifier specifier;
238 /* Mode of dependency */
239 enum ia64_dependency_mode mode;
240 /* Dependency semantics */
241 enum ia64_dependency_semantics semantics;
242 /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
243 #define REG_NONE (-1)
244 int regindex;
245 /* Special info on semantics */
246 const char *info;
247 };
248
249 /* Two arrays of indexes into the ia64_dependency table.
250 chks are dependencies to check for conflicts when an opcode is
251 encountered; regs are dependencies to register (mark as used) when an
252 opcode is used. chks correspond to readers (RAW) or writers (WAW or
253 WAR) of a resource, while regs correspond to writers (RAW or WAW) and
254 readers (WAR) of a resource. */
255 struct ia64_opcode_dependency
256 {
257 int nchks;
258 const unsigned short *chks;
259 int nregs;
260 const unsigned short *regs;
261 };
262
263 /* encode/extract the note/index for a dependency */
264 #define RDEP(N,X) (((N)<<11)|(X))
265 #define NOTE(X) (((X)>>11)&0x1F)
266 #define DEP(X) ((X)&0x7FF)
267
268 /* A template descriptor describes the execution units that are active
269 for each of the three slots. It also specifies the location of
270 instruction group boundaries that may be present between two slots. */
271 struct ia64_templ_desc
272 {
273 int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
274 enum ia64_unit exec_unit[3];
275 const char *name;
276 };
277
278 /* The opcode table is an array of struct ia64_opcode. */
279
280 struct ia64_opcode
281 {
282 /* The opcode name. */
283 const char *name;
284
285 /* The type of the instruction: */
286 enum ia64_insn_type type;
287
288 /* Number of output operands: */
289 int num_outputs;
290
291 /* The opcode itself. Those bits which will be filled in with
292 operands are zeroes. */
293 ia64_insn opcode;
294
295 /* The opcode mask. This is used by the disassembler. This is a
296 mask containing ones indicating those bits which must match the
297 opcode field, and zeroes indicating those bits which need not
298 match (and are presumably filled in by operands). */
299 ia64_insn mask;
300
301 /* An array of operand codes. Each code is an index into the
302 operand table. They appear in the order which the operands must
303 appear in assembly code, and are terminated by a zero. */
304 enum ia64_opnd operands[5];
305
306 /* One bit flags for the opcode. These are primarily used to
307 indicate specific processors and environments support the
308 instructions. The defined values are listed below. */
309 unsigned int flags;
310
311 /* Used by ia64_find_next_opcode (). */
312 short ent_index;
313
314 /* Opcode dependencies. */
315 const struct ia64_opcode_dependency *dependencies;
316 };
317
318 /* Values defined for the flags field of a struct ia64_opcode. */
319
320 #define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
321 #define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
322 #define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
323 #define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
324 #define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
325 #define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
326 #define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
327 #define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
328 #define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
329 #define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
330 #define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
331
332 /* A macro to extract the major opcode from an instruction. */
333 #define IA64_OP(i) (((i) >> 37) & 0xf)
334
335 enum ia64_operand_class
336 {
337 IA64_OPND_CLASS_CST, /* constant */
338 IA64_OPND_CLASS_REG, /* register */
339 IA64_OPND_CLASS_IND, /* indirect register */
340 IA64_OPND_CLASS_ABS, /* absolute value */
341 IA64_OPND_CLASS_REL, /* IP-relative value */
342 };
343
344 /* The operands table is an array of struct ia64_operand. */
345
346 struct ia64_operand
347 {
348 enum ia64_operand_class class;
349
350 /* Set VALUE as the operand bits for the operand of type SELF in the
351 instruction pointed to by CODE. If an error occurs, *CODE is not
352 modified and the returned string describes the cause of the
353 error. If no error occurs, NULL is returned. */
354 const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
355 ia64_insn *code);
356
357 /* Extract the operand bits for an operand of type SELF from
358 instruction CODE store them in *VALUE. If an error occurs, the
359 cause of the error is described by the string returned. If no
360 error occurs, NULL is returned. */
361 const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
362 ia64_insn *value);
363
364 /* A string whose meaning depends on the operand class. */
365
366 const char *str;
367
368 struct bit_field
369 {
370 /* The number of bits in the operand. */
371 int bits;
372
373 /* How far the operand is left shifted in the instruction. */
374 int shift;
375 }
376 field[4]; /* no operand has more than this many bit-fields */
377
378 unsigned int flags;
379
380 const char *desc; /* brief description */
381 };
382
383 /* Values defined for the flags field of a struct ia64_operand. */
384
385 /* Disassemble as signed decimal (instead of hex): */
386 #define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
387 /* Disassemble as unsigned decimal (instead of hex): */
388 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
389
390 #define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))
391
392 static const char*
393 ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
394 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
395 {
396 return "internal error---this shouldn't happen";
397 }
398
399 static const char*
400 ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
401 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
402 {
403 return "internal error---this shouldn't happen";
404 }
405
406 static const char*
407 ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
408 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
409 {
410 return 0;
411 }
412
413 static const char*
414 ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
415 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
416 {
417 return 0;
418 }
419
420 static const char*
421 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
422 {
423 if (value >= 1u << self->field[0].bits)
424 return "register number out of range";
425
426 *code |= value << self->field[0].shift;
427 return 0;
428 }
429
430 static const char*
431 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
432 {
433 *valuep = ((code >> self->field[0].shift)
434 & ((1u << self->field[0].bits) - 1));
435 return 0;
436 }
437
438 static const char*
439 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
440 {
441 ia64_insn new = 0;
442 int i;
443
444 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
445 {
446 new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
447 << self->field[i].shift);
448 value >>= self->field[i].bits;
449 }
450 if (value)
451 return "integer operand out of range";
452
453 *code |= new;
454 return 0;
455 }
456
457 static const char*
458 ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
459 {
460 uint64_t value = 0;
461 int i, bits = 0, total = 0;
462
463 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
464 {
465 bits = self->field[i].bits;
466 value |= ((code >> self->field[i].shift)
467 & ((((uint64_t) 1) << bits) - 1)) << total;
468 total += bits;
469 }
470 *valuep = value;
471 return 0;
472 }
473
474 static const char*
475 ins_immu5b (const struct ia64_operand *self, ia64_insn value,
476 ia64_insn *code)
477 {
478 if (value < 32 || value > 63)
479 return "value must be between 32 and 63";
480 return ins_immu (self, value - 32, code);
481 }
482
483 static const char*
484 ext_immu5b (const struct ia64_operand *self, ia64_insn code,
485 ia64_insn *valuep)
486 {
487 const char *result;
488
489 result = ext_immu (self, code, valuep);
490 if (result)
491 return result;
492
493 *valuep = *valuep + 32;
494 return 0;
495 }
496
497 static const char*
498 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
499 {
500 if (value & 0x7)
501 return "value not an integer multiple of 8";
502 return ins_immu (self, value >> 3, code);
503 }
504
505 static const char*
506 ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
507 {
508 const char *result;
509
510 result = ext_immu (self, code, valuep);
511 if (result)
512 return result;
513
514 *valuep = *valuep << 3;
515 return 0;
516 }
517
518 static const char*
519 ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
520 ia64_insn *code, int scale)
521 {
522 int64_t svalue = value, sign_bit = 0;
523 ia64_insn new = 0;
524 int i;
525
526 svalue >>= scale;
527
528 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
529 {
530 new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
531 << self->field[i].shift);
532 sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
533 svalue >>= self->field[i].bits;
534 }
535 if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
536 return "integer operand out of range";
537
538 *code |= new;
539 return 0;
540 }
541
542 static const char*
543 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
544 ia64_insn *valuep, int scale)
545 {
546 int i, bits = 0, total = 0;
547 int64_t val = 0, sign;
548
549 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
550 {
551 bits = self->field[i].bits;
552 val |= ((code >> self->field[i].shift)
553 & ((((uint64_t) 1) << bits) - 1)) << total;
554 total += bits;
555 }
556 /* sign extend: */
557 sign = (int64_t) 1 << (total - 1);
558 val = (val ^ sign) - sign;
559
560 *valuep = (val << scale);
561 return 0;
562 }
563
564 static const char*
565 ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
566 {
567 return ins_imms_scaled (self, value, code, 0);
568 }
569
570 static const char*
571 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
572 {
573 value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
574
575 return ins_imms_scaled (self, value, code, 0);
576 }
577
578 static const char*
579 ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
580 {
581 return ext_imms_scaled (self, code, valuep, 0);
582 }
583
584 static const char*
585 ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
586 {
587 --value;
588 return ins_imms_scaled (self, value, code, 0);
589 }
590
591 static const char*
592 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
593 ia64_insn *code)
594 {
595 value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
596
597 --value;
598 return ins_imms_scaled (self, value, code, 0);
599 }
600
601 static const char*
602 ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
603 {
604 const char *res = ext_imms_scaled (self, code, valuep, 0);
605
606 ++*valuep;
607 return res;
608 }
609
610 static const char*
611 ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
612 {
613 return ins_imms_scaled (self, value, code, 1);
614 }
615
616 static const char*
617 ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
618 {
619 return ext_imms_scaled (self, code, valuep, 1);
620 }
621
622 static const char*
623 ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
624 {
625 return ins_imms_scaled (self, value, code, 4);
626 }
627
628 static const char*
629 ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
630 {
631 return ext_imms_scaled (self, code, valuep, 4);
632 }
633
634 static const char*
635 ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
636 {
637 return ins_imms_scaled (self, value, code, 16);
638 }
639
640 static const char*
641 ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
642 {
643 return ext_imms_scaled (self, code, valuep, 16);
644 }
645
646 static const char*
647 ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
648 {
649 ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
650 return ins_immu (self, value ^ mask, code);
651 }
652
653 static const char*
654 ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
655 {
656 const char *result;
657 ia64_insn mask;
658
659 mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
660 result = ext_immu (self, code, valuep);
661 if (!result)
662 {
663 mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
664 *valuep ^= mask;
665 }
666 return result;
667 }
668
669 static const char*
670 ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
671 {
672 --value;
673 if (value >= ((uint64_t) 1) << self->field[0].bits)
674 return "count out of range";
675
676 *code |= value << self->field[0].shift;
677 return 0;
678 }
679
680 static const char*
681 ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
682 {
683 *valuep = ((code >> self->field[0].shift)
684 & ((((uint64_t) 1) << self->field[0].bits) - 1)) + 1;
685 return 0;
686 }
687
688 static const char*
689 ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
690 {
691 --value;
692
693 if (value > 2)
694 return "count must be in range 1..3";
695
696 *code |= value << self->field[0].shift;
697 return 0;
698 }
699
700 static const char*
701 ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
702 {
703 *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
704 return 0;
705 }
706
707 static const char*
708 ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
709 {
710 switch (value)
711 {
712 case 0: value = 0; break;
713 case 7: value = 1; break;
714 case 15: value = 2; break;
715 case 16: value = 3; break;
716 default: return "count must be 0, 7, 15, or 16";
717 }
718 *code |= value << self->field[0].shift;
719 return 0;
720 }
721
722 static const char*
723 ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
724 {
725 ia64_insn value;
726
727 value = (code >> self->field[0].shift) & 0x3;
728 switch (value)
729 {
730 case 0: value = 0; break;
731 case 1: value = 7; break;
732 case 2: value = 15; break;
733 case 3: value = 16; break;
734 }
735 *valuep = value;
736 return 0;
737 }
738
739 static const char*
740 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
741 {
742 int64_t val = value;
743 uint64_t sign = 0;
744
745 if (val < 0)
746 {
747 sign = 0x4;
748 value = -value;
749 }
750 switch (value)
751 {
752 case 1: value = 3; break;
753 case 4: value = 2; break;
754 case 8: value = 1; break;
755 case 16: value = 0; break;
756 default: return "count must be +/- 1, 4, 8, or 16";
757 }
758 *code |= (sign | value) << self->field[0].shift;
759 return 0;
760 }
761
762 static const char*
763 ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
764 {
765 int64_t val;
766 int negate;
767
768 val = (code >> self->field[0].shift) & 0x7;
769 negate = val & 0x4;
770 switch (val & 0x3)
771 {
772 case 0: val = 16; break;
773 case 1: val = 8; break;
774 case 2: val = 4; break;
775 case 3: val = 1; break;
776 }
777 if (negate)
778 val = -val;
779
780 *valuep = val;
781 return 0;
782 }
783
784 /* glib.h defines ABS so we must undefine it to avoid a clash */
785 #undef ABS
786
787 #define CST IA64_OPND_CLASS_CST
788 #define REG IA64_OPND_CLASS_REG
789 #define IND IA64_OPND_CLASS_IND
790 #define ABS IA64_OPND_CLASS_ABS
791 #define REL IA64_OPND_CLASS_REL
792
793 #define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
794 #define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
795
796 const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
797 {
798 /* constants: */
799 { CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
800 { CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
801 { CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
802 { CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
803 { CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
804 { CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
805 { CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
806 { CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
807 { CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
808 { CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
809 { CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
810 { CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
811 { CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
812 { CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
813
814 /* register operands: */
815 { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
816 "an application register" },
817 { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
818 "a branch register" },
819 { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
820 "a branch register"},
821 { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
822 "a control register"},
823 { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
824 "a floating-point register" },
825 { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
826 "a floating-point register" },
827 { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
828 "a floating-point register" },
829 { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
830 "a floating-point register" },
831 { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
832 "a predicate register" },
833 { REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
834 "a predicate register" },
835 { REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
836 "a general register" },
837 { REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
838 "a general register" },
839 { REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
840 "a general register" },
841 { REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
842 "a general register r0-r3" },
843
844 /* memory operands: */
845 { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
846 "a memory address" },
847
848 /* indirect operands: */
849 { IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
850 "a cpuid register" },
851 { IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
852 "a dbr register" },
853 { IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
854 "a dtr register" },
855 { IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
856 "an itr register" },
857 { IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
858 "an ibr register" },
859 { IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
860 "an msr register" },
861 { IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
862 "a pkr register" },
863 { IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
864 "a pmc register" },
865 { IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
866 "a pmd register" },
867 { IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
868 "an rr register" },
869
870 /* immediate operands: */
871 { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
872 "a 5-bit count (0-31)" },
873 { ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
874 "a 2-bit count (1-4)" },
875 { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
876 "a 2-bit count (1-3)" },
877 { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
878 "a count (0, 7, 15, or 16)" },
879 { ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
880 "a 5-bit count (0-31)" },
881 { ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
882 "a 6-bit count (0-63)" },
883 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
884 "a 6-bit bit pos (0-63)" },
885 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
886 "a 6-bit bit pos (0-63)" },
887 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
888 "a 6-bit bit pos (0-63)" },
889 { ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
890 "a 1-bit integer (-1, 0)" },
891 { ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
892 "a 2-bit unsigned (0-3)" },
893 { ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */
894 "a 5-bit unsigned (32 + (0-31))" },
895 { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
896 "a 7-bit unsigned (0-127)" },
897 { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
898 "a 7-bit unsigned (0-127)" },
899 { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
900 "a frame size (register count)" },
901 { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
902 "a local register count" },
903 { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
904 "a rotating register count (integer multiple of 8)" },
905 { ABS, ins_imms, ext_imms, 0, /* IMM8 */
906 {{ 7, 13}, { 1, 36}}, SDEC,
907 "an 8-bit integer (-128-127)" },
908 { ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
909 {{ 7, 13}, { 1, 36}}, SDEC,
910 "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
911 { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
912 {{ 7, 13}, { 1, 36}}, SDEC,
913 "an 8-bit integer (-127-128)" },
914 { ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
915 {{ 7, 13}, { 1, 36}}, SDEC,
916 "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
917 { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
918 {{ 7, 13}, { 1, 36}}, SDEC,
919 "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
920 { ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
921 "a 9-bit unsigned (0-511)" },
922 { ABS, ins_imms, ext_imms, 0, /* IMM9a */
923 {{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
924 "a 9-bit integer (-256-255)" },
925 { ABS, ins_imms, ext_imms, 0, /* IMM9b */
926 {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
927 "a 9-bit integer (-256-255)" },
928 { ABS, ins_imms, ext_imms, 0, /* IMM14 */
929 {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
930 "a 14-bit integer (-8192-8191)" },
931 { ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
932 {{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
933 "a 17-bit integer (-65536-65535)" },
934 { ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
935 "a 21-bit unsigned" },
936 { ABS, ins_imms, ext_imms, 0, /* IMM22 */
937 {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
938 "a 22-bit signed integer" },
939 { ABS, ins_immu, ext_immu, 0, /* IMMU24 */
940 {{21, 6}, { 2, 31}, { 1, 36}}, 0,
941 "a 24-bit unsigned" },
942 { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
943 "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
944 { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
945 "a 62-bit unsigned" },
946 { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
947 "a 64-bit unsigned" },
948 { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
949 "an increment (+/- 1, 4, 8, or 16)" },
950 { ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
951 "a 4-bit length (1-16)" },
952 { ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
953 "a 6-bit length (1-64)" },
954 { ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
955 "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
956 { ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
957 "an 8-bit mix type" },
958 { ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
959 "a 6-bit bit pos (0-63)" },
960 { REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
961 "a branch tag" },
962 { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
963 "a branch tag" },
964 { REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
965 "a branch target" },
966 { REL, ins_imms4, ext_imms4, 0, /* TGT25b */
967 {{ 7, 6}, {13, 20}, { 1, 36}}, 0,
968 "a branch target" },
969 { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
970 "a branch target" },
971 { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
972 "a branch target" },
973
974 { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */
975 "ldxmov target" },
976 };
977
978
979 /* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
980 Copyright 1999, 2000 Free Software Foundation, Inc.
981 Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
982
983 This file is part of GDB, GAS, and the GNU binutils.
984
985 GDB, GAS, and the GNU binutils are free software; you can redistribute
986 them and/or modify them under the terms of the GNU General Public
987 License as published by the Free Software Foundation; either version
988 2, or (at your option) any later version.
989
990 GDB, GAS, and the GNU binutils are distributed in the hope that they
991 will be useful, but WITHOUT ANY WARRANTY; without even the implied
992 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
993 the GNU General Public License for more details.
994
995 You should have received a copy of the GNU General Public License
996 along with this file; see the file COPYING. If not, see
997 <http://www.gnu.org/licenses/>. */
998
999 /* The primary opcode table is made up of the following: */
1000 struct ia64_main_table
1001 {
1002 /* The entry in the string table that corresponds to the name of this
1003 opcode. */
1004 unsigned short name_index;
1005
1006 /* The type of opcode; corresponds to the TYPE field in
1007 struct ia64_opcode. */
1008 unsigned char opcode_type;
1009
1010 /* The number of outputs for this opcode. */
1011 unsigned char num_outputs;
1012
1013 /* The base insn value for this opcode. It may be modified by completers. */
1014 ia64_insn opcode;
1015
1016 /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
1017 ia64_insn mask;
1018
1019 /* The operands of this instruction. Corresponds to the OPERANDS field
1020 in struct ia64_opcode. */
1021 unsigned char operands[5];
1022
1023 /* The flags for this instruction. Corresponds to the FLAGS field in
1024 struct ia64_opcode. */
1025 short flags;
1026
1027 /* The tree of completers for this instruction; this is an offset into
1028 completer_table. */
1029 short completers;
1030 };
1031
1032 /* Each instruction has a set of possible "completers", or additional
1033 suffixes that can alter the instruction's behavior, and which has
1034 potentially different dependencies.
1035
1036 The completer entries modify certain bits in the instruction opcode.
1037 Which bits are to be modified are marked by the BITS, MASK and
1038 OFFSET fields. The completer entry may also note dependencies for the
1039 opcode.
1040
1041 These completers are arranged in a DAG; the pointers are indexes
1042 into the completer_table array. The completer DAG is searched by
1043 find_completer () and ia64_find_matching_opcode ().
1044
1045 Note that each completer needs to be applied in turn, so that if we
1046 have the instruction
1047 cmp.lt.unc
1048 the completer entries for both "lt" and "unc" would need to be applied
1049 to the opcode's value.
1050
1051 Some instructions do not require any completers; these contain an
1052 empty completer entry. Instructions that require a completer do
1053 not contain an empty entry.
1054
1055 Terminal completers (those completers that validly complete an
1056 instruction) are marked by having the TERMINAL_COMPLETER flag set.
1057
1058 Only dependencies listed in the terminal completer for an opcode are
1059 considered to apply to that opcode instance. */
1060
1061 struct ia64_completer_table
1062 {
1063 /* The bit value that this completer sets. */
1064 unsigned int bits;
1065
1066 /* And its mask. 1s are bits that are to be modified in the
1067 instruction. */
1068 unsigned int mask;
1069
1070 /* The entry in the string table that corresponds to the name of this
1071 completer. */
1072 unsigned short name_index;
1073
1074 /* An alternative completer, or -1 if this is the end of the chain. */
1075 short alternative;
1076
1077 /* A pointer to the DAG of completers that can potentially follow
1078 this one, or -1. */
1079 short subentries;
1080
1081 /* The bit offset in the instruction where BITS and MASK should be
1082 applied. */
1083 unsigned char offset : 7;
1084
1085 unsigned char terminal_completer : 1;
1086
1087 /* Index into the dependency list table */
1088 short dependencies;
1089 };
1090
1091 /* This contains sufficient information for the disassembler to resolve
1092 the complete name of the original instruction. */
1093 struct ia64_dis_names
1094 {
1095 /* COMPLETER_INDEX represents the tree of completers that make up
1096 the instruction. The LSB represents the top of the tree for the
1097 specified instruction.
1098
1099 A 0 bit indicates to go to the next alternate completer via the
1100 alternative field; a 1 bit indicates that the current completer
1101 is part of the instruction, and to go down the subentries index.
1102 We know we've reached the final completer when we run out of 1
1103 bits.
1104
1105 There is always at least one 1 bit. */
1106 unsigned int completer_index : 20;
1107
1108 /* The index in the main_table[] array for the instruction. */
1109 unsigned short insn_index : 11;
1110
1111 /* If set, the next entry in this table is an alternate possibility
1112 for this instruction encoding. Which one to use is determined by
1113 the instruction type and other factors (see opcode_verify ()). */
1114 unsigned int next_flag : 1;
1115
1116 /* The disassembly priority of this entry among instructions. */
1117 unsigned short priority;
1118 };
1119
1120 static const char * const ia64_strings[] = {
1121 "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",
1122 "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",
1123 "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16",
1124 "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop",
1125 "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl",
1126 "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand",
1127 "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt",
1128 "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax",
1129 "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma",
1130 "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp",
1131 "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg",
1132 "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta",
1133 "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu",
1134 "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia",
1135 "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8",
1136 "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le",
1137 "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many",
1138 "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne",
1139 "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1",
1140 "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1",
1141 "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1",
1142 "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2",
1143 "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2",
1144 "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz",
1145 "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3",
1146 "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig",
1147 "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2",
1148 "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1",
1149 "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa",
1150 "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4",
1151 "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2",
1152 "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2",
1153 "zxt4",
1154 };
1155
1156 static const struct ia64_dependency
1157 dependencies[] = {
1158 { "ALAT", 0, 0, 0, -1, NULL, },
1159 { "AR[BSP]", 26, 0, 2, 17, NULL, },
1160 { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, },
1161 { "AR[CCV]", 26, 0, 2, 32, NULL, },
1162 { "AR[CFLG]", 26, 0, 2, 27, NULL, },
1163 { "AR[CSD]", 26, 0, 2, 25, NULL, },
1164 { "AR[EC]", 26, 0, 2, 66, NULL, },
1165 { "AR[EFLAG]", 26, 0, 2, 24, NULL, },
1166 { "AR[FCR]", 26, 0, 2, 21, NULL, },
1167 { "AR[FDR]", 26, 0, 2, 30, NULL, },
1168 { "AR[FIR]", 26, 0, 2, 29, NULL, },
1169 { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, },
1170 { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, },
1171 { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, },
1172 { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, },
1173 { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, },
1174 { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, },
1175 { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, },
1176 { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, },
1177 { "AR[FPSR].traps", 30, 0, 2, -1, NULL, },
1178 { "AR[FPSR].rv", 30, 0, 2, -1, NULL, },
1179 { "AR[FSR]", 26, 0, 2, 28, NULL, },
1180 { "AR[ITC]", 26, 0, 2, 44, NULL, },
1181 { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, },
1182 { "AR[LC]", 26, 0, 2, 65, NULL, },
1183 { "AR[PFS]", 26, 0, 2, 64, NULL, },
1184 { "AR[PFS]", 26, 0, 2, 64, NULL, },
1185 { "AR[PFS]", 26, 0, 0, 64, NULL, },
1186 { "AR[RNAT]", 26, 0, 2, 19, NULL, },
1187 { "AR[RSC]", 26, 0, 2, 16, NULL, },
1188 { "AR[SSD]", 26, 0, 2, 26, NULL, },
1189 { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, },
1190 { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, },
1191 { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, },
1192 { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
1193 { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, },
1194 { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
1195 { "CFM", 6, 0, 2, -1, NULL, },
1196 { "CFM", 6, 0, 2, -1, NULL, },
1197 { "CFM", 6, 0, 2, -1, NULL, },
1198 { "CFM", 6, 0, 2, -1, NULL, },
1199 { "CFM", 6, 0, 0, -1, NULL, },
1200 { "CPUID#", 7, 0, 5, -1, NULL, },
1201 { "CR[CMCV]", 27, 0, 3, 74, NULL, },
1202 { "CR[DCR]", 27, 0, 3, 0, NULL, },
1203 { "CR[EOI]", 27, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", },
1204 { "CR[GPTA]", 27, 0, 3, 9, NULL, },
1205 { "CR[IFA]", 27, 0, 1, 20, NULL, },
1206 { "CR[IFA]", 27, 0, 3, 20, NULL, },
1207 { "CR[IFS]", 27, 0, 3, 23, NULL, },
1208 { "CR[IFS]", 27, 0, 1, 23, NULL, },
1209 { "CR[IFS]", 27, 0, 1, 23, NULL, },
1210 { "CR[IHA]", 27, 0, 3, 25, NULL, },
1211 { "CR[IIM]", 27, 0, 3, 24, NULL, },
1212 { "CR[IIP]", 27, 0, 3, 19, NULL, },
1213 { "CR[IIP]", 27, 0, 1, 19, NULL, },
1214 { "CR[IIPA]", 27, 0, 3, 22, NULL, },
1215 { "CR[IPSR]", 27, 0, 3, 16, NULL, },
1216 { "CR[IPSR]", 27, 0, 1, 16, NULL, },
1217 { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, },
1218 { "CR[ISR]", 27, 0, 3, 17, NULL, },
1219 { "CR[ITIR]", 27, 0, 3, 21, NULL, },
1220 { "CR[ITIR]", 27, 0, 1, 21, NULL, },
1221 { "CR[ITM]", 27, 0, 3, 1, NULL, },
1222 { "CR[ITV]", 27, 0, 3, 72, NULL, },
1223 { "CR[IVA]", 27, 0, 4, 2, NULL, },
1224 { "CR[IVR]", 27, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vector Register (IVR Ð CR65)\" on page 2:118", },
1225 { "CR[LID]", 27, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID Ð CR64)\" on page 2:117", },
1226 { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, },
1227 { "CR[PMV]", 27, 0, 3, 73, NULL, },
1228 { "CR[PTA]", 27, 0, 3, 8, NULL, },
1229 { "CR[TPR]", 27, 0, 3, 66, NULL, },
1230 { "CR[TPR]", 27, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register (TPR Ð CR66)\" on page 2:119", },
1231 { "CR[TPR]", 27, 0, 1, 66, NULL, },
1232 { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, },
1233 { "DBR#", 11, 0, 2, -1, NULL, },
1234 { "DBR#", 11, 0, 3, -1, NULL, },
1235 { "DTC", 0, 0, 3, -1, NULL, },
1236 { "DTC", 0, 0, 2, -1, NULL, },
1237 { "DTC", 0, 0, 0, -1, NULL, },
1238 { "DTC", 0, 0, 2, -1, NULL, },
1239 { "DTC_LIMIT*", 0, 0, 2, -1, NULL, },
1240 { "DTR", 0, 0, 3, -1, NULL, },
1241 { "DTR", 0, 0, 2, -1, NULL, },
1242 { "DTR", 0, 0, 3, -1, NULL, },
1243 { "DTR", 0, 0, 0, -1, NULL, },
1244 { "DTR", 0, 0, 2, -1, NULL, },
1245 { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, },
1246 { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, },
1247 { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, },
1248 { "GR0", 14, 0, 0, -1, NULL, },
1249 { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, },
1250 { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, },
1251 { "IBR#", 16, 0, 2, -1, NULL, },
1252 { "InService*", 17, 0, 3, -1, NULL, },
1253 { "InService*", 17, 0, 2, -1, NULL, },
1254 { "InService*", 17, 0, 2, -1, NULL, },
1255 { "IP", 0, 0, 0, -1, NULL, },
1256 { "ITC", 0, 0, 4, -1, NULL, },
1257 { "ITC", 0, 0, 2, -1, NULL, },
1258 { "ITC", 0, 0, 0, -1, NULL, },
1259 { "ITC", 0, 0, 4, -1, NULL, },
1260 { "ITC", 0, 0, 2, -1, NULL, },
1261 { "ITC_LIMIT*", 0, 0, 2, -1, NULL, },
1262 { "ITR", 0, 0, 2, -1, NULL, },
1263 { "ITR", 0, 0, 4, -1, NULL, },
1264 { "ITR", 0, 0, 2, -1, NULL, },
1265 { "ITR", 0, 0, 0, -1, NULL, },
1266 { "ITR", 0, 0, 4, -1, NULL, },
1267 { "memory", 0, 0, 0, -1, NULL, },
1268 { "MSR#", 18, 0, 5, -1, NULL, },
1269 { "PKR#", 19, 0, 3, -1, NULL, },
1270 { "PKR#", 19, 0, 0, -1, NULL, },
1271 { "PKR#", 19, 0, 2, -1, NULL, },
1272 { "PKR#", 19, 0, 2, -1, NULL, },
1273 { "PMC#", 20, 0, 2, -1, NULL, },
1274 { "PMC#", 20, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter Registers\" for PMC[0].fr on page 2:150", },
1275 { "PMD#", 21, 0, 2, -1, NULL, },
1276 { "PR0", 0, 0, 0, -1, NULL, },
1277 { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
1278 { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
1279 { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, },
1280 { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
1281 { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
1282 { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, },
1283 { "PR63", 24, 0, 2, -1, NULL, },
1284 { "PR63", 24, 0, 2, -1, NULL, },
1285 { "PR63", 24, 0, 0, -1, NULL, },
1286 { "PSR.ac", 28, 0, 1, 3, NULL, },
1287 { "PSR.ac", 28, 0, 3, 3, NULL, },
1288 { "PSR.ac", 28, 0, 2, 3, NULL, },
1289 { "PSR.ac", 28, 0, 2, 3, NULL, },
1290 { "PSR.be", 28, 0, 1, 1, NULL, },
1291 { "PSR.be", 28, 0, 3, 1, NULL, },
1292 { "PSR.be", 28, 0, 2, 1, NULL, },
1293 { "PSR.be", 28, 0, 2, 1, NULL, },
1294 { "PSR.bn", 28, 0, 2, 44, NULL, },
1295 { "PSR.cpl", 28, 0, 1, 32, NULL, },
1296 { "PSR.cpl", 28, 0, 2, 32, NULL, },
1297 { "PSR.da", 28, 0, 2, 38, NULL, },
1298 { "PSR.db", 28, 0, 3, 24, NULL, },
1299 { "PSR.db", 28, 0, 2, 24, NULL, },
1300 { "PSR.db", 28, 0, 2, 24, NULL, },
1301 { "PSR.dd", 28, 0, 2, 39, NULL, },
1302 { "PSR.dfh", 28, 0, 3, 19, NULL, },
1303 { "PSR.dfh", 28, 0, 2, 19, NULL, },
1304 { "PSR.dfh", 28, 0, 2, 19, NULL, },
1305 { "PSR.dfl", 28, 0, 3, 18, NULL, },
1306 { "PSR.dfl", 28, 0, 2, 18, NULL, },
1307 { "PSR.dfl", 28, 0, 2, 18, NULL, },
1308 { "PSR.di", 28, 0, 3, 22, NULL, },
1309 { "PSR.di", 28, 0, 2, 22, NULL, },
1310 { "PSR.di", 28, 0, 2, 22, NULL, },
1311 { "PSR.dt", 28, 0, 3, 17, NULL, },
1312 { "PSR.dt", 28, 0, 2, 17, NULL, },
1313 { "PSR.dt", 28, 0, 2, 17, NULL, },
1314 { "PSR.ed", 28, 0, 2, 43, NULL, },
1315 { "PSR.i", 28, 0, 2, 14, NULL, },
1316 { "PSR.ia", 28, 0, 0, 14, NULL, },
1317 { "PSR.ic", 28, 0, 2, 13, NULL, },
1318 { "PSR.ic", 28, 0, 3, 13, NULL, },
1319 { "PSR.ic", 28, 0, 2, 13, NULL, },
1320 { "PSR.id", 28, 0, 0, 14, NULL, },
1321 { "PSR.is", 28, 0, 0, 14, NULL, },
1322 { "PSR.it", 28, 0, 2, 14, NULL, },
1323 { "PSR.lp", 28, 0, 2, 25, NULL, },
1324 { "PSR.lp", 28, 0, 3, 25, NULL, },
1325 { "PSR.lp", 28, 0, 2, 25, NULL, },
1326 { "PSR.mc", 28, 0, 2, 35, NULL, },
1327 { "PSR.mfh", 28, 0, 2, 5, NULL, },
1328 { "PSR.mfl", 28, 0, 2, 4, NULL, },
1329 { "PSR.pk", 28, 0, 3, 15, NULL, },
1330 { "PSR.pk", 28, 0, 2, 15, NULL, },
1331 { "PSR.pk", 28, 0, 2, 15, NULL, },
1332 { "PSR.pp", 28, 0, 2, 21, NULL, },
1333 { "PSR.ri", 28, 0, 0, 41, NULL, },
1334 { "PSR.rt", 28, 0, 2, 27, NULL, },
1335 { "PSR.rt", 28, 0, 3, 27, NULL, },
1336 { "PSR.rt", 28, 0, 2, 27, NULL, },
1337 { "PSR.si", 28, 0, 2, 23, NULL, },
1338 { "PSR.si", 28, 0, 3, 23, NULL, },
1339 { "PSR.si", 28, 0, 2, 23, NULL, },
1340 { "PSR.sp", 28, 0, 2, 20, NULL, },
1341 { "PSR.sp", 28, 0, 3, 20, NULL, },
1342 { "PSR.sp", 28, 0, 2, 20, NULL, },
1343 { "PSR.ss", 28, 0, 2, 40, NULL, },
1344 { "PSR.tb", 28, 0, 3, 26, NULL, },
1345 { "PSR.tb", 28, 0, 2, 26, NULL, },
1346 { "PSR.tb", 28, 0, 2, 26, NULL, },
1347 { "PSR.up", 28, 0, 2, 2, NULL, },
1348 { "PSR.vm", 28, 0, 1, 46, NULL, },
1349 { "PSR.vm", 28, 0, 2, 46, NULL, },
1350 { "RR#", 25, 0, 3, -1, NULL, },
1351 { "RR#", 25, 0, 2, -1, NULL, },
1352 { "RSE", 29, 0, 2, -1, NULL, },
1353 { "ALAT", 0, 1, 0, -1, NULL, },
1354 { "AR[BSP]", 26, 1, 2, 17, NULL, },
1355 { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, },
1356 { "AR[CCV]", 26, 1, 2, 32, NULL, },
1357 { "AR[CFLG]", 26, 1, 2, 27, NULL, },
1358 { "AR[CSD]", 26, 1, 2, 25, NULL, },
1359 { "AR[EC]", 26, 1, 2, 66, NULL, },
1360 { "AR[EFLAG]", 26, 1, 2, 24, NULL, },
1361 { "AR[FCR]", 26, 1, 2, 21, NULL, },
1362 { "AR[FDR]", 26, 1, 2, 30, NULL, },
1363 { "AR[FIR]", 26, 1, 2, 29, NULL, },
1364 { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, },
1365 { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, },
1366 { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, },
1367 { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, },
1368 { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, },
1369 { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
1370 { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
1371 { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, },
1372 { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
1373 { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
1374 { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, },
1375 { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
1376 { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
1377 { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, },
1378 { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
1379 { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
1380 { "AR[FPSR].rv", 30, 1, 2, -1, NULL, },
1381 { "AR[FPSR].traps", 30, 1, 2, -1, NULL, },
1382 { "AR[FSR]", 26, 1, 2, 28, NULL, },
1383 { "AR[ITC]", 26, 1, 2, 44, NULL, },
1384 { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, },
1385 { "AR[LC]", 26, 1, 2, 65, NULL, },
1386 { "AR[PFS]", 26, 1, 0, 64, NULL, },
1387 { "AR[PFS]", 26, 1, 2, 64, NULL, },
1388 { "AR[PFS]", 26, 1, 2, 64, NULL, },
1389 { "AR[RNAT]", 26, 1, 2, 19, NULL, },
1390 { "AR[RSC]", 26, 1, 2, 16, NULL, },
1391 { "AR[SSD]", 26, 1, 2, 26, NULL, },
1392 { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, },
1393 { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, },
1394 { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, },
1395 { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
1396 { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
1397 { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
1398 { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, },
1399 { "CFM", 6, 1, 2, -1, NULL, },
1400 { "CPUID#", 7, 1, 0, -1, NULL, },
1401 { "CR[CMCV]", 27, 1, 2, 74, NULL, },
1402 { "CR[DCR]", 27, 1, 2, 0, NULL, },
1403 { "CR[EOI]", 27, 1, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", },
1404 { "CR[GPTA]", 27, 1, 2, 9, NULL, },
1405 { "CR[IFA]", 27, 1, 2, 20, NULL, },
1406 { "CR[IFS]", 27, 1, 2, 23, NULL, },
1407 { "CR[IHA]", 27, 1, 2, 25, NULL, },
1408 { "CR[IIM]", 27, 1, 2, 24, NULL, },
1409 { "CR[IIP]", 27, 1, 2, 19, NULL, },
1410 { "CR[IIPA]", 27, 1, 2, 22, NULL, },
1411 { "CR[IPSR]", 27, 1, 2, 16, NULL, },
1412 { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, },
1413 { "CR[ISR]", 27, 1, 2, 17, NULL, },
1414 { "CR[ITIR]", 27, 1, 2, 21, NULL, },
1415 { "CR[ITM]", 27, 1, 2, 1, NULL, },
1416 { "CR[ITV]", 27, 1, 2, 72, NULL, },
1417 { "CR[IVA]", 27, 1, 2, 2, NULL, },
1418 { "CR[IVR]", 27, 1, 7, 65, "SC", },
1419 { "CR[LID]", 27, 1, 7, 64, "SC", },
1420 { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, },
1421 { "CR[PMV]", 27, 1, 2, 73, NULL, },
1422 { "CR[PTA]", 27, 1, 2, 8, NULL, },
1423 { "CR[TPR]", 27, 1, 2, 66, NULL, },
1424 { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, },
1425 { "DBR#", 11, 1, 2, -1, NULL, },
1426 { "DTC", 0, 1, 0, -1, NULL, },
1427 { "DTC", 0, 1, 2, -1, NULL, },
1428 { "DTC", 0, 1, 2, -1, NULL, },
1429 { "DTC_LIMIT*", 0, 1, 2, -1, NULL, },
1430 { "DTR", 0, 1, 2, -1, NULL, },
1431 { "DTR", 0, 1, 2, -1, NULL, },
1432 { "DTR", 0, 1, 2, -1, NULL, },
1433 { "DTR", 0, 1, 0, -1, NULL, },
1434 { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, },
1435 { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, },
1436 { "GR0", 14, 1, 0, -1, NULL, },
1437 { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, },
1438 { "IBR#", 16, 1, 2, -1, NULL, },
1439 { "InService*", 17, 1, 7, -1, "SC", },
1440 { "IP", 0, 1, 0, -1, NULL, },
1441 { "ITC", 0, 1, 0, -1, NULL, },
1442 { "ITC", 0, 1, 2, -1, NULL, },
1443 { "ITC", 0, 1, 2, -1, NULL, },
1444 { "ITR", 0, 1, 2, -1, NULL, },
1445 { "ITR", 0, 1, 2, -1, NULL, },
1446 { "ITR", 0, 1, 0, -1, NULL, },
1447 { "memory", 0, 1, 0, -1, NULL, },
1448 { "MSR#", 18, 1, 7, -1, "SC", },
1449 { "PKR#", 19, 1, 0, -1, NULL, },
1450 { "PKR#", 19, 1, 0, -1, NULL, },
1451 { "PKR#", 19, 1, 2, -1, NULL, },
1452 { "PMC#", 20, 1, 2, -1, NULL, },
1453 { "PMD#", 21, 1, 2, -1, NULL, },
1454 { "PR0", 0, 1, 0, -1, NULL, },
1455 { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
1456 { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
1457 { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
1458 { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
1459 { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
1460 { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
1461 { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
1462 { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
1463 { "PR63", 24, 1, 0, -1, NULL, },
1464 { "PR63", 24, 1, 0, -1, NULL, },
1465 { "PR63", 24, 1, 2, -1, NULL, },
1466 { "PR63", 24, 1, 2, -1, NULL, },
1467 { "PSR.ac", 28, 1, 2, 3, NULL, },
1468 { "PSR.be", 28, 1, 2, 1, NULL, },
1469 { "PSR.bn", 28, 1, 2, 44, NULL, },
1470 { "PSR.cpl", 28, 1, 2, 32, NULL, },
1471 { "PSR.da", 28, 1, 2, 38, NULL, },
1472 { "PSR.db", 28, 1, 2, 24, NULL, },
1473 { "PSR.dd", 28, 1, 2, 39, NULL, },
1474 { "PSR.dfh", 28, 1, 2, 19, NULL, },
1475 { "PSR.dfl", 28, 1, 2, 18, NULL, },
1476 { "PSR.di", 28, 1, 2, 22, NULL, },
1477 { "PSR.dt", 28, 1, 2, 17, NULL, },
1478 { "PSR.ed", 28, 1, 2, 43, NULL, },
1479 { "PSR.i", 28, 1, 2, 14, NULL, },
1480 { "PSR.ia", 28, 1, 2, 14, NULL, },
1481 { "PSR.ic", 28, 1, 2, 13, NULL, },
1482 { "PSR.id", 28, 1, 2, 14, NULL, },
1483 { "PSR.is", 28, 1, 2, 14, NULL, },
1484 { "PSR.it", 28, 1, 2, 14, NULL, },
1485 { "PSR.lp", 28, 1, 2, 25, NULL, },
1486 { "PSR.mc", 28, 1, 2, 35, NULL, },
1487 { "PSR.mfh", 28, 1, 0, 5, NULL, },
1488 { "PSR.mfh", 28, 1, 2, 5, NULL, },
1489 { "PSR.mfh", 28, 1, 2, 5, NULL, },
1490 { "PSR.mfl", 28, 1, 0, 4, NULL, },
1491 { "PSR.mfl", 28, 1, 2, 4, NULL, },
1492 { "PSR.mfl", 28, 1, 2, 4, NULL, },
1493 { "PSR.pk", 28, 1, 2, 15, NULL, },
1494 { "PSR.pp", 28, 1, 2, 21, NULL, },
1495 { "PSR.ri", 28, 1, 2, 41, NULL, },
1496 { "PSR.rt", 28, 1, 2, 27, NULL, },
1497 { "PSR.si", 28, 1, 2, 23, NULL, },
1498 { "PSR.sp", 28, 1, 2, 20, NULL, },
1499 { "PSR.ss", 28, 1, 2, 40, NULL, },
1500 { "PSR.tb", 28, 1, 2, 26, NULL, },
1501 { "PSR.up", 28, 1, 2, 2, NULL, },
1502 { "PSR.vm", 28, 1, 2, 46, NULL, },
1503 { "RR#", 25, 1, 2, -1, NULL, },
1504 { "RSE", 29, 1, 2, -1, NULL, },
1505 { "PR63", 24, 2, 6, -1, NULL, },
1506 };
1507
1508 static const unsigned short dep0[] = {
1509 97, 282, 2140, 2327,
1510 };
1511
1512 static const unsigned short dep1[] = {
1513 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1514 2327, 4135, 20616,
1515 };
1516
1517 static const unsigned short dep2[] = {
1518 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2347, 2348, 2351,
1519 2352, 2355, 2356,
1520 };
1521
1522 static const unsigned short dep3[] = {
1523 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1524 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 20616,
1525 };
1526
1527 static const unsigned short dep4[] = {
1528 97, 282, 22646, 22647, 22649, 22650, 22652, 22653, 22655, 22824, 22827, 22828,
1529 22831, 22832, 22835, 22836,
1530 };
1531
1532 static const unsigned short dep5[] = {
1533 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1534 4135, 20616, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1535 };
1536
1537 static const unsigned short dep6[] = {
1538 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2347, 2349,
1539 2351, 2353, 2355,
1540 };
1541
1542 static const unsigned short dep7[] = {
1543 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1544 2344, 2345, 2348, 2349, 2352, 2353, 2356, 4135, 20616,
1545 };
1546
1547 static const unsigned short dep8[] = {
1548 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2346, 2348, 2350,
1549 2352, 2354, 2356,
1550 };
1551
1552 static const unsigned short dep9[] = {
1553 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1554 2344, 2346, 2347, 2350, 2351, 2354, 2355, 4135, 20616,
1555 };
1556
1557 static const unsigned short dep10[] = {
1558 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2346, 2347,
1559 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356,
1560 };
1561
1562 static const unsigned short dep11[] = {
1563 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1564 2344, 2345, 2346, 2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356,
1565 4135, 20616,
1566 };
1567
1568 static const unsigned short dep12[] = {
1569 97, 282, 2395,
1570 };
1571
1572 static const unsigned short dep13[] = {
1573 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2082, 2083, 2166, 2168,
1574 2169, 2171, 2172, 2174, 2175, 4135,
1575 };
1576
1577 static const unsigned short dep14[] = {
1578 97, 163, 282, 325, 2395, 28866, 29018,
1579 };
1580
1581 static const unsigned short dep15[] = {
1582 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
1583 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 40, 41, 97, 150, 152, 158, 162,
1584 164, 175, 185, 186, 188, 282, 325, 2082, 2083, 2166, 2168, 2169, 2171, 2172,
1585 2174, 2175, 4135, 28866, 29018,
1586 };
1587
1588 static const unsigned short dep16[] = {
1589 1, 6, 40, 97, 137, 196, 201, 241, 282, 312, 2395, 28866, 29018,
1590 };
1591
1592 static const unsigned short dep17[] = {
1593 1, 25, 27, 38, 40, 41, 97, 158, 162, 164, 166, 167, 175, 185, 186, 188, 196,
1594 201, 241, 282, 312, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175,
1595 4135, 28866, 29018,
1596 };
1597
1598 static const unsigned short dep18[] = {
1599 1, 40, 51, 97, 196, 241, 248, 282, 28866, 29018,
1600 };
1601
1602 static const unsigned short dep19[] = {
1603 1, 38, 40, 41, 97, 158, 160, 161, 162, 175, 185, 190, 191, 196, 241, 248,
1604 282, 4135, 28866, 29018,
1605 };
1606
1607 static const unsigned short dep20[] = {
1608 40, 97, 241, 282,
1609 };
1610
1611 static const unsigned short dep21[] = {
1612 97, 158, 162, 175, 185, 241, 282,
1613 };
1614
1615 static const unsigned short dep22[] = {
1616 1, 40, 97, 131, 135, 136, 138, 139, 142, 143, 146, 149, 152, 155, 156, 157,
1617 158, 161, 162, 163, 164, 167, 168, 169, 170, 173, 174, 175, 178, 181, 184,
1618 185, 188, 189, 191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316,
1619 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333,
1620 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 28866, 29018,
1621 };
1622
1623 static const unsigned short dep23[] = {
1624 1, 38, 40, 41, 50, 51, 55, 58, 73, 97, 137, 138, 158, 162, 175, 185, 190,
1625 191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319,
1626 320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333, 334, 335, 336,
1627 337, 338, 339, 340, 341, 342, 343, 344, 4135, 28866, 29018,
1628 };
1629
1630 static const unsigned short dep24[] = {
1631 97, 136, 282, 311,
1632 };
1633
1634 static const unsigned short dep25[] = {
1635 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 311,
1636 };
1637
1638 static const unsigned short dep26[] = {
1639 97, 137, 282, 312,
1640 };
1641
1642 static const unsigned short dep27[] = {
1643 25, 26, 97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 312,
1644
1645 };
1646
1647 static const unsigned short dep28[] = {
1648 97, 190, 282, 344,
1649 };
1650
1651 static const unsigned short dep29[] = {
1652 97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 344,
1653 };
1654
1655 static const unsigned short dep30[] = {
1656 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175,
1657 4135,
1658 };
1659
1660 static const unsigned short dep31[] = {
1661 1, 25, 40, 97, 196, 228, 229, 241, 282, 2082, 2285, 2288, 2395, 28866, 29018,
1662
1663 };
1664
1665 static const unsigned short dep32[] = {
1666 1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228,
1667 230, 241, 282, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286,
1668 2288, 4135, 28866, 29018,
1669 };
1670
1671 static const unsigned short dep33[] = {
1672 97, 282,
1673 };
1674
1675 static const unsigned short dep34[] = {
1676 97, 158, 162, 175, 185, 282, 2082, 2084,
1677 };
1678
1679 static const unsigned short dep35[] = {
1680 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2168, 2169, 2171,
1681 2172, 2174, 2175, 4135,
1682 };
1683
1684 static const unsigned short dep36[] = {
1685 6, 37, 38, 39, 97, 125, 126, 201, 241, 282, 307, 308, 2395,
1686 };
1687
1688 static const unsigned short dep37[] = {
1689 6, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 241, 282, 307,
1690 308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135,
1691 };
1692
1693 static const unsigned short dep38[] = {
1694 24, 97, 227, 282, 2395,
1695 };
1696
1697 static const unsigned short dep39[] = {
1698 24, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 227, 282, 2166, 2168, 2169,
1699 2171, 2172, 2174, 2175, 4135,
1700 };
1701
1702 static const unsigned short dep40[] = {
1703 6, 24, 37, 38, 39, 97, 125, 126, 201, 227, 241, 282, 307, 308, 2395,
1704 };
1705
1706 static const unsigned short dep41[] = {
1707 6, 24, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 227, 241, 282,
1708 307, 308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135,
1709 };
1710
1711 static const unsigned short dep42[] = {
1712 1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228,
1713 230, 241, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286, 2288, 4135,
1714 28866, 29018,
1715 };
1716
1717 static const unsigned short dep43[] = {
1718 97, 158, 162, 175, 185, 282,
1719 };
1720
1721 static const unsigned short dep44[] = {
1722 15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1723 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1724 22832, 22835, 22836,
1725 };
1726
1727 static const unsigned short dep45[] = {
1728 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
1729 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1730 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1731 };
1732
1733 static const unsigned short dep46[] = {
1734 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325,
1735 18601, 18602, 18761, 18762, 18764, 18765, 22646, 22647, 22648, 22650, 22651,
1736 22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1737 };
1738
1739 static const unsigned short dep47[] = {
1740 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
1741 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135,
1742 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 22824, 22827, 22828,
1743 22831, 22832, 22835, 22836,
1744 };
1745
1746 static const unsigned short dep48[] = {
1747 16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1748 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1749 22832, 22835, 22836,
1750 };
1751
1752 static const unsigned short dep49[] = {
1753 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
1754 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1755 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1756 };
1757
1758 static const unsigned short dep50[] = {
1759 17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1760 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1761 22832, 22835, 22836,
1762 };
1763
1764 static const unsigned short dep51[] = {
1765 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
1766 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1767 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1768 };
1769
1770 static const unsigned short dep52[] = {
1771 18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1772 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1773 22832, 22835, 22836,
1774 };
1775
1776 static const unsigned short dep53[] = {
1777 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
1778 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1779 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1780 };
1781
1782 static const unsigned short dep54[] = {
1783 15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1784
1785 };
1786
1787 static const unsigned short dep55[] = {
1788 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
1789 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1790 18764, 18766,
1791 };
1792
1793 static const unsigned short dep56[] = {
1794 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325,
1795 18601, 18602, 18761, 18762, 18764, 18765,
1796 };
1797
1798 static const unsigned short dep57[] = {
1799 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
1800 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135,
1801 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766,
1802 };
1803
1804 static const unsigned short dep58[] = {
1805 16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1806
1807 };
1808
1809 static const unsigned short dep59[] = {
1810 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
1811 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1812 18764, 18766,
1813 };
1814
1815 static const unsigned short dep60[] = {
1816 17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1817
1818 };
1819
1820 static const unsigned short dep61[] = {
1821 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
1822 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1823 18764, 18766,
1824 };
1825
1826 static const unsigned short dep62[] = {
1827 18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1828
1829 };
1830
1831 static const unsigned short dep63[] = {
1832 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
1833 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1834 18764, 18766,
1835 };
1836
1837 static const unsigned short dep64[] = {
1838 97, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1839 };
1840
1841 static const unsigned short dep65[] = {
1842 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173,
1843 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766,
1844 };
1845
1846 static const unsigned short dep66[] = {
1847 11, 97, 206, 282,
1848 };
1849
1850 static const unsigned short dep67[] = {
1851 11, 40, 41, 97, 158, 162, 175, 185, 206, 282, 2166, 2167, 2170, 2173, 4135,
1852
1853 };
1854
1855 static const unsigned short dep68[] = {
1856 11, 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135,
1857 };
1858
1859 static const unsigned short dep69[] = {
1860 12, 97, 207, 282,
1861 };
1862
1863 static const unsigned short dep70[] = {
1864 11, 40, 41, 97, 158, 162, 175, 185, 207, 282, 2166, 2167, 2170, 2173, 4135,
1865
1866 };
1867
1868 static const unsigned short dep71[] = {
1869 13, 97, 208, 282,
1870 };
1871
1872 static const unsigned short dep72[] = {
1873 11, 40, 41, 97, 158, 162, 175, 185, 208, 282, 2166, 2167, 2170, 2173, 4135,
1874
1875 };
1876
1877 static const unsigned short dep73[] = {
1878 14, 97, 209, 282,
1879 };
1880
1881 static const unsigned short dep74[] = {
1882 11, 40, 41, 97, 158, 162, 175, 185, 209, 282, 2166, 2167, 2170, 2173, 4135,
1883
1884 };
1885
1886 static const unsigned short dep75[] = {
1887 15, 97, 211, 212, 282,
1888 };
1889
1890 static const unsigned short dep76[] = {
1891 40, 41, 97, 158, 162, 175, 185, 211, 212, 282, 2166, 2167, 2170, 2173, 4135,
1892
1893 };
1894
1895 static const unsigned short dep77[] = {
1896 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135,
1897 };
1898
1899 static const unsigned short dep78[] = {
1900 16, 97, 214, 215, 282,
1901 };
1902
1903 static const unsigned short dep79[] = {
1904 40, 41, 97, 158, 162, 175, 185, 214, 215, 282, 2166, 2167, 2170, 2173, 4135,
1905
1906 };
1907
1908 static const unsigned short dep80[] = {
1909 17, 97, 217, 218, 282,
1910 };
1911
1912 static const unsigned short dep81[] = {
1913 40, 41, 97, 158, 162, 175, 185, 217, 218, 282, 2166, 2167, 2170, 2173, 4135,
1914
1915 };
1916
1917 static const unsigned short dep82[] = {
1918 18, 97, 220, 221, 282,
1919 };
1920
1921 static const unsigned short dep83[] = {
1922 40, 41, 97, 158, 162, 175, 185, 220, 221, 282, 2166, 2167, 2170, 2173, 4135,
1923
1924 };
1925
1926 static const unsigned short dep84[] = {
1927 15, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167,
1928 2170, 2173, 4135,
1929 };
1930
1931 static const unsigned short dep85[] = {
1932 15, 16, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166,
1933 2167, 2170, 2173, 4135,
1934 };
1935
1936 static const unsigned short dep86[] = {
1937 15, 17, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166,
1938 2167, 2170, 2173, 4135,
1939 };
1940
1941 static const unsigned short dep87[] = {
1942 15, 18, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166,
1943 2167, 2170, 2173, 4135,
1944 };
1945
1946 static const unsigned short dep88[] = {
1947 15, 97, 210, 211, 282,
1948 };
1949
1950 static const unsigned short dep89[] = {
1951 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2166, 2167, 2170,
1952 2173, 4135,
1953 };
1954
1955 static const unsigned short dep90[] = {
1956 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282,
1957 };
1958
1959 static const unsigned short dep91[] = {
1960 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
1961 216, 218, 219, 221, 282, 2166, 2167, 2170, 2173, 4135,
1962 };
1963
1964 static const unsigned short dep92[] = {
1965 16, 97, 213, 214, 282,
1966 };
1967
1968 static const unsigned short dep93[] = {
1969 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2166, 2167, 2170,
1970 2173, 4135,
1971 };
1972
1973 static const unsigned short dep94[] = {
1974 17, 97, 216, 217, 282,
1975 };
1976
1977 static const unsigned short dep95[] = {
1978 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2166, 2167, 2170,
1979 2173, 4135,
1980 };
1981
1982 static const unsigned short dep96[] = {
1983 18, 97, 219, 220, 282,
1984 };
1985
1986 static const unsigned short dep97[] = {
1987 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2166, 2167, 2170,
1988 2173, 4135,
1989 };
1990
1991 static const unsigned short dep98[] = {
1992 15, 97, 210, 211, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
1993 2348, 2351, 2352, 2355, 2356,
1994 };
1995
1996 static const unsigned short dep99[] = {
1997 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
1998 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
1999 16530, 16531, 16533,
2000 };
2001
2002 static const unsigned short dep100[] = {
2003 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2166, 2167,
2004 2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351, 2352, 2355, 2356,
2005 };
2006
2007 static const unsigned short dep101[] = {
2008 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
2009 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2344, 2347,
2010 2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533,
2011 };
2012
2013 static const unsigned short dep102[] = {
2014 16, 97, 213, 214, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
2015 2348, 2351, 2352, 2355, 2356,
2016 };
2017
2018 static const unsigned short dep103[] = {
2019 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
2020 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
2021 16530, 16531, 16533,
2022 };
2023
2024 static const unsigned short dep104[] = {
2025 17, 97, 216, 217, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
2026 2348, 2351, 2352, 2355, 2356,
2027 };
2028
2029 static const unsigned short dep105[] = {
2030 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
2031 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
2032 16530, 16531, 16533,
2033 };
2034
2035 static const unsigned short dep106[] = {
2036 18, 97, 219, 220, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
2037 2348, 2351, 2352, 2355, 2356,
2038 };
2039
2040 static const unsigned short dep107[] = {
2041 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
2042 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
2043 16530, 16531, 16533,
2044 };
2045
2046 static const unsigned short dep108[] = {
2047 15, 97, 210, 211, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2048 22827, 22828, 22831, 22832, 22835, 22836,
2049 };
2050
2051 static const unsigned short dep109[] = {
2052 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
2053 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2054 22831, 22832, 22835, 22836,
2055 };
2056
2057 static const unsigned short dep110[] = {
2058 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 22646, 22647,
2059 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835,
2060 22836,
2061 };
2062
2063 static const unsigned short dep111[] = {
2064 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
2065 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 4135, 16528,
2066 16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
2067 };
2068
2069 static const unsigned short dep112[] = {
2070 16, 97, 213, 214, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2071 22827, 22828, 22831, 22832, 22835, 22836,
2072 };
2073
2074 static const unsigned short dep113[] = {
2075 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
2076 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2077 22831, 22832, 22835, 22836,
2078 };
2079
2080 static const unsigned short dep114[] = {
2081 17, 97, 216, 217, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2082 22827, 22828, 22831, 22832, 22835, 22836,
2083 };
2084
2085 static const unsigned short dep115[] = {
2086 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
2087 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2088 22831, 22832, 22835, 22836,
2089 };
2090
2091 static const unsigned short dep116[] = {
2092 18, 97, 219, 220, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2093 22827, 22828, 22831, 22832, 22835, 22836,
2094 };
2095
2096 static const unsigned short dep117[] = {
2097 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
2098 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2099 22831, 22832, 22835, 22836,
2100 };
2101
2102 static const unsigned short dep118[] = {
2103 97, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351,
2104 2352, 2355, 2356,
2105 };
2106
2107 static const unsigned short dep119[] = {
2108 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173,
2109 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533,
2110
2111 };
2112
2113 static const unsigned short dep120[] = {
2114 97, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828,
2115 22831, 22832, 22835, 22836,
2116 };
2117
2118 static const unsigned short dep121[] = {
2119 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173,
2120 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835,
2121 22836,
2122 };
2123
2124 static const unsigned short dep122[] = {
2125 19, 20, 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167,
2126 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766,
2127
2128 };
2129
2130 static const unsigned short dep123[] = {
2131 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2138, 2139, 2140, 2166,
2132 2167, 2170, 2173, 4135, 20616,
2133 };
2134
2135 static const unsigned short dep124[] = {
2136 97, 282, 2083, 2084, 2286, 2287,
2137 };
2138
2139 static const unsigned short dep125[] = {
2140 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
2141 2285, 2287, 4135, 20616,
2142 };
2143
2144 static const unsigned short dep126[] = {
2145 40, 41, 97, 158, 162, 175, 185, 282, 2082, 2084, 2166, 2167, 2170, 2173, 2327,
2146 4135, 20616,
2147 };
2148
2149 static const unsigned short dep127[] = {
2150 97, 282, 14455, 14457, 14458, 14460, 14461, 14463, 14635, 14636, 14639, 14640,
2151 14643, 14644,
2152 };
2153
2154 static const unsigned short dep128[] = {
2155 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 4135, 14635, 14636,
2156 14639, 14640, 14643, 14644, 20616, 24694, 24695, 24698, 24701,
2157 };
2158
2159 static const unsigned short dep129[] = {
2160 97, 122, 124, 125, 127, 282, 303, 304, 307, 308,
2161 };
2162
2163 static const unsigned short dep130[] = {
2164 40, 41, 97, 158, 162, 175, 185, 282, 303, 304, 307, 308, 4135, 24694, 24695,
2165 24698, 24701,
2166 };
2167
2168 static const unsigned short dep131[] = {
2169 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2327, 4135, 20616,
2170
2171 };
2172
2173 static const unsigned short dep132[] = {
2174 40, 41, 97, 119, 122, 125, 158, 162, 175, 185, 282, 2327, 4135, 20616, 24694,
2175
2176 };
2177
2178 static const unsigned short dep133[] = {
2179 6, 24, 26, 27, 97, 201, 227, 230, 282, 2081, 2284,
2180 };
2181
2182 static const unsigned short dep134[] = {
2183 40, 41, 97, 158, 162, 175, 185, 201, 227, 229, 282, 2138, 2139, 2140, 2166,
2184 2167, 2170, 2173, 2284, 4135, 20616,
2185 };
2186
2187 static const unsigned short dep135[] = {
2188 6, 24, 25, 26, 40, 41, 97, 158, 162, 175, 185, 282, 2081, 2166, 2167, 2170,
2189 2173, 2327, 4135, 20616,
2190 };
2191
2192 static const unsigned short dep136[] = {
2193 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2347, 2348,
2194 2351, 2352, 2355, 2356, 4135,
2195 };
2196
2197 static const unsigned short dep137[] = {
2198 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, 22824,
2199 22827, 22828, 22831, 22832, 22835, 22836,
2200 };
2201
2202 static const unsigned short dep138[] = {
2203 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2348,
2204 2349, 2352, 2353, 2356, 4135,
2205 };
2206
2207 static const unsigned short dep139[] = {
2208 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2346, 2347,
2209 2350, 2351, 2354, 2355, 4135,
2210 };
2211
2212 static const unsigned short dep140[] = {
2213 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2346,
2214 2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 4135,
2215 };
2216
2217 static const unsigned short dep141[] = {
2218 0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167, 2170, 2173,
2219 4135,
2220 };
2221
2222 static const unsigned short dep142[] = {
2223 0, 97, 195, 282,
2224 };
2225
2226 static const unsigned short dep143[] = {
2227 0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 195, 282, 2166, 2167, 2170,
2228 2173, 4135,
2229 };
2230
2231 static const unsigned short dep144[] = {
2232 40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135,
2233 };
2234
2235 static const unsigned short dep145[] = {
2236 2, 28, 97, 197, 231, 282, 28866, 29018,
2237 };
2238
2239 static const unsigned short dep146[] = {
2240 1, 2, 28, 29, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 28866, 29018,
2241
2242 };
2243
2244 static const unsigned short dep147[] = {
2245 1, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 4135,
2246 28866, 29018,
2247 };
2248
2249 static const unsigned short dep148[] = {
2250 0, 40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135,
2251
2252 };
2253
2254 static const unsigned short dep149[] = {
2255 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
2256 28, 29, 30, 31, 97, 196, 197, 198, 199, 200, 202, 203, 204, 205, 206, 207,
2257 208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, 223, 224, 225, 231,
2258 232, 233, 234, 282, 2071, 2081, 2274, 2284, 28866, 29018,
2259 };
2260
2261 static const unsigned short dep150[] = {
2262 29, 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 196, 197, 198, 199,
2263 200, 202, 203, 204, 205, 206, 207, 208, 209, 211, 212, 214, 215, 217, 218,
2264 220, 221, 222, 223, 224, 225, 231, 232, 233, 234, 282, 2138, 2139, 2140, 2166,
2265 2167, 2170, 2173, 2274, 2284, 4135, 20616, 28866, 29018,
2266 };
2267
2268 static const unsigned short dep151[] = {
2269 97, 282, 14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666,
2270 14667, 14669, 14670, 14679,
2271 };
2272
2273 static const unsigned short dep152[] = {
2274 40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 2166, 2167, 2170, 2173, 4135,
2275 14645, 14646, 14666, 14667, 14669, 14670, 14679,
2276 };
2277
2278 static const unsigned short dep153[] = {
2279 14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666, 14667,
2280 14669, 14670, 14679,
2281 };
2282
2283 static const unsigned short dep154[] = {
2284 183, 184, 14645, 14646, 14666, 14667, 14669, 14670, 14679,
2285 };
2286
2287 static const unsigned short dep155[] = {
2288 97, 282, 14465, 14466, 14469, 14470, 14480, 14481, 14483, 14484, 14486, 14487,
2289 14489, 14490, 14493, 14495, 14496, 14505, 14506, 14507, 14508, 14510, 14515,
2290 14516, 14518, 14519, 14525, 14645, 14646, 14652, 14653, 14654, 14655, 14657,
2291 14659, 14666, 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679,
2292 };
2293
2294 static const unsigned short dep156[] = {
2295 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170,
2296 2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666,
2297 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, 34888,
2298 };
2299
2300 static const unsigned short dep157[] = {
2301 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170,
2302 2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666,
2303 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679,
2304 };
2305
2306 static const unsigned short dep158[] = {
2307 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
2308 28, 29, 30, 31, 40, 41, 97, 137, 138, 158, 162, 175, 180, 181, 185, 190, 191,
2309 282, 2071, 2081, 2166, 2167, 2170, 2173, 2327, 4135, 20616, 28866,
2310 };
2311
2312 static const unsigned short dep159[] = {
2313 43, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 56, 57, 58, 60, 61, 62, 63,
2314 64, 65, 67, 69, 70, 71, 72, 73, 94, 96, 97, 243, 244, 245, 246, 247, 248,
2315 249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261, 263, 264, 265, 281,
2316 282, 2116, 2310,
2317 };
2318
2319 static const unsigned short dep160[] = {
2320 40, 41, 96, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191, 243, 244,
2321 245, 246, 247, 248, 249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261,
2322 263, 264, 265, 281, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2310, 4135,
2323 20616,
2324 };
2325
2326 static const unsigned short dep161[] = {
2327 59, 95, 97, 254, 281, 282, 2140, 2327,
2328 };
2329
2330 static const unsigned short dep162[] = {
2331 40, 41, 43, 44, 46, 48, 49, 51, 52, 53, 54, 56, 57, 60, 61, 63, 64, 65, 66,
2332 67, 69, 70, 71, 94, 95, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191,
2333 254, 281, 282, 2107, 2116, 2166, 2167, 2170, 2173, 2327, 4135, 20616,
2334 };
2335
2336 static const unsigned short dep163[] = {
2337 2, 28, 41, 97, 197, 231, 241, 282, 2140, 2327, 28866, 29018,
2338 };
2339
2340 static const unsigned short dep164[] = {
2341 2, 25, 26, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231,
2342 241, 282, 2327, 4135, 20616, 28866, 29018,
2343 };
2344
2345 static const unsigned short dep165[] = {
2346 97, 129, 130, 133, 134, 140, 141, 144, 145, 147, 148, 150, 151, 153, 154,
2347 157, 159, 160, 165, 166, 169, 170, 171, 172, 174, 176, 177, 179, 180, 182,
2348 183, 186, 187, 189, 282, 309, 310, 314, 316, 317, 318, 319, 321, 323, 327,
2349 330, 331, 333, 334, 335, 336, 338, 339, 340, 342, 343,
2350 };
2351
2352 static const unsigned short dep166[] = {
2353 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 309, 310, 314, 316,
2354 317, 318, 319, 321, 323, 327, 330, 331, 333, 334, 335, 336, 338, 339, 340,
2355 342, 343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, 34888,
2356 };
2357
2358 static const unsigned short dep167[] = {
2359 97, 128, 130, 132, 134, 169, 170, 189, 282, 309, 310, 330, 331, 333, 334,
2360 343,
2361 };
2362
2363 static const unsigned short dep168[] = {
2364 40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 309, 310, 330, 331, 333, 334,
2365 343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616,
2366 };
2367
2368 static const unsigned short dep169[] = {
2369 40, 41, 97, 130, 131, 134, 135, 137, 138, 141, 142, 145, 146, 148, 149, 151,
2370 152, 154, 155, 157, 158, 159, 161, 162, 164, 165, 167, 168, 169, 170, 172,
2371 173, 174, 175, 176, 178, 179, 181, 182, 184, 185, 187, 188, 189, 190, 191,
2372 282, 2166, 2167, 2170, 2173, 2327, 4135, 20616,
2373 };
2374
2375 static const unsigned short dep170[] = {
2376 40, 41, 97, 130, 131, 134, 135, 158, 162, 169, 170, 175, 185, 189, 282, 2166,
2377 2167, 2170, 2173, 2327, 4135, 20616,
2378 };
2379
2380 static const unsigned short dep171[] = {
2381 40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 153, 155, 158, 162, 171, 173,
2382 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135,
2383 20616,
2384 };
2385
2386 static const unsigned short dep172[] = {
2387 40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 139, 140, 142, 143, 153, 155,
2388 158, 162, 171, 173, 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170,
2389 2173, 4135, 20616,
2390 };
2391
2392 static const unsigned short dep173[] = {
2393 77, 78, 97, 101, 102, 269, 270, 282, 284, 285,
2394 };
2395
2396 static const unsigned short dep174[] = {
2397 40, 41, 47, 62, 78, 80, 86, 97, 99, 102, 137, 138, 158, 160, 161, 162, 175,
2398 185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166, 2167,
2399 2170, 2173, 4135, 20616,
2400 };
2401
2402 static const unsigned short dep175[] = {
2403 40, 41, 47, 62, 78, 80, 97, 99, 102, 104, 106, 137, 138, 158, 160, 161, 162,
2404 175, 185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166,
2405 2167, 2170, 2173, 4135, 20616,
2406 };
2407
2408 static const unsigned short dep176[] = {
2409 97, 282, 12480, 12481, 12633,
2410 };
2411
2412 static const unsigned short dep177[] = {
2413 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2414 2166, 2167, 2170, 2173, 4135, 12633, 20616,
2415 };
2416
2417 static const unsigned short dep178[] = {
2418 97, 282, 6219, 6220, 6411,
2419 };
2420
2421 static const unsigned short dep179[] = {
2422 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2423 2166, 2167, 2170, 2173, 4135, 6411, 20616,
2424 };
2425
2426 static const unsigned short dep180[] = {
2427 97, 282, 6237, 6424,
2428 };
2429
2430 static const unsigned short dep181[] = {
2431 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2432 2166, 2167, 2170, 2173, 4135, 6424, 20616,
2433 };
2434
2435 static const unsigned short dep182[] = {
2436 97, 282, 6255, 6256, 6257, 6258, 6435, 6437, 8484,
2437 };
2438
2439 static const unsigned short dep183[] = {
2440 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2441 2166, 2167, 2170, 2173, 4135, 6258, 6436, 6437, 8304, 8483, 20616,
2442 };
2443
2444 static const unsigned short dep184[] = {
2445 97, 282, 6259, 6260, 6438,
2446 };
2447
2448 static const unsigned short dep185[] = {
2449 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2450 2166, 2167, 2170, 2173, 4135, 6438, 20616,
2451 };
2452
2453 static const unsigned short dep186[] = {
2454 97, 282, 6261, 6439,
2455 };
2456
2457 static const unsigned short dep187[] = {
2458 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2459 2166, 2167, 2170, 2173, 4135, 6439, 20616,
2460 };
2461
2462 static const unsigned short dep188[] = {
2463 97, 282, 10350, 10530,
2464 };
2465
2466 static const unsigned short dep189[] = {
2467 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2468 2166, 2167, 2170, 2173, 4135, 10530, 20616,
2469 };
2470
2471 static const unsigned short dep190[] = {
2472 77, 78, 82, 83, 97, 101, 102, 269, 270, 272, 273, 282, 284, 285,
2473 };
2474
2475 static const unsigned short dep191[] = {