disas: Clean up CPUDebug initialization
[qemu.git] / include / disas / dis-asm.h
1 /* Interface between the opcode library and its callers.
2 Written by Cygnus Support, 1993.
3
4 The opcode library (libopcodes.a) provides instruction decoders for
5 a large variety of instruction sets, callable with an identical
6 interface, for making instruction-processing programs more independent
7 of the instruction set being processed. */
8
9 #ifndef DISAS_DIS_ASM_H
10 #define DISAS_DIS_ASM_H
11
12 typedef void *PTR;
13 typedef uint64_t bfd_vma;
14 typedef int64_t bfd_signed_vma;
15 typedef uint8_t bfd_byte;
16 #define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
17 #define snprintf_vma(s,ss,x) snprintf (s, ss, "%0" PRIx64, x)
18
19 #define BFD64
20
21 enum bfd_flavour {
22 bfd_target_unknown_flavour,
23 bfd_target_aout_flavour,
24 bfd_target_coff_flavour,
25 bfd_target_ecoff_flavour,
26 bfd_target_elf_flavour,
27 bfd_target_ieee_flavour,
28 bfd_target_nlm_flavour,
29 bfd_target_oasys_flavour,
30 bfd_target_tekhex_flavour,
31 bfd_target_srec_flavour,
32 bfd_target_ihex_flavour,
33 bfd_target_som_flavour,
34 bfd_target_os9k_flavour,
35 bfd_target_versados_flavour,
36 bfd_target_msdos_flavour,
37 bfd_target_evax_flavour
38 };
39
40 enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
41
42 enum bfd_architecture
43 {
44 bfd_arch_unknown, /* File arch not known */
45 bfd_arch_obscure, /* Arch known, not one of these */
46 bfd_arch_m68k, /* Motorola 68xxx */
47 #define bfd_mach_m68000 1
48 #define bfd_mach_m68008 2
49 #define bfd_mach_m68010 3
50 #define bfd_mach_m68020 4
51 #define bfd_mach_m68030 5
52 #define bfd_mach_m68040 6
53 #define bfd_mach_m68060 7
54 #define bfd_mach_cpu32 8
55 #define bfd_mach_mcf5200 9
56 #define bfd_mach_mcf5206e 10
57 #define bfd_mach_mcf5307 11
58 #define bfd_mach_mcf5407 12
59 #define bfd_mach_mcf528x 13
60 #define bfd_mach_mcfv4e 14
61 #define bfd_mach_mcf521x 15
62 #define bfd_mach_mcf5249 16
63 #define bfd_mach_mcf547x 17
64 #define bfd_mach_mcf548x 18
65 bfd_arch_vax, /* DEC Vax */
66 bfd_arch_i960, /* Intel 960 */
67 /* The order of the following is important.
68 lower number indicates a machine type that
69 only accepts a subset of the instructions
70 available to machines with higher numbers.
71 The exception is the "ca", which is
72 incompatible with all other machines except
73 "core". */
74
75 #define bfd_mach_i960_core 1
76 #define bfd_mach_i960_ka_sa 2
77 #define bfd_mach_i960_kb_sb 3
78 #define bfd_mach_i960_mc 4
79 #define bfd_mach_i960_xa 5
80 #define bfd_mach_i960_ca 6
81 #define bfd_mach_i960_jx 7
82 #define bfd_mach_i960_hx 8
83
84 bfd_arch_a29k, /* AMD 29000 */
85 bfd_arch_sparc, /* SPARC */
86 #define bfd_mach_sparc 1
87 /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
88 #define bfd_mach_sparc_sparclet 2
89 #define bfd_mach_sparc_sparclite 3
90 #define bfd_mach_sparc_v8plus 4
91 #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
92 #define bfd_mach_sparc_sparclite_le 6
93 #define bfd_mach_sparc_v9 7
94 #define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
95 #define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
96 #define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
97 /* Nonzero if MACH has the v9 instruction set. */
98 #define bfd_mach_sparc_v9_p(mach) \
99 ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
100 && (mach) != bfd_mach_sparc_sparclite_le)
101 bfd_arch_mips, /* MIPS Rxxxx */
102 #define bfd_mach_mips3000 3000
103 #define bfd_mach_mips3900 3900
104 #define bfd_mach_mips4000 4000
105 #define bfd_mach_mips4010 4010
106 #define bfd_mach_mips4100 4100
107 #define bfd_mach_mips4300 4300
108 #define bfd_mach_mips4400 4400
109 #define bfd_mach_mips4600 4600
110 #define bfd_mach_mips4650 4650
111 #define bfd_mach_mips5000 5000
112 #define bfd_mach_mips6000 6000
113 #define bfd_mach_mips8000 8000
114 #define bfd_mach_mips10000 10000
115 #define bfd_mach_mips16 16
116 bfd_arch_i386, /* Intel 386 */
117 #define bfd_mach_i386_i386 0
118 #define bfd_mach_i386_i8086 1
119 #define bfd_mach_i386_i386_intel_syntax 2
120 #define bfd_mach_x86_64 3
121 #define bfd_mach_x86_64_intel_syntax 4
122 bfd_arch_we32k, /* AT&T WE32xxx */
123 bfd_arch_tahoe, /* CCI/Harris Tahoe */
124 bfd_arch_i860, /* Intel 860 */
125 bfd_arch_romp, /* IBM ROMP PC/RT */
126 bfd_arch_alliant, /* Alliant */
127 bfd_arch_convex, /* Convex */
128 bfd_arch_m88k, /* Motorola 88xxx */
129 bfd_arch_pyramid, /* Pyramid Technology */
130 bfd_arch_h8300, /* Hitachi H8/300 */
131 #define bfd_mach_h8300 1
132 #define bfd_mach_h8300h 2
133 #define bfd_mach_h8300s 3
134 bfd_arch_powerpc, /* PowerPC */
135 #define bfd_mach_ppc 0
136 #define bfd_mach_ppc64 1
137 #define bfd_mach_ppc_403 403
138 #define bfd_mach_ppc_403gc 4030
139 #define bfd_mach_ppc_e500 500
140 #define bfd_mach_ppc_505 505
141 #define bfd_mach_ppc_601 601
142 #define bfd_mach_ppc_602 602
143 #define bfd_mach_ppc_603 603
144 #define bfd_mach_ppc_ec603e 6031
145 #define bfd_mach_ppc_604 604
146 #define bfd_mach_ppc_620 620
147 #define bfd_mach_ppc_630 630
148 #define bfd_mach_ppc_750 750
149 #define bfd_mach_ppc_860 860
150 #define bfd_mach_ppc_a35 35
151 #define bfd_mach_ppc_rs64ii 642
152 #define bfd_mach_ppc_rs64iii 643
153 #define bfd_mach_ppc_7400 7400
154 bfd_arch_rs6000, /* IBM RS/6000 */
155 bfd_arch_hppa, /* HP PA RISC */
156 #define bfd_mach_hppa10 10
157 #define bfd_mach_hppa11 11
158 #define bfd_mach_hppa20 20
159 #define bfd_mach_hppa20w 25
160 bfd_arch_d10v, /* Mitsubishi D10V */
161 bfd_arch_z8k, /* Zilog Z8000 */
162 #define bfd_mach_z8001 1
163 #define bfd_mach_z8002 2
164 bfd_arch_h8500, /* Hitachi H8/500 */
165 bfd_arch_sh, /* Hitachi SH */
166 #define bfd_mach_sh 1
167 #define bfd_mach_sh2 0x20
168 #define bfd_mach_sh_dsp 0x2d
169 #define bfd_mach_sh2a 0x2a
170 #define bfd_mach_sh2a_nofpu 0x2b
171 #define bfd_mach_sh2e 0x2e
172 #define bfd_mach_sh3 0x30
173 #define bfd_mach_sh3_nommu 0x31
174 #define bfd_mach_sh3_dsp 0x3d
175 #define bfd_mach_sh3e 0x3e
176 #define bfd_mach_sh4 0x40
177 #define bfd_mach_sh4_nofpu 0x41
178 #define bfd_mach_sh4_nommu_nofpu 0x42
179 #define bfd_mach_sh4a 0x4a
180 #define bfd_mach_sh4a_nofpu 0x4b
181 #define bfd_mach_sh4al_dsp 0x4d
182 #define bfd_mach_sh5 0x50
183 bfd_arch_alpha, /* Dec Alpha */
184 #define bfd_mach_alpha 1
185 #define bfd_mach_alpha_ev4 0x10
186 #define bfd_mach_alpha_ev5 0x20
187 #define bfd_mach_alpha_ev6 0x30
188 bfd_arch_arm, /* Advanced Risc Machines ARM */
189 #define bfd_mach_arm_unknown 0
190 #define bfd_mach_arm_2 1
191 #define bfd_mach_arm_2a 2
192 #define bfd_mach_arm_3 3
193 #define bfd_mach_arm_3M 4
194 #define bfd_mach_arm_4 5
195 #define bfd_mach_arm_4T 6
196 #define bfd_mach_arm_5 7
197 #define bfd_mach_arm_5T 8
198 #define bfd_mach_arm_5TE 9
199 #define bfd_mach_arm_XScale 10
200 #define bfd_mach_arm_ep9312 11
201 #define bfd_mach_arm_iWMMXt 12
202 #define bfd_mach_arm_iWMMXt2 13
203 bfd_arch_ns32k, /* National Semiconductors ns32000 */
204 bfd_arch_w65, /* WDC 65816 */
205 bfd_arch_tic30, /* Texas Instruments TMS320C30 */
206 bfd_arch_v850, /* NEC V850 */
207 #define bfd_mach_v850 0
208 bfd_arch_arc, /* Argonaut RISC Core */
209 #define bfd_mach_arc_base 0
210 bfd_arch_m32r, /* Mitsubishi M32R/D */
211 #define bfd_mach_m32r 0 /* backwards compatibility */
212 bfd_arch_mn10200, /* Matsushita MN10200 */
213 bfd_arch_mn10300, /* Matsushita MN10300 */
214 bfd_arch_avr, /* AVR microcontrollers */
215 #define bfd_mach_avr1 1
216 #define bfd_mach_avr2 2
217 #define bfd_mach_avr25 25
218 #define bfd_mach_avr3 3
219 #define bfd_mach_avr31 31
220 #define bfd_mach_avr35 35
221 #define bfd_mach_avr4 4
222 #define bfd_mach_avr5 5
223 #define bfd_mach_avr51 51
224 #define bfd_mach_avr6 6
225 #define bfd_mach_avrtiny 100
226 #define bfd_mach_avrxmega1 101
227 #define bfd_mach_avrxmega2 102
228 #define bfd_mach_avrxmega3 103
229 #define bfd_mach_avrxmega4 104
230 #define bfd_mach_avrxmega5 105
231 #define bfd_mach_avrxmega6 106
232 #define bfd_mach_avrxmega7 107
233 bfd_arch_cris, /* Axis CRIS */
234 #define bfd_mach_cris_v0_v10 255
235 #define bfd_mach_cris_v32 32
236 #define bfd_mach_cris_v10_v32 1032
237 bfd_arch_microblaze, /* Xilinx MicroBlaze. */
238 bfd_arch_moxie, /* The Moxie core. */
239 bfd_arch_ia64, /* HP/Intel ia64 */
240 #define bfd_mach_ia64_elf64 64
241 #define bfd_mach_ia64_elf32 32
242 bfd_arch_nios2, /* Nios II */
243 #define bfd_mach_nios2 0
244 #define bfd_mach_nios2r1 1
245 #define bfd_mach_nios2r2 2
246 bfd_arch_lm32, /* Lattice Mico32 */
247 #define bfd_mach_lm32 1
248 bfd_arch_rx, /* Renesas RX */
249 #define bfd_mach_rx 0x75
250 #define bfd_mach_rx_v2 0x76
251 #define bfd_mach_rx_v3 0x77
252 bfd_arch_last
253 };
254 #define bfd_mach_s390_31 31
255 #define bfd_mach_s390_64 64
256
257 typedef struct symbol_cache_entry
258 {
259 const char *name;
260 union
261 {
262 PTR p;
263 bfd_vma i;
264 } udata;
265 } asymbol;
266
267 typedef int (*fprintf_function)(FILE *f, const char *fmt, ...)
268 GCC_FMT_ATTR(2, 3);
269
270 enum dis_insn_type {
271 dis_noninsn, /* Not a valid instruction */
272 dis_nonbranch, /* Not a branch instruction */
273 dis_branch, /* Unconditional branch */
274 dis_condbranch, /* Conditional branch */
275 dis_jsr, /* Jump to subroutine */
276 dis_condjsr, /* Conditional jump to subroutine */
277 dis_dref, /* Data reference instruction */
278 dis_dref2 /* Two data references in instruction */
279 };
280
281 /* This struct is passed into the instruction decoding routine,
282 and is passed back out into each callback. The various fields are used
283 for conveying information from your main routine into your callbacks,
284 for passing information into the instruction decoders (such as the
285 addresses of the callback functions), or for passing information
286 back from the instruction decoders to their callers.
287
288 It must be initialized before it is first passed; this can be done
289 by hand, or using one of the initialization macros below. */
290
291 typedef struct disassemble_info {
292 fprintf_function fprintf_func;
293 FILE *stream;
294 PTR application_data;
295
296 /* Target description. We could replace this with a pointer to the bfd,
297 but that would require one. There currently isn't any such requirement
298 so to avoid introducing one we record these explicitly. */
299 /* The bfd_flavour. This can be bfd_target_unknown_flavour. */
300 enum bfd_flavour flavour;
301 /* The bfd_arch value. */
302 enum bfd_architecture arch;
303 /* The bfd_mach value. */
304 unsigned long mach;
305 /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
306 enum bfd_endian endian;
307
308 /* An array of pointers to symbols either at the location being disassembled
309 or at the start of the function being disassembled. The array is sorted
310 so that the first symbol is intended to be the one used. The others are
311 present for any misc. purposes. This is not set reliably, but if it is
312 not NULL, it is correct. */
313 asymbol **symbols;
314 /* Number of symbols in array. */
315 int num_symbols;
316
317 /* For use by the disassembler.
318 The top 16 bits are reserved for public use (and are documented here).
319 The bottom 16 bits are for the internal use of the disassembler. */
320 unsigned long flags;
321 #define INSN_HAS_RELOC 0x80000000
322 #define INSN_ARM_BE32 0x00010000
323 PTR private_data;
324
325 /* Function used to get bytes to disassemble. MEMADDR is the
326 address of the stuff to be disassembled, MYADDR is the address to
327 put the bytes in, and LENGTH is the number of bytes to read.
328 INFO is a pointer to this struct.
329 Returns an errno value or 0 for success. */
330 int (*read_memory_func)
331 (bfd_vma memaddr, bfd_byte *myaddr, int length,
332 struct disassemble_info *info);
333
334 /* Function which should be called if we get an error that we can't
335 recover from. STATUS is the errno value from read_memory_func and
336 MEMADDR is the address that we were trying to read. INFO is a
337 pointer to this struct. */
338 void (*memory_error_func)
339 (int status, bfd_vma memaddr, struct disassemble_info *info);
340
341 /* Function called to print ADDR. */
342 void (*print_address_func)
343 (bfd_vma addr, struct disassemble_info *info);
344
345 /* Function called to print an instruction. The function is architecture
346 * specific.
347 */
348 int (*print_insn)(bfd_vma addr, struct disassemble_info *info);
349
350 /* Function called to determine if there is a symbol at the given ADDR.
351 If there is, the function returns 1, otherwise it returns 0.
352 This is used by ports which support an overlay manager where
353 the overlay number is held in the top part of an address. In
354 some circumstances we want to include the overlay number in the
355 address, (normally because there is a symbol associated with
356 that address), but sometimes we want to mask out the overlay bits. */
357 int (* symbol_at_address_func)
358 (bfd_vma addr, struct disassemble_info * info);
359
360 /* These are for buffer_read_memory. */
361 bfd_byte *buffer;
362 bfd_vma buffer_vma;
363 int buffer_length;
364
365 /* This variable may be set by the instruction decoder. It suggests
366 the number of bytes objdump should display on a single line. If
367 the instruction decoder sets this, it should always set it to
368 the same value in order to get reasonable looking output. */
369 int bytes_per_line;
370
371 /* the next two variables control the way objdump displays the raw data */
372 /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
373 /* output will look like this:
374 00: 00000000 00000000
375 with the chunks displayed according to "display_endian". */
376 int bytes_per_chunk;
377 enum bfd_endian display_endian;
378
379 /* Results from instruction decoders. Not all decoders yet support
380 this information. This info is set each time an instruction is
381 decoded, and is only valid for the last such instruction.
382
383 To determine whether this decoder supports this information, set
384 insn_info_valid to 0, decode an instruction, then check it. */
385
386 char insn_info_valid; /* Branch info has been set. */
387 char branch_delay_insns; /* How many sequential insn's will run before
388 a branch takes effect. (0 = normal) */
389 char data_size; /* Size of data reference in insn, in bytes */
390 enum dis_insn_type insn_type; /* Type of instruction */
391 bfd_vma target; /* Target address of branch or dref, if known;
392 zero if unknown. */
393 bfd_vma target2; /* Second target address for dref2 */
394
395 /* Command line options specific to the target disassembler. */
396 char * disassembler_options;
397
398 /* Field intended to be used by targets in any way they deem suitable. */
399 int64_t target_info;
400
401 /* Options for Capstone disassembly. */
402 int cap_arch;
403 int cap_mode;
404 int cap_insn_unit;
405 int cap_insn_split;
406
407 } disassemble_info;
408
409 /* Standard disassemblers. Disassemble one instruction at the given
410 target address. Return number of bytes processed. */
411 typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
412
413 int print_insn_tci(bfd_vma, disassemble_info*);
414 int print_insn_big_mips (bfd_vma, disassemble_info*);
415 int print_insn_little_mips (bfd_vma, disassemble_info*);
416 int print_insn_nanomips (bfd_vma, disassemble_info*);
417 int print_insn_i386 (bfd_vma, disassemble_info*);
418 int print_insn_m68k (bfd_vma, disassemble_info*);
419 int print_insn_z8001 (bfd_vma, disassemble_info*);
420 int print_insn_z8002 (bfd_vma, disassemble_info*);
421 int print_insn_h8300 (bfd_vma, disassemble_info*);
422 int print_insn_h8300h (bfd_vma, disassemble_info*);
423 int print_insn_h8300s (bfd_vma, disassemble_info*);
424 int print_insn_h8500 (bfd_vma, disassemble_info*);
425 int print_insn_arm_a64 (bfd_vma, disassemble_info*);
426 int print_insn_alpha (bfd_vma, disassemble_info*);
427 disassembler_ftype arc_get_disassembler (int, int);
428 int print_insn_arm (bfd_vma, disassemble_info*);
429 int print_insn_sparc (bfd_vma, disassemble_info*);
430 int print_insn_big_a29k (bfd_vma, disassemble_info*);
431 int print_insn_little_a29k (bfd_vma, disassemble_info*);
432 int print_insn_i960 (bfd_vma, disassemble_info*);
433 int print_insn_sh (bfd_vma, disassemble_info*);
434 int print_insn_shl (bfd_vma, disassemble_info*);
435 int print_insn_hppa (bfd_vma, disassemble_info*);
436 int print_insn_m32r (bfd_vma, disassemble_info*);
437 int print_insn_m88k (bfd_vma, disassemble_info*);
438 int print_insn_mn10200 (bfd_vma, disassemble_info*);
439 int print_insn_mn10300 (bfd_vma, disassemble_info*);
440 int print_insn_moxie (bfd_vma, disassemble_info*);
441 int print_insn_ns32k (bfd_vma, disassemble_info*);
442 int print_insn_big_powerpc (bfd_vma, disassemble_info*);
443 int print_insn_little_powerpc (bfd_vma, disassemble_info*);
444 int print_insn_rs6000 (bfd_vma, disassemble_info*);
445 int print_insn_w65 (bfd_vma, disassemble_info*);
446 int print_insn_d10v (bfd_vma, disassemble_info*);
447 int print_insn_v850 (bfd_vma, disassemble_info*);
448 int print_insn_tic30 (bfd_vma, disassemble_info*);
449 int print_insn_ppc (bfd_vma, disassemble_info*);
450 int print_insn_s390 (bfd_vma, disassemble_info*);
451 int print_insn_crisv32 (bfd_vma, disassemble_info*);
452 int print_insn_crisv10 (bfd_vma, disassemble_info*);
453 int print_insn_microblaze (bfd_vma, disassemble_info*);
454 int print_insn_ia64 (bfd_vma, disassemble_info*);
455 int print_insn_lm32 (bfd_vma, disassemble_info*);
456 int print_insn_big_nios2 (bfd_vma, disassemble_info*);
457 int print_insn_little_nios2 (bfd_vma, disassemble_info*);
458 int print_insn_xtensa (bfd_vma, disassemble_info*);
459 int print_insn_riscv32 (bfd_vma, disassemble_info*);
460 int print_insn_riscv64 (bfd_vma, disassemble_info*);
461 int print_insn_rx(bfd_vma, disassemble_info *);
462
463 #ifndef ATTRIBUTE_UNUSED
464 #define ATTRIBUTE_UNUSED __attribute__((unused))
465 #endif
466
467 /* from libbfd */
468
469 bfd_vma bfd_getl64 (const bfd_byte *addr);
470 bfd_vma bfd_getl32 (const bfd_byte *addr);
471 bfd_vma bfd_getb32 (const bfd_byte *addr);
472 bfd_vma bfd_getl16 (const bfd_byte *addr);
473 bfd_vma bfd_getb16 (const bfd_byte *addr);
474 typedef bool bfd_boolean;
475
476 #endif /* DISAS_DIS_ASM_H */