meson: rename .inc.h files to .h.inc
[qemu.git] / include / exec / cpu-all.h
1 /*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_ALL_H
20 #define CPU_ALL_H
21
22 #include "exec/cpu-common.h"
23 #include "exec/memory.h"
24 #include "qemu/thread.h"
25 #include "hw/core/cpu.h"
26 #include "qemu/rcu.h"
27
28 #define EXCP_INTERRUPT 0x10000 /* async interruption */
29 #define EXCP_HLT 0x10001 /* hlt instruction reached */
30 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
31 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
32 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
33 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
34
35 /* some important defines:
36 *
37 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
38 * otherwise little endian.
39 *
40 * TARGET_WORDS_BIGENDIAN : same for target cpu
41 */
42
43 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
44 #define BSWAP_NEEDED
45 #endif
46
47 #ifdef BSWAP_NEEDED
48
49 static inline uint16_t tswap16(uint16_t s)
50 {
51 return bswap16(s);
52 }
53
54 static inline uint32_t tswap32(uint32_t s)
55 {
56 return bswap32(s);
57 }
58
59 static inline uint64_t tswap64(uint64_t s)
60 {
61 return bswap64(s);
62 }
63
64 static inline void tswap16s(uint16_t *s)
65 {
66 *s = bswap16(*s);
67 }
68
69 static inline void tswap32s(uint32_t *s)
70 {
71 *s = bswap32(*s);
72 }
73
74 static inline void tswap64s(uint64_t *s)
75 {
76 *s = bswap64(*s);
77 }
78
79 #else
80
81 static inline uint16_t tswap16(uint16_t s)
82 {
83 return s;
84 }
85
86 static inline uint32_t tswap32(uint32_t s)
87 {
88 return s;
89 }
90
91 static inline uint64_t tswap64(uint64_t s)
92 {
93 return s;
94 }
95
96 static inline void tswap16s(uint16_t *s)
97 {
98 }
99
100 static inline void tswap32s(uint32_t *s)
101 {
102 }
103
104 static inline void tswap64s(uint64_t *s)
105 {
106 }
107
108 #endif
109
110 #if TARGET_LONG_SIZE == 4
111 #define tswapl(s) tswap32(s)
112 #define tswapls(s) tswap32s((uint32_t *)(s))
113 #define bswaptls(s) bswap32s(s)
114 #else
115 #define tswapl(s) tswap64(s)
116 #define tswapls(s) tswap64s((uint64_t *)(s))
117 #define bswaptls(s) bswap64s(s)
118 #endif
119
120 /* Target-endianness CPU memory access functions. These fit into the
121 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
122 */
123 #if defined(TARGET_WORDS_BIGENDIAN)
124 #define lduw_p(p) lduw_be_p(p)
125 #define ldsw_p(p) ldsw_be_p(p)
126 #define ldl_p(p) ldl_be_p(p)
127 #define ldq_p(p) ldq_be_p(p)
128 #define ldfl_p(p) ldfl_be_p(p)
129 #define ldfq_p(p) ldfq_be_p(p)
130 #define stw_p(p, v) stw_be_p(p, v)
131 #define stl_p(p, v) stl_be_p(p, v)
132 #define stq_p(p, v) stq_be_p(p, v)
133 #define stfl_p(p, v) stfl_be_p(p, v)
134 #define stfq_p(p, v) stfq_be_p(p, v)
135 #define ldn_p(p, sz) ldn_be_p(p, sz)
136 #define stn_p(p, sz, v) stn_be_p(p, sz, v)
137 #else
138 #define lduw_p(p) lduw_le_p(p)
139 #define ldsw_p(p) ldsw_le_p(p)
140 #define ldl_p(p) ldl_le_p(p)
141 #define ldq_p(p) ldq_le_p(p)
142 #define ldfl_p(p) ldfl_le_p(p)
143 #define ldfq_p(p) ldfq_le_p(p)
144 #define stw_p(p, v) stw_le_p(p, v)
145 #define stl_p(p, v) stl_le_p(p, v)
146 #define stq_p(p, v) stq_le_p(p, v)
147 #define stfl_p(p, v) stfl_le_p(p, v)
148 #define stfq_p(p, v) stfq_le_p(p, v)
149 #define ldn_p(p, sz) ldn_le_p(p, sz)
150 #define stn_p(p, sz, v) stn_le_p(p, sz, v)
151 #endif
152
153 /* MMU memory access macros */
154
155 #if defined(CONFIG_USER_ONLY)
156 #include "exec/user/abitypes.h"
157
158 /* On some host systems the guest address space is reserved on the host.
159 * This allows the guest address space to be offset to a convenient location.
160 */
161 extern unsigned long guest_base;
162 extern bool have_guest_base;
163 extern unsigned long reserved_va;
164
165 /*
166 * Limit the guest addresses as best we can.
167 *
168 * When not using -R reserved_va, we cannot really limit the guest
169 * to less address space than the host. For 32-bit guests, this
170 * acts as a sanity check that we're not giving the guest an address
171 * that it cannot even represent. For 64-bit guests... the address
172 * might not be what the real kernel would give, but it is at least
173 * representable in the guest.
174 *
175 * TODO: Improve address allocation to avoid this problem, and to
176 * avoid setting bits at the top of guest addresses that might need
177 * to be used for tags.
178 */
179 #define GUEST_ADDR_MAX_ \
180 ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \
181 UINT32_MAX : ~0ul)
182 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : GUEST_ADDR_MAX_)
183
184 #else
185
186 #include "exec/hwaddr.h"
187
188 #define SUFFIX
189 #define ARG1 as
190 #define ARG1_DECL AddressSpace *as
191 #define TARGET_ENDIANNESS
192 #include "exec/memory_ldst.h.inc"
193
194 #define SUFFIX _cached_slow
195 #define ARG1 cache
196 #define ARG1_DECL MemoryRegionCache *cache
197 #define TARGET_ENDIANNESS
198 #include "exec/memory_ldst.h.inc"
199
200 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
201 {
202 address_space_stl_notdirty(as, addr, val,
203 MEMTXATTRS_UNSPECIFIED, NULL);
204 }
205
206 #define SUFFIX
207 #define ARG1 as
208 #define ARG1_DECL AddressSpace *as
209 #define TARGET_ENDIANNESS
210 #include "exec/memory_ldst_phys.h.inc"
211
212 /* Inline fast path for direct RAM access. */
213 #define ENDIANNESS
214 #include "exec/memory_ldst_cached.h.inc"
215
216 #define SUFFIX _cached
217 #define ARG1 cache
218 #define ARG1_DECL MemoryRegionCache *cache
219 #define TARGET_ENDIANNESS
220 #include "exec/memory_ldst_phys.h.inc"
221 #endif
222
223 /* page related stuff */
224
225 #ifdef TARGET_PAGE_BITS_VARY
226 typedef struct {
227 bool decided;
228 int bits;
229 target_long mask;
230 } TargetPageBits;
231 #if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
232 extern const TargetPageBits target_page;
233 #else
234 extern TargetPageBits target_page;
235 #endif
236 #ifdef CONFIG_DEBUG_TCG
237 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
238 #define TARGET_PAGE_MASK ({ assert(target_page.decided); target_page.mask; })
239 #else
240 #define TARGET_PAGE_BITS target_page.bits
241 #define TARGET_PAGE_MASK target_page.mask
242 #endif
243 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
244 #else
245 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
246 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
247 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
248 #endif
249
250 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
251
252 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
253 * when intptr_t is 32-bit and we are aligning a long long.
254 */
255 extern uintptr_t qemu_host_page_size;
256 extern intptr_t qemu_host_page_mask;
257
258 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
259 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size)
260
261 /* same as PROT_xxx */
262 #define PAGE_READ 0x0001
263 #define PAGE_WRITE 0x0002
264 #define PAGE_EXEC 0x0004
265 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
266 #define PAGE_VALID 0x0008
267 /* original state of the write flag (used when tracking self-modifying
268 code */
269 #define PAGE_WRITE_ORG 0x0010
270 /* Invalidate the TLB entry immediately, helpful for s390x
271 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */
272 #define PAGE_WRITE_INV 0x0040
273 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
274 /* FIXME: Code that sets/uses this is broken and needs to go away. */
275 #define PAGE_RESERVED 0x0020
276 #endif
277
278 #if defined(CONFIG_USER_ONLY)
279 void page_dump(FILE *f);
280
281 typedef int (*walk_memory_regions_fn)(void *, target_ulong,
282 target_ulong, unsigned long);
283 int walk_memory_regions(void *, walk_memory_regions_fn);
284
285 int page_get_flags(target_ulong address);
286 void page_set_flags(target_ulong start, target_ulong end, int flags);
287 int page_check_range(target_ulong start, target_ulong len, int flags);
288 #endif
289
290 CPUArchState *cpu_copy(CPUArchState *env);
291
292 /* Flags for use in ENV->INTERRUPT_PENDING.
293
294 The numbers assigned here are non-sequential in order to preserve
295 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
296 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
297 the vmstate dump. */
298
299 /* External hardware interrupt pending. This is typically used for
300 interrupts from devices. */
301 #define CPU_INTERRUPT_HARD 0x0002
302
303 /* Exit the current TB. This is typically used when some system-level device
304 makes some change to the memory mapping. E.g. the a20 line change. */
305 #define CPU_INTERRUPT_EXITTB 0x0004
306
307 /* Halt the CPU. */
308 #define CPU_INTERRUPT_HALT 0x0020
309
310 /* Debug event pending. */
311 #define CPU_INTERRUPT_DEBUG 0x0080
312
313 /* Reset signal. */
314 #define CPU_INTERRUPT_RESET 0x0400
315
316 /* Several target-specific external hardware interrupts. Each target/cpu.h
317 should define proper names based on these defines. */
318 #define CPU_INTERRUPT_TGT_EXT_0 0x0008
319 #define CPU_INTERRUPT_TGT_EXT_1 0x0010
320 #define CPU_INTERRUPT_TGT_EXT_2 0x0040
321 #define CPU_INTERRUPT_TGT_EXT_3 0x0200
322 #define CPU_INTERRUPT_TGT_EXT_4 0x1000
323
324 /* Several target-specific internal interrupts. These differ from the
325 preceding target-specific interrupts in that they are intended to
326 originate from within the cpu itself, typically in response to some
327 instruction being executed. These, therefore, are not masked while
328 single-stepping within the debugger. */
329 #define CPU_INTERRUPT_TGT_INT_0 0x0100
330 #define CPU_INTERRUPT_TGT_INT_1 0x0800
331 #define CPU_INTERRUPT_TGT_INT_2 0x2000
332
333 /* First unused bit: 0x4000. */
334
335 /* The set of all bits that should be masked when single-stepping. */
336 #define CPU_INTERRUPT_SSTEP_MASK \
337 (CPU_INTERRUPT_HARD \
338 | CPU_INTERRUPT_TGT_EXT_0 \
339 | CPU_INTERRUPT_TGT_EXT_1 \
340 | CPU_INTERRUPT_TGT_EXT_2 \
341 | CPU_INTERRUPT_TGT_EXT_3 \
342 | CPU_INTERRUPT_TGT_EXT_4)
343
344 #ifdef CONFIG_USER_ONLY
345
346 /*
347 * Allow some level of source compatibility with softmmu. We do not
348 * support any of the more exotic features, so only invalid pages may
349 * be signaled by probe_access_flags().
350 */
351 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
352 #define TLB_MMIO 0
353 #define TLB_WATCHPOINT 0
354
355 #else
356
357 /*
358 * Flags stored in the low bits of the TLB virtual address.
359 * These are defined so that fast path ram access is all zeros.
360 * The flags all must be between TARGET_PAGE_BITS and
361 * maximum address alignment bit.
362 *
363 * Use TARGET_PAGE_BITS_MIN so that these bits are constant
364 * when TARGET_PAGE_BITS_VARY is in effect.
365 */
366 /* Zero if TLB entry is valid. */
367 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
368 /* Set if TLB entry references a clean RAM page. The iotlb entry will
369 contain the page physical address. */
370 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
371 /* Set if TLB entry is an IO callback. */
372 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
373 /* Set if TLB entry contains a watchpoint. */
374 #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4))
375 /* Set if TLB entry requires byte swap. */
376 #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5))
377 /* Set if TLB entry writes ignored. */
378 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
379
380 /* Use this mask to check interception with an alignment mask
381 * in a TCG backend.
382 */
383 #define TLB_FLAGS_MASK \
384 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
385 | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE)
386
387 /**
388 * tlb_hit_page: return true if page aligned @addr is a hit against the
389 * TLB entry @tlb_addr
390 *
391 * @addr: virtual address to test (must be page aligned)
392 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
393 */
394 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr)
395 {
396 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
397 }
398
399 /**
400 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
401 *
402 * @addr: virtual address to test (need not be page aligned)
403 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
404 */
405 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr)
406 {
407 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
408 }
409
410 void dump_exec_info(void);
411 void dump_opcount_info(void);
412 #endif /* !CONFIG_USER_ONLY */
413
414 /* Returns: 0 on success, -1 on error */
415 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
416 void *ptr, target_ulong len, bool is_write);
417
418 int cpu_exec(CPUState *cpu);
419
420 /**
421 * cpu_set_cpustate_pointers(cpu)
422 * @cpu: The cpu object
423 *
424 * Set the generic pointers in CPUState into the outer object.
425 */
426 static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
427 {
428 cpu->parent_obj.env_ptr = &cpu->env;
429 cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr;
430 }
431
432 /**
433 * env_archcpu(env)
434 * @env: The architecture environment
435 *
436 * Return the ArchCPU associated with the environment.
437 */
438 static inline ArchCPU *env_archcpu(CPUArchState *env)
439 {
440 return container_of(env, ArchCPU, env);
441 }
442
443 /**
444 * env_cpu(env)
445 * @env: The architecture environment
446 *
447 * Return the CPUState associated with the environment.
448 */
449 static inline CPUState *env_cpu(CPUArchState *env)
450 {
451 return &env_archcpu(env)->parent_obj;
452 }
453
454 /**
455 * env_neg(env)
456 * @env: The architecture environment
457 *
458 * Return the CPUNegativeOffsetState associated with the environment.
459 */
460 static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
461 {
462 ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
463 return &arch_cpu->neg;
464 }
465
466 /**
467 * cpu_neg(cpu)
468 * @cpu: The generic CPUState
469 *
470 * Return the CPUNegativeOffsetState associated with the cpu.
471 */
472 static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu)
473 {
474 ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj);
475 return &arch_cpu->neg;
476 }
477
478 /**
479 * env_tlb(env)
480 * @env: The architecture environment
481 *
482 * Return the CPUTLB state associated with the environment.
483 */
484 static inline CPUTLB *env_tlb(CPUArchState *env)
485 {
486 return &env_neg(env)->tlb;
487 }
488
489 #endif /* CPU_ALL_H */