cpu: Move breakpoints field from CPU_COMMON to CPUState
[qemu.git] / include / exec / cpu-defs.h
1 /*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_DEFS_H
20 #define CPU_DEFS_H
21
22 #ifndef NEED_CPU_H
23 #error cpu.h included from common code
24 #endif
25
26 #include "config.h"
27 #include <inttypes.h>
28 #include "qemu/osdep.h"
29 #include "qemu/queue.h"
30 #ifndef CONFIG_USER_ONLY
31 #include "exec/hwaddr.h"
32 #endif
33
34 #ifndef TARGET_LONG_BITS
35 #error TARGET_LONG_BITS must be defined before including this header
36 #endif
37
38 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
39
40 /* target_ulong is the type of a virtual address */
41 #if TARGET_LONG_SIZE == 4
42 typedef int32_t target_long;
43 typedef uint32_t target_ulong;
44 #define TARGET_FMT_lx "%08x"
45 #define TARGET_FMT_ld "%d"
46 #define TARGET_FMT_lu "%u"
47 #elif TARGET_LONG_SIZE == 8
48 typedef int64_t target_long;
49 typedef uint64_t target_ulong;
50 #define TARGET_FMT_lx "%016" PRIx64
51 #define TARGET_FMT_ld "%" PRId64
52 #define TARGET_FMT_lu "%" PRIu64
53 #else
54 #error TARGET_LONG_SIZE undefined
55 #endif
56
57 #define EXCP_INTERRUPT 0x10000 /* async interruption */
58 #define EXCP_HLT 0x10001 /* hlt instruction reached */
59 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
60 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
61 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
62
63 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
64 addresses on the same page. The top bits are the same. This allows
65 TLB invalidation to quickly clear a subset of the hash table. */
66 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
67 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
68 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
69 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
70
71 #if !defined(CONFIG_USER_ONLY)
72 #define CPU_TLB_BITS 8
73 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
74
75 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
76 #define CPU_TLB_ENTRY_BITS 4
77 #else
78 #define CPU_TLB_ENTRY_BITS 5
79 #endif
80
81 typedef struct CPUTLBEntry {
82 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
83 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
84 go directly to ram.
85 bit 3 : indicates that the entry is invalid
86 bit 2..0 : zero
87 */
88 target_ulong addr_read;
89 target_ulong addr_write;
90 target_ulong addr_code;
91 /* Addend to virtual address to get host address. IO accesses
92 use the corresponding iotlb value. */
93 uintptr_t addend;
94 /* padding to get a power of two size */
95 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
96 (sizeof(target_ulong) * 3 +
97 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
98 sizeof(uintptr_t))];
99 } CPUTLBEntry;
100
101 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
102
103 #define CPU_COMMON_TLB \
104 /* The meaning of the MMU modes is defined in the target code. */ \
105 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
106 hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
107 target_ulong tlb_flush_addr; \
108 target_ulong tlb_flush_mask;
109
110 #else
111
112 #define CPU_COMMON_TLB
113
114 #endif
115
116
117 #define CPU_TEMP_BUF_NLONGS 128
118 #define CPU_COMMON \
119 /* soft mmu support */ \
120 CPU_COMMON_TLB \
121
122 #endif