Merge tag 'pull-la-20220814' of https://gitlab.com/rth7680/qemu into staging
[qemu.git] / include / exec / cpu-defs.h
1 /*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_DEFS_H
20 #define CPU_DEFS_H
21
22 #ifndef NEED_CPU_H
23 #error cpu.h included from common code
24 #endif
25
26 #include "qemu/host-utils.h"
27 #include "qemu/thread.h"
28 #ifndef CONFIG_USER_ONLY
29 #include "exec/hwaddr.h"
30 #endif
31 #include "exec/memattrs.h"
32 #include "hw/core/cpu.h"
33
34 #include "cpu-param.h"
35
36 #ifndef TARGET_LONG_BITS
37 # error TARGET_LONG_BITS must be defined in cpu-param.h
38 #endif
39 #ifndef NB_MMU_MODES
40 # error NB_MMU_MODES must be defined in cpu-param.h
41 #endif
42 #ifndef TARGET_PHYS_ADDR_SPACE_BITS
43 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
44 #endif
45 #ifndef TARGET_VIRT_ADDR_SPACE_BITS
46 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h
47 #endif
48 #ifndef TARGET_PAGE_BITS
49 # ifdef TARGET_PAGE_BITS_VARY
50 # ifndef TARGET_PAGE_BITS_MIN
51 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
52 # endif
53 # else
54 # error TARGET_PAGE_BITS must be defined in cpu-param.h
55 # endif
56 #endif
57
58 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
59
60 /* target_ulong is the type of a virtual address */
61 #if TARGET_LONG_SIZE == 4
62 typedef int32_t target_long;
63 typedef uint32_t target_ulong;
64 #define TARGET_FMT_lx "%08x"
65 #define TARGET_FMT_ld "%d"
66 #define TARGET_FMT_lu "%u"
67 #elif TARGET_LONG_SIZE == 8
68 typedef int64_t target_long;
69 typedef uint64_t target_ulong;
70 #define TARGET_FMT_lx "%016" PRIx64
71 #define TARGET_FMT_ld "%" PRId64
72 #define TARGET_FMT_lu "%" PRIu64
73 #else
74 #error TARGET_LONG_SIZE undefined
75 #endif
76
77 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
78
79 /* use a fully associative victim tlb of 8 entries */
80 #define CPU_VTLB_SIZE 8
81
82 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
83 #define CPU_TLB_ENTRY_BITS 4
84 #else
85 #define CPU_TLB_ENTRY_BITS 5
86 #endif
87
88 #define CPU_TLB_DYN_MIN_BITS 6
89 #define CPU_TLB_DYN_DEFAULT_BITS 8
90
91 # if HOST_LONG_BITS == 32
92 /* Make sure we do not require a double-word shift for the TLB load */
93 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
94 # else /* HOST_LONG_BITS == 64 */
95 /*
96 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
97 * 2**34 == 16G of address space. This is roughly what one would expect a
98 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
99 * Skylake's Level-2 STLB has 16 1G entries.
100 * Also, make sure we do not size the TLB past the guest's address space.
101 */
102 # ifdef TARGET_PAGE_BITS_VARY
103 # define CPU_TLB_DYN_MAX_BITS \
104 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
105 # else
106 # define CPU_TLB_DYN_MAX_BITS \
107 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
108 # endif
109 # endif
110
111 typedef struct CPUTLBEntry {
112 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
113 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
114 go directly to ram.
115 bit 3 : indicates that the entry is invalid
116 bit 2..0 : zero
117 */
118 union {
119 struct {
120 target_ulong addr_read;
121 target_ulong addr_write;
122 target_ulong addr_code;
123 /* Addend to virtual address to get host address. IO accesses
124 use the corresponding iotlb value. */
125 uintptr_t addend;
126 };
127 /* padding to get a power of two size */
128 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS];
129 };
130 } CPUTLBEntry;
131
132 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
133
134 /* The IOTLB is not accessed directly inline by generated TCG code,
135 * so the CPUIOTLBEntry layout is not as critical as that of the
136 * CPUTLBEntry. (This is also why we don't want to combine the two
137 * structs into one.)
138 */
139 typedef struct CPUIOTLBEntry {
140 /*
141 * @addr contains:
142 * - in the lower TARGET_PAGE_BITS, a physical section number
143 * - with the lower TARGET_PAGE_BITS masked off, an offset which
144 * must be added to the virtual address to obtain:
145 * + the ram_addr_t of the target RAM (if the physical section
146 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
147 * + the offset within the target MemoryRegion (otherwise)
148 */
149 hwaddr addr;
150 MemTxAttrs attrs;
151 } CPUIOTLBEntry;
152
153 /*
154 * Data elements that are per MMU mode, minus the bits accessed by
155 * the TCG fast path.
156 */
157 typedef struct CPUTLBDesc {
158 /*
159 * Describe a region covering all of the large pages allocated
160 * into the tlb. When any page within this region is flushed,
161 * we must flush the entire tlb. The region is matched if
162 * (addr & large_page_mask) == large_page_addr.
163 */
164 target_ulong large_page_addr;
165 target_ulong large_page_mask;
166 /* host time (in ns) at the beginning of the time window */
167 int64_t window_begin_ns;
168 /* maximum number of entries observed in the window */
169 size_t window_max_entries;
170 size_t n_used_entries;
171 /* The next index to use in the tlb victim table. */
172 size_t vindex;
173 /* The tlb victim table, in two parts. */
174 CPUTLBEntry vtable[CPU_VTLB_SIZE];
175 CPUIOTLBEntry viotlb[CPU_VTLB_SIZE];
176 /* The iotlb. */
177 CPUIOTLBEntry *iotlb;
178 } CPUTLBDesc;
179
180 /*
181 * Data elements that are per MMU mode, accessed by the fast path.
182 * The structure is aligned to aid loading the pair with one insn.
183 */
184 typedef struct CPUTLBDescFast {
185 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
186 uintptr_t mask;
187 /* The array of tlb entries itself. */
188 CPUTLBEntry *table;
189 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *));
190
191 /*
192 * Data elements that are shared between all MMU modes.
193 */
194 typedef struct CPUTLBCommon {
195 /* Serialize updates to f.table and d.vtable, and others as noted. */
196 QemuSpin lock;
197 /*
198 * Within dirty, for each bit N, modifications have been made to
199 * mmu_idx N since the last time that mmu_idx was flushed.
200 * Protected by tlb_c.lock.
201 */
202 uint16_t dirty;
203 /*
204 * Statistics. These are not lock protected, but are read and
205 * written atomically. This allows the monitor to print a snapshot
206 * of the stats without interfering with the cpu.
207 */
208 size_t full_flush_count;
209 size_t part_flush_count;
210 size_t elide_flush_count;
211 } CPUTLBCommon;
212
213 /*
214 * The entire softmmu tlb, for all MMU modes.
215 * The meaning of each of the MMU modes is defined in the target code.
216 * Since this is placed within CPUNegativeOffsetState, the smallest
217 * negative offsets are at the end of the struct.
218 */
219
220 typedef struct CPUTLB {
221 CPUTLBCommon c;
222 CPUTLBDesc d[NB_MMU_MODES];
223 CPUTLBDescFast f[NB_MMU_MODES];
224 } CPUTLB;
225
226 /* This will be used by TCG backends to compute offsets. */
227 #define TLB_MASK_TABLE_OFS(IDX) \
228 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env))
229
230 #else
231
232 typedef struct CPUTLB { } CPUTLB;
233
234 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
235
236 /*
237 * This structure must be placed in ArchCPU immediately
238 * before CPUArchState, as a field named "neg".
239 */
240 typedef struct CPUNegativeOffsetState {
241 CPUTLB tlb;
242 IcountDecr icount_decr;
243 } CPUNegativeOffsetState;
244
245 #endif