cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / include / exec / exec-all.h
1 /*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef _EXEC_ALL_H_
21 #define _EXEC_ALL_H_
22
23 #include "qemu-common.h"
24
25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
26 #define DEBUG_DISAS
27
28 /* Page tracking code uses ram addresses in system mode, and virtual
29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
30 type. */
31 #if defined(CONFIG_USER_ONLY)
32 typedef abi_ulong tb_page_addr_t;
33 #else
34 typedef ram_addr_t tb_page_addr_t;
35 #endif
36
37 /* is_jmp field values */
38 #define DISAS_NEXT 0 /* next instruction can be analyzed */
39 #define DISAS_JUMP 1 /* only pc was modified dynamically */
40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
42
43 struct TranslationBlock;
44 typedef struct TranslationBlock TranslationBlock;
45
46 /* XXX: make safe guess about sizes */
47 #define MAX_OP_PER_INSTR 208
48
49 #if HOST_LONG_BITS == 32
50 #define MAX_OPC_PARAM_PER_ARG 2
51 #else
52 #define MAX_OPC_PARAM_PER_ARG 1
53 #endif
54 #define MAX_OPC_PARAM_IARGS 5
55 #define MAX_OPC_PARAM_OARGS 1
56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
57
58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
59 * and up to 4 + N parameters on 64-bit archs
60 * (N = number of input arguments + output arguments). */
61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
62 #define OPC_BUF_SIZE 640
63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
64
65 /* Maximum size a TCG op can expand to. This is complicated because a
66 single op may require several host instructions and register reloads.
67 For now take a wild guess at 192 bytes, which should allow at least
68 a couple of fixup instructions per argument. */
69 #define TCG_MAX_OP_SIZE 192
70
71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
72
73 #include "qemu/log.h"
74
75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
78 int pc_pos);
79
80 void cpu_gen_init(void);
81 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
82 int *gen_code_size_ptr);
83 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
84 void page_size_init(void);
85
86 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
87 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
88 TranslationBlock *tb_gen_code(CPUState *cpu,
89 target_ulong pc, target_ulong cs_base, int flags,
90 int cflags);
91 void cpu_exec_init(CPUArchState *env);
92 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
93 int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
94 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
95 int is_cpu_write_access);
96 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
97 int is_cpu_write_access);
98 #if !defined(CONFIG_USER_ONLY)
99 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
100 /* cputlb.c */
101 void tlb_flush_page(CPUState *cpu, target_ulong addr);
102 void tlb_flush(CPUState *cpu, int flush_global);
103 void tlb_set_page(CPUArchState *env, target_ulong vaddr,
104 hwaddr paddr, int prot,
105 int mmu_idx, target_ulong size);
106 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
107 #else
108 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
109 {
110 }
111
112 static inline void tlb_flush(CPUState *cpu, int flush_global)
113 {
114 }
115 #endif
116
117 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
118
119 #define CODE_GEN_PHYS_HASH_BITS 15
120 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
121
122 /* estimated block size for TB allocation */
123 /* XXX: use a per code average code fragment size and modulate it
124 according to the host CPU */
125 #if defined(CONFIG_SOFTMMU)
126 #define CODE_GEN_AVG_BLOCK_SIZE 128
127 #else
128 #define CODE_GEN_AVG_BLOCK_SIZE 64
129 #endif
130
131 #if defined(__arm__) || defined(_ARCH_PPC) \
132 || defined(__x86_64__) || defined(__i386__) \
133 || defined(__sparc__) || defined(__aarch64__) \
134 || defined(CONFIG_TCG_INTERPRETER)
135 #define USE_DIRECT_JUMP
136 #endif
137
138 struct TranslationBlock {
139 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
140 target_ulong cs_base; /* CS base for this block */
141 uint64_t flags; /* flags defining in which context the code was generated */
142 uint16_t size; /* size of target code for this block (1 <=
143 size <= TARGET_PAGE_SIZE) */
144 uint16_t cflags; /* compile flags */
145 #define CF_COUNT_MASK 0x7fff
146 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
147
148 uint8_t *tc_ptr; /* pointer to the translated code */
149 /* next matching tb for physical address. */
150 struct TranslationBlock *phys_hash_next;
151 /* first and second physical page containing code. The lower bit
152 of the pointer tells the index in page_next[] */
153 struct TranslationBlock *page_next[2];
154 tb_page_addr_t page_addr[2];
155
156 /* the following data are used to directly call another TB from
157 the code of this one. */
158 uint16_t tb_next_offset[2]; /* offset of original jump target */
159 #ifdef USE_DIRECT_JUMP
160 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
161 #else
162 uintptr_t tb_next[2]; /* address of jump generated code */
163 #endif
164 /* list of TBs jumping to this one. This is a circular list using
165 the two least significant bits of the pointers to tell what is
166 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
167 jmp_first */
168 struct TranslationBlock *jmp_next[2];
169 struct TranslationBlock *jmp_first;
170 uint32_t icount;
171 };
172
173 #include "exec/spinlock.h"
174
175 typedef struct TBContext TBContext;
176
177 struct TBContext {
178
179 TranslationBlock *tbs;
180 TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
181 int nb_tbs;
182 /* any access to the tbs or the page table must use this lock */
183 spinlock_t tb_lock;
184
185 /* statistics */
186 int tb_flush_count;
187 int tb_phys_invalidate_count;
188
189 int tb_invalidated_flag;
190 };
191
192 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
193 {
194 target_ulong tmp;
195 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
196 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
197 }
198
199 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
200 {
201 target_ulong tmp;
202 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
203 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
204 | (tmp & TB_JMP_ADDR_MASK));
205 }
206
207 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
208 {
209 return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
210 }
211
212 void tb_free(TranslationBlock *tb);
213 void tb_flush(CPUArchState *env);
214 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
215
216 #if defined(USE_DIRECT_JUMP)
217
218 #if defined(CONFIG_TCG_INTERPRETER)
219 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
220 {
221 /* patch the branch destination */
222 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
223 /* no need to flush icache explicitly */
224 }
225 #elif defined(_ARCH_PPC)
226 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
227 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
228 #elif defined(__i386__) || defined(__x86_64__)
229 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
230 {
231 /* patch the branch destination */
232 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
233 /* no need to flush icache explicitly */
234 }
235 #elif defined(__aarch64__)
236 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
237 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
238 #elif defined(__arm__)
239 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
240 {
241 #if !QEMU_GNUC_PREREQ(4, 1)
242 register unsigned long _beg __asm ("a1");
243 register unsigned long _end __asm ("a2");
244 register unsigned long _flg __asm ("a3");
245 #endif
246
247 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
248 *(uint32_t *)jmp_addr =
249 (*(uint32_t *)jmp_addr & ~0xffffff)
250 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
251
252 #if QEMU_GNUC_PREREQ(4, 1)
253 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
254 #else
255 /* flush icache */
256 _beg = jmp_addr;
257 _end = jmp_addr + 4;
258 _flg = 0;
259 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
260 #endif
261 }
262 #elif defined(__sparc__)
263 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
264 #else
265 #error tb_set_jmp_target1 is missing
266 #endif
267
268 static inline void tb_set_jmp_target(TranslationBlock *tb,
269 int n, uintptr_t addr)
270 {
271 uint16_t offset = tb->tb_jmp_offset[n];
272 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
273 }
274
275 #else
276
277 /* set the jump target */
278 static inline void tb_set_jmp_target(TranslationBlock *tb,
279 int n, uintptr_t addr)
280 {
281 tb->tb_next[n] = addr;
282 }
283
284 #endif
285
286 static inline void tb_add_jump(TranslationBlock *tb, int n,
287 TranslationBlock *tb_next)
288 {
289 /* NOTE: this test is only needed for thread safety */
290 if (!tb->jmp_next[n]) {
291 /* patch the native jump address */
292 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
293
294 /* add in TB jmp circular list */
295 tb->jmp_next[n] = tb_next->jmp_first;
296 tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
297 }
298 }
299
300 /* GETRA is the true target of the return instruction that we'll execute,
301 defined here for simplicity of defining the follow-up macros. */
302 #if defined(CONFIG_TCG_INTERPRETER)
303 extern uintptr_t tci_tb_ptr;
304 # define GETRA() tci_tb_ptr
305 #else
306 # define GETRA() \
307 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
308 #endif
309
310 /* The true return address will often point to a host insn that is part of
311 the next translated guest insn. Adjust the address backward to point to
312 the middle of the call insn. Subtracting one would do the job except for
313 several compressed mode architectures (arm, mips) which set the low bit
314 to indicate the compressed mode; subtracting two works around that. It
315 is also the case that there are no host isas that contain a call insn
316 smaller than 4 bytes, so we don't worry about special-casing this. */
317 #if defined(CONFIG_TCG_INTERPRETER)
318 # define GETPC_ADJ 0
319 #else
320 # define GETPC_ADJ 2
321 #endif
322
323 #define GETPC() (GETRA() - GETPC_ADJ)
324
325 #if !defined(CONFIG_USER_ONLY)
326
327 void phys_mem_set_alloc(void *(*alloc)(size_t));
328
329 struct MemoryRegion *iotlb_to_region(AddressSpace *as, hwaddr index);
330 bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
331 uint64_t *pvalue, unsigned size);
332 bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
333 uint64_t value, unsigned size);
334
335 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
336 uintptr_t retaddr);
337
338 uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
339 uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
340 uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
341 uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
342
343 #define ACCESS_TYPE (NB_MMU_MODES + 1)
344 #define MEMSUFFIX _code
345
346 #define DATA_SIZE 1
347 #include "exec/softmmu_header.h"
348
349 #define DATA_SIZE 2
350 #include "exec/softmmu_header.h"
351
352 #define DATA_SIZE 4
353 #include "exec/softmmu_header.h"
354
355 #define DATA_SIZE 8
356 #include "exec/softmmu_header.h"
357
358 #undef ACCESS_TYPE
359 #undef MEMSUFFIX
360
361 #endif
362
363 #if defined(CONFIG_USER_ONLY)
364 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
365 {
366 return addr;
367 }
368 #else
369 /* cputlb.c */
370 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
371 #endif
372
373 typedef void (CPUDebugExcpHandler)(CPUArchState *env);
374
375 void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
376
377 /* vl.c */
378 extern int singlestep;
379
380 /* cpu-exec.c */
381 extern volatile sig_atomic_t exit_request;
382
383 /**
384 * cpu_can_do_io:
385 * @cpu: The CPU for which to check IO.
386 *
387 * Deterministic execution requires that IO only be performed on the last
388 * instruction of a TB so that interrupts take effect immediately.
389 *
390 * Returns: %true if memory-mapped IO is safe, %false otherwise.
391 */
392 static inline bool cpu_can_do_io(CPUState *cpu)
393 {
394 if (!use_icount) {
395 return true;
396 }
397 /* If not executing code then assume we are ok. */
398 if (cpu->current_tb == NULL) {
399 return true;
400 }
401 return cpu->can_do_io != 0;
402 }
403
404 #endif