Add ENET device to i.MX6 SOC.
[qemu.git] / include / exec / exec-all.h
1 /*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef _EXEC_ALL_H_
21 #define _EXEC_ALL_H_
22
23 #include "qemu-common.h"
24 #include "exec/tb-context.h"
25
26 /* allow to see translation results - the slowdown should be negligible, so we leave it */
27 #define DEBUG_DISAS
28
29 /* Page tracking code uses ram addresses in system mode, and virtual
30 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
31 type. */
32 #if defined(CONFIG_USER_ONLY)
33 typedef abi_ulong tb_page_addr_t;
34 #else
35 typedef ram_addr_t tb_page_addr_t;
36 #endif
37
38 /* is_jmp field values */
39 #define DISAS_NEXT 0 /* next instruction can be analyzed */
40 #define DISAS_JUMP 1 /* only pc was modified dynamically */
41 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
42 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
43
44 #include "qemu/log.h"
45
46 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
47 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
48 target_ulong *data);
49
50 void cpu_gen_init(void);
51 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
52
53 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
54 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
55 TranslationBlock *tb_gen_code(CPUState *cpu,
56 target_ulong pc, target_ulong cs_base,
57 uint32_t flags,
58 int cflags);
59 void cpu_exec_init(CPUState *cpu, Error **errp);
60 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
61 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
62
63 #if !defined(CONFIG_USER_ONLY)
64 void cpu_reloading_memory_map(void);
65 /**
66 * cpu_address_space_init:
67 * @cpu: CPU to add this address space to
68 * @as: address space to add
69 * @asidx: integer index of this address space
70 *
71 * Add the specified address space to the CPU's cpu_ases list.
72 * The address space added with @asidx 0 is the one used for the
73 * convenience pointer cpu->as.
74 * The target-specific code which registers ASes is responsible
75 * for defining what semantics address space 0, 1, 2, etc have.
76 *
77 * Before the first call to this function, the caller must set
78 * cpu->num_ases to the total number of address spaces it needs
79 * to support.
80 *
81 * Note that with KVM only one address space is supported.
82 */
83 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx);
84 /* cputlb.c */
85 /**
86 * tlb_flush_page:
87 * @cpu: CPU whose TLB should be flushed
88 * @addr: virtual address of page to be flushed
89 *
90 * Flush one page from the TLB of the specified CPU, for all
91 * MMU indexes.
92 */
93 void tlb_flush_page(CPUState *cpu, target_ulong addr);
94 /**
95 * tlb_flush:
96 * @cpu: CPU whose TLB should be flushed
97 * @flush_global: ignored
98 *
99 * Flush the entire TLB for the specified CPU.
100 * The flush_global flag is in theory an indicator of whether the whole
101 * TLB should be flushed, or only those entries not marked global.
102 * In practice QEMU does not implement any global/not global flag for
103 * TLB entries, and the argument is ignored.
104 */
105 void tlb_flush(CPUState *cpu, int flush_global);
106 /**
107 * tlb_flush_page_by_mmuidx:
108 * @cpu: CPU whose TLB should be flushed
109 * @addr: virtual address of page to be flushed
110 * @...: list of MMU indexes to flush, terminated by a negative value
111 *
112 * Flush one page from the TLB of the specified CPU, for the specified
113 * MMU indexes.
114 */
115 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...);
116 /**
117 * tlb_flush_by_mmuidx:
118 * @cpu: CPU whose TLB should be flushed
119 * @...: list of MMU indexes to flush, terminated by a negative value
120 *
121 * Flush all entries from the TLB of the specified CPU, for the specified
122 * MMU indexes.
123 */
124 void tlb_flush_by_mmuidx(CPUState *cpu, ...);
125 /**
126 * tlb_set_page_with_attrs:
127 * @cpu: CPU to add this TLB entry for
128 * @vaddr: virtual address of page to add entry for
129 * @paddr: physical address of the page
130 * @attrs: memory transaction attributes
131 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
132 * @mmu_idx: MMU index to insert TLB entry for
133 * @size: size of the page in bytes
134 *
135 * Add an entry to this CPU's TLB (a mapping from virtual address
136 * @vaddr to physical address @paddr) with the specified memory
137 * transaction attributes. This is generally called by the target CPU
138 * specific code after it has been called through the tlb_fill()
139 * entry point and performed a successful page table walk to find
140 * the physical address and attributes for the virtual address
141 * which provoked the TLB miss.
142 *
143 * At most one entry for a given virtual address is permitted. Only a
144 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
145 * used by tlb_flush_page.
146 */
147 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
148 hwaddr paddr, MemTxAttrs attrs,
149 int prot, int mmu_idx, target_ulong size);
150 /* tlb_set_page:
151 *
152 * This function is equivalent to calling tlb_set_page_with_attrs()
153 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
154 * as a convenience for CPUs which don't use memory transaction attributes.
155 */
156 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
157 hwaddr paddr, int prot,
158 int mmu_idx, target_ulong size);
159 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
160 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
161 uintptr_t retaddr);
162 #else
163 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
164 {
165 }
166
167 static inline void tlb_flush(CPUState *cpu, int flush_global)
168 {
169 }
170
171 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
172 target_ulong addr, ...)
173 {
174 }
175
176 static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...)
177 {
178 }
179 #endif
180
181 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
182
183 /* Estimated block size for TB allocation. */
184 /* ??? The following is based on a 2015 survey of x86_64 host output.
185 Better would seem to be some sort of dynamically sized TB array,
186 adapting to the block sizes actually being produced. */
187 #if defined(CONFIG_SOFTMMU)
188 #define CODE_GEN_AVG_BLOCK_SIZE 400
189 #else
190 #define CODE_GEN_AVG_BLOCK_SIZE 150
191 #endif
192
193 #if defined(__arm__) || defined(_ARCH_PPC) \
194 || defined(__x86_64__) || defined(__i386__) \
195 || defined(__sparc__) || defined(__aarch64__) \
196 || defined(__s390x__) || defined(__mips__) \
197 || defined(CONFIG_TCG_INTERPRETER)
198 /* NOTE: Direct jump patching must be atomic to be thread-safe. */
199 #define USE_DIRECT_JUMP
200 #endif
201
202 struct TranslationBlock {
203 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
204 target_ulong cs_base; /* CS base for this block */
205 uint32_t flags; /* flags defining in which context the code was generated */
206 uint16_t size; /* size of target code for this block (1 <=
207 size <= TARGET_PAGE_SIZE) */
208 uint16_t icount;
209 uint32_t cflags; /* compile flags */
210 #define CF_COUNT_MASK 0x7fff
211 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
212 #define CF_NOCACHE 0x10000 /* To be freed after execution */
213 #define CF_USE_ICOUNT 0x20000
214 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */
215
216 void *tc_ptr; /* pointer to the translated code */
217 uint8_t *tc_search; /* pointer to search data */
218 /* next matching tb for physical address. */
219 struct TranslationBlock *phys_hash_next;
220 /* original tb when cflags has CF_NOCACHE */
221 struct TranslationBlock *orig_tb;
222 /* first and second physical page containing code. The lower bit
223 of the pointer tells the index in page_next[] */
224 struct TranslationBlock *page_next[2];
225 tb_page_addr_t page_addr[2];
226
227 /* The following data are used to directly call another TB from
228 * the code of this one. This can be done either by emitting direct or
229 * indirect native jump instructions. These jumps are reset so that the TB
230 * just continue its execution. The TB can be linked to another one by
231 * setting one of the jump targets (or patching the jump instruction). Only
232 * two of such jumps are supported.
233 */
234 uint16_t jmp_reset_offset[2]; /* offset of original jump target */
235 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
236 #ifdef USE_DIRECT_JUMP
237 uint16_t jmp_insn_offset[2]; /* offset of native jump instruction */
238 #else
239 uintptr_t jmp_target_addr[2]; /* target address for indirect jump */
240 #endif
241 /* Each TB has an assosiated circular list of TBs jumping to this one.
242 * jmp_list_first points to the first TB jumping to this one.
243 * jmp_list_next is used to point to the next TB in a list.
244 * Since each TB can have two jumps, it can participate in two lists.
245 * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a
246 * TranslationBlock structure, but the two least significant bits of
247 * them are used to encode which data field of the pointed TB should
248 * be used to traverse the list further from that TB:
249 * 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first.
250 * In other words, 0/1 tells which jump is used in the pointed TB,
251 * and 2 means that this is a pointer back to the target TB of this list.
252 */
253 uintptr_t jmp_list_next[2];
254 uintptr_t jmp_list_first;
255 };
256
257 void tb_free(TranslationBlock *tb);
258 void tb_flush(CPUState *cpu);
259 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
260
261 #if defined(USE_DIRECT_JUMP)
262
263 #if defined(CONFIG_TCG_INTERPRETER)
264 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
265 {
266 /* patch the branch destination */
267 atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
268 /* no need to flush icache explicitly */
269 }
270 #elif defined(_ARCH_PPC)
271 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
272 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
273 #elif defined(__i386__) || defined(__x86_64__)
274 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
275 {
276 /* patch the branch destination */
277 atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
278 /* no need to flush icache explicitly */
279 }
280 #elif defined(__s390x__)
281 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
282 {
283 /* patch the branch destination */
284 intptr_t disp = addr - (jmp_addr - 2);
285 atomic_set((int32_t *)jmp_addr, disp / 2);
286 /* no need to flush icache explicitly */
287 }
288 #elif defined(__aarch64__)
289 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
290 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
291 #elif defined(__arm__)
292 void arm_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
293 #define tb_set_jmp_target1 arm_tb_set_jmp_target
294 #elif defined(__sparc__) || defined(__mips__)
295 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
296 #else
297 #error tb_set_jmp_target1 is missing
298 #endif
299
300 static inline void tb_set_jmp_target(TranslationBlock *tb,
301 int n, uintptr_t addr)
302 {
303 uint16_t offset = tb->jmp_insn_offset[n];
304 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
305 }
306
307 #else
308
309 /* set the jump target */
310 static inline void tb_set_jmp_target(TranslationBlock *tb,
311 int n, uintptr_t addr)
312 {
313 tb->jmp_target_addr[n] = addr;
314 }
315
316 #endif
317
318 static inline void tb_add_jump(TranslationBlock *tb, int n,
319 TranslationBlock *tb_next)
320 {
321 if (tb->jmp_list_next[n]) {
322 /* Another thread has already done this while we were
323 * outside of the lock; nothing to do in this case */
324 return;
325 }
326 qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
327 "Linking TBs %p [" TARGET_FMT_lx
328 "] index %d -> %p [" TARGET_FMT_lx "]\n",
329 tb->tc_ptr, tb->pc, n,
330 tb_next->tc_ptr, tb_next->pc);
331
332 /* patch the native jump address */
333 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
334
335 /* add in TB jmp circular list */
336 tb->jmp_list_next[n] = tb_next->jmp_list_first;
337 tb_next->jmp_list_first = (uintptr_t)tb | n;
338 }
339
340 /* GETRA is the true target of the return instruction that we'll execute,
341 defined here for simplicity of defining the follow-up macros. */
342 #if defined(CONFIG_TCG_INTERPRETER)
343 extern uintptr_t tci_tb_ptr;
344 # define GETRA() tci_tb_ptr
345 #else
346 # define GETRA() \
347 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
348 #endif
349
350 /* The true return address will often point to a host insn that is part of
351 the next translated guest insn. Adjust the address backward to point to
352 the middle of the call insn. Subtracting one would do the job except for
353 several compressed mode architectures (arm, mips) which set the low bit
354 to indicate the compressed mode; subtracting two works around that. It
355 is also the case that there are no host isas that contain a call insn
356 smaller than 4 bytes, so we don't worry about special-casing this. */
357 #define GETPC_ADJ 2
358
359 #define GETPC() (GETRA() - GETPC_ADJ)
360
361 #if !defined(CONFIG_USER_ONLY)
362
363 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
364 hwaddr index, MemTxAttrs attrs);
365
366 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
367 uintptr_t retaddr);
368
369 #endif
370
371 #if defined(CONFIG_USER_ONLY)
372 void mmap_lock(void);
373 void mmap_unlock(void);
374
375 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
376 {
377 return addr;
378 }
379 #else
380 static inline void mmap_lock(void) {}
381 static inline void mmap_unlock(void) {}
382
383 /* cputlb.c */
384 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
385
386 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
387 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
388
389 /* exec.c */
390 void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
391
392 MemoryRegionSection *
393 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
394 hwaddr *xlat, hwaddr *plen);
395 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
396 MemoryRegionSection *section,
397 target_ulong vaddr,
398 hwaddr paddr, hwaddr xlat,
399 int prot,
400 target_ulong *address);
401 bool memory_region_is_unassigned(MemoryRegion *mr);
402
403 #endif
404
405 /* vl.c */
406 extern int singlestep;
407
408 /* cpu-exec.c, accessed with atomic_mb_read/atomic_mb_set */
409 extern CPUState *tcg_current_cpu;
410 extern bool exit_request;
411
412 #endif