Merge tag 'trivial-branch-for-7.1-pull-request' of https://gitlab.com/laurent_vivier...
[qemu.git] / include / hw / acpi / tpm.h
1 /*
2 * tpm.h - TPM ACPI definitions
3 *
4 * Copyright (C) 2014 IBM Corporation
5 *
6 * Authors:
7 * Stefan Berger <stefanb@us.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 *
12 * Implementation of the TIS interface according to specs found at
13 * http://www.trustedcomputinggroup.org
14 *
15 */
16 #ifndef HW_ACPI_TPM_H
17 #define HW_ACPI_TPM_H
18
19 #include "qemu/units.h"
20 #include "hw/registerfields.h"
21 #include "hw/acpi/aml-build.h"
22 #include "sysemu/tpm.h"
23
24 #ifdef CONFIG_TPM
25
26 #define TPM_TIS_ADDR_BASE 0xFED40000
27 #define TPM_TIS_ADDR_SIZE 0x5000
28
29 #define TPM_TIS_IRQ 5
30
31 #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */
32 #define TPM_TIS_LOCALITY_SHIFT 12
33
34 /* tis registers */
35 #define TPM_TIS_REG_ACCESS 0x00
36 #define TPM_TIS_REG_INT_ENABLE 0x08
37 #define TPM_TIS_REG_INT_VECTOR 0x0c
38 #define TPM_TIS_REG_INT_STATUS 0x10
39 #define TPM_TIS_REG_INTF_CAPABILITY 0x14
40 #define TPM_TIS_REG_STS 0x18
41 #define TPM_TIS_REG_DATA_FIFO 0x24
42 #define TPM_TIS_REG_INTERFACE_ID 0x30
43 #define TPM_TIS_REG_DATA_XFIFO 0x80
44 #define TPM_TIS_REG_DATA_XFIFO_END 0xbc
45 #define TPM_TIS_REG_DID_VID 0xf00
46 #define TPM_TIS_REG_RID 0xf04
47
48 /* vendor-specific registers */
49 #define TPM_TIS_REG_DEBUG 0xf90
50
51 #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */
52 #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */
53 #define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */
54 #define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */
55 #define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */
56
57 #define TPM_TIS_STS_VALID (1 << 7)
58 #define TPM_TIS_STS_COMMAND_READY (1 << 6)
59 #define TPM_TIS_STS_TPM_GO (1 << 5)
60 #define TPM_TIS_STS_DATA_AVAILABLE (1 << 4)
61 #define TPM_TIS_STS_EXPECT (1 << 3)
62 #define TPM_TIS_STS_SELFTEST_DONE (1 << 2)
63 #define TPM_TIS_STS_RESPONSE_RETRY (1 << 1)
64
65 #define TPM_TIS_BURST_COUNT_SHIFT 8
66 #define TPM_TIS_BURST_COUNT(X) \
67 ((X) << TPM_TIS_BURST_COUNT_SHIFT)
68
69 #define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7)
70 #define TPM_TIS_ACCESS_ACTIVE_LOCALITY (1 << 5)
71 #define TPM_TIS_ACCESS_BEEN_SEIZED (1 << 4)
72 #define TPM_TIS_ACCESS_SEIZE (1 << 3)
73 #define TPM_TIS_ACCESS_PENDING_REQUEST (1 << 2)
74 #define TPM_TIS_ACCESS_REQUEST_USE (1 << 1)
75 #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0)
76
77 #define TPM_TIS_INT_ENABLED (1 << 31)
78 #define TPM_TIS_INT_DATA_AVAILABLE (1 << 0)
79 #define TPM_TIS_INT_STS_VALID (1 << 1)
80 #define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2)
81 #define TPM_TIS_INT_COMMAND_READY (1 << 7)
82
83 #define TPM_TIS_INT_POLARITY_MASK (3 << 3)
84 #define TPM_TIS_INT_POLARITY_LOW_LEVEL (1 << 3)
85
86 #define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \
87 TPM_TIS_INT_DATA_AVAILABLE | \
88 TPM_TIS_INT_STS_VALID | \
89 TPM_TIS_INT_COMMAND_READY)
90
91 #define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)
92 #define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)
93 #define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9)
94 #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)
95 #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8)
96 #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */
97 #define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \
98 (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
99 TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
100 TPM_TIS_CAP_DATA_TRANSFER_64B | \
101 TPM_TIS_CAP_INTERFACE_VERSION1_3 | \
102 TPM_TIS_INTERRUPTS_SUPPORTED)
103
104 #define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \
105 (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
106 TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
107 TPM_TIS_CAP_DATA_TRANSFER_64B | \
108 TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \
109 TPM_TIS_INTERRUPTS_SUPPORTED)
110
111 #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */
112 #define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */
113 #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */
114 #define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */
115 #define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */
116 #define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */
117
118 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \
119 (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \
120 (~0u << 4)/* all of it is don't care */)
121
122 /* if backend was a TPM 2.0: */
123 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \
124 (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \
125 TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \
126 TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \
127 TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)
128
129 #define TPM_TIS_TPM_DID 0x0001
130 #define TPM_TIS_TPM_VID PCI_VENDOR_ID_IBM
131 #define TPM_TIS_TPM_RID 0x0001
132
133 #define TPM_TIS_NO_DATA_BYTE 0xff
134
135
136 REG32(CRB_LOC_STATE, 0x00)
137 FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)
138 FIELD(CRB_LOC_STATE, locAssigned, 1, 1)
139 FIELD(CRB_LOC_STATE, activeLocality, 2, 3)
140 FIELD(CRB_LOC_STATE, reserved, 5, 2)
141 FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1)
142 REG32(CRB_LOC_CTRL, 0x08)
143 REG32(CRB_LOC_STS, 0x0C)
144 FIELD(CRB_LOC_STS, Granted, 0, 1)
145 FIELD(CRB_LOC_STS, beenSeized, 1, 1)
146 REG32(CRB_INTF_ID, 0x30)
147 FIELD(CRB_INTF_ID, InterfaceType, 0, 4)
148 FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4)
149 FIELD(CRB_INTF_ID, CapLocality, 8, 1)
150 FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1)
151 FIELD(CRB_INTF_ID, Reserved1, 10, 1)
152 FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2)
153 FIELD(CRB_INTF_ID, CapFIFO, 13, 1)
154 FIELD(CRB_INTF_ID, CapCRB, 14, 1)
155 FIELD(CRB_INTF_ID, CapIFRes, 15, 2)
156 FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2)
157 FIELD(CRB_INTF_ID, IntfSelLock, 19, 1)
158 FIELD(CRB_INTF_ID, Reserved2, 20, 4)
159 FIELD(CRB_INTF_ID, RID, 24, 8)
160 REG32(CRB_INTF_ID2, 0x34)
161 FIELD(CRB_INTF_ID2, VID, 0, 16)
162 FIELD(CRB_INTF_ID2, DID, 16, 16)
163 REG32(CRB_CTRL_EXT, 0x38)
164 REG32(CRB_CTRL_REQ, 0x40)
165 REG32(CRB_CTRL_STS, 0x44)
166 FIELD(CRB_CTRL_STS, tpmSts, 0, 1)
167 FIELD(CRB_CTRL_STS, tpmIdle, 1, 1)
168 REG32(CRB_CTRL_CANCEL, 0x48)
169 REG32(CRB_CTRL_START, 0x4C)
170 REG32(CRB_INT_ENABLED, 0x50)
171 REG32(CRB_INT_STS, 0x54)
172 REG32(CRB_CTRL_CMD_SIZE, 0x58)
173 REG32(CRB_CTRL_CMD_LADDR, 0x5C)
174 REG32(CRB_CTRL_CMD_HADDR, 0x60)
175 REG32(CRB_CTRL_RSP_SIZE, 0x64)
176 REG32(CRB_CTRL_RSP_ADDR, 0x68)
177 REG32(CRB_DATA_BUFFER, 0x80)
178
179 #define TPM_CRB_ADDR_BASE 0xFED40000
180 #define TPM_CRB_ADDR_SIZE 0x1000
181 #define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ)
182 #define TPM_CRB_R_MAX R_CRB_DATA_BUFFER
183
184 #define TPM_LOG_AREA_MINIMUM_SIZE (64 * KiB)
185
186 #define TPM_TCPA_ACPI_CLASS_CLIENT 0
187 #define TPM_TCPA_ACPI_CLASS_SERVER 1
188
189 #define TPM2_ACPI_CLASS_CLIENT 0
190 #define TPM2_ACPI_CLASS_SERVER 1
191
192 #define TPM2_START_METHOD_MMIO 6
193 #define TPM2_START_METHOD_CRB 7
194
195 /*
196 * Physical Presence Interface
197 */
198 #define TPM_PPI_ADDR_SIZE 0x400
199 #define TPM_PPI_ADDR_BASE 0xFED45000
200
201 #define TPM_PPI_VERSION_NONE 0
202 #define TPM_PPI_VERSION_1_30 1
203
204 /* whether function is blocked by BIOS settings; bits 0, 1, 2 */
205 #define TPM_PPI_FUNC_NOT_IMPLEMENTED (0 << 0)
206 #define TPM_PPI_FUNC_BIOS_ONLY (1 << 0)
207 #define TPM_PPI_FUNC_BLOCKED (2 << 0)
208 #define TPM_PPI_FUNC_ALLOWED_USR_REQ (3 << 0)
209 #define TPM_PPI_FUNC_ALLOWED_USR_NOT_REQ (4 << 0)
210 #define TPM_PPI_FUNC_MASK (7 << 0)
211
212 void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);
213
214 #endif /* CONFIG_TPM */
215
216 #endif /* HW_ACPI_TPM_H */