Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into staging
[qemu.git] / include / hw / adc / stm32f2xx_adc.h
1 /*
2 * STM32F2XX ADC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef HW_STM32F2XX_ADC_H
26 #define HW_STM32F2XX_ADC_H
27
28 #include "hw/sysbus.h"
29 #include "qom/object.h"
30
31 #define ADC_SR 0x00
32 #define ADC_CR1 0x04
33 #define ADC_CR2 0x08
34 #define ADC_SMPR1 0x0C
35 #define ADC_SMPR2 0x10
36 #define ADC_JOFR1 0x14
37 #define ADC_JOFR2 0x18
38 #define ADC_JOFR3 0x1C
39 #define ADC_JOFR4 0x20
40 #define ADC_HTR 0x24
41 #define ADC_LTR 0x28
42 #define ADC_SQR1 0x2C
43 #define ADC_SQR2 0x30
44 #define ADC_SQR3 0x34
45 #define ADC_JSQR 0x38
46 #define ADC_JDR1 0x3C
47 #define ADC_JDR2 0x40
48 #define ADC_JDR3 0x44
49 #define ADC_JDR4 0x48
50 #define ADC_DR 0x4C
51
52 #define ADC_CR2_ADON 0x01
53 #define ADC_CR2_CONT 0x02
54 #define ADC_CR2_ALIGN 0x800
55 #define ADC_CR2_SWSTART 0x40000000
56
57 #define ADC_CR1_RES 0x3000000
58
59 #define ADC_COMMON_ADDRESS 0x100
60
61 #define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
62 OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXADCState, STM32F2XX_ADC)
63
64 struct STM32F2XXADCState {
65 /* <private> */
66 SysBusDevice parent_obj;
67
68 /* <public> */
69 MemoryRegion mmio;
70
71 uint32_t adc_sr;
72 uint32_t adc_cr1;
73 uint32_t adc_cr2;
74 uint32_t adc_smpr1;
75 uint32_t adc_smpr2;
76 uint32_t adc_jofr[4];
77 uint32_t adc_htr;
78 uint32_t adc_ltr;
79 uint32_t adc_sqr1;
80 uint32_t adc_sqr2;
81 uint32_t adc_sqr3;
82 uint32_t adc_jsqr;
83 uint32_t adc_jdr[4];
84 uint32_t adc_dr;
85
86 qemu_irq irq;
87 };
88
89 #endif /* HW_STM32F2XX_ADC_H */