block/export: Add query-block-exports
[qemu.git] / include / hw / arm / armsse.h
1 /*
2 * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /*
13 * This is a model of the Arm "Subsystems for Embedded" family of
14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
15 * SSE-200. Currently we model:
16 * - the Arm IoT Kit which is documented in
17 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
18 * - the SSE-200 which is documented in
19 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
20 *
21 * The IoTKit contains:
22 * a Cortex-M33
23 * the IDAU
24 * some timers and watchdogs
25 * two peripheral protection controllers
26 * a memory protection controller
27 * a security controller
28 * a bus fabric which arranges that some parts of the address
29 * space are secure and non-secure aliases of each other
30 * The SSE-200 additionally contains:
31 * a second Cortex-M33
32 * two Message Handling Units (MHUs)
33 * an optional CryptoCell (which we do not model)
34 * more SRAM banks with associated MPCs
35 * multiple Power Policy Units (PPUs)
36 * a control interface for an icache for each CPU
37 * per-CPU identity and control register blocks
38 *
39 * QEMU interface:
40 * + QOM property "memory" is a MemoryRegion containing the devices provided
41 * by the board model.
42 * + QOM property "MAINCLK" is the frequency of the main system clock
43 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
44 * (In hardware, the SSE-200 permits the number of expansion interrupts
45 * for the two CPUs to be configured separately, but we restrict it to
46 * being the same for both, to avoid having to have separate Property
47 * lists for different variants. This restriction can be relaxed later
48 * if necessary.)
49 * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
50 * address of each SRAM bank (and thus the total amount of internal SRAM)
51 * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
52 * (where it expects to load the PC and SP from the vector table on reset)
53 * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which
54 * set whether the CPUs have the FPU and DSP features present. The default
55 * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
56 * SSE-200 both are present; CPU0 in an SSE-200 has neither.
57 * Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
58 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
59 * which are wired to its NVIC lines 32 .. n+32
60 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
61 * CPU 1, which are wired to its NVIC lines 32 .. n+32
62 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
63 * bus master devices in the board model to make transactions into
64 * all the devices and memory areas in the IoTKit
65 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
66 * might provide:
67 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
68 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
69 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
70 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
71 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
72 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
73 * might provide:
74 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
75 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
76 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
77 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
78 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
79 * Controlling each of the 16 expansion MPCs which a system using the IoTKit
80 * might provide:
81 * + named GPIO inputs mpcexp_status[0..15]
82 * Controlling each of the 16 expansion MSCs which a system using the IoTKit
83 * might provide:
84 * + named GPIO inputs mscexp_status[0..15]
85 * + named GPIO outputs mscexp_clear[0..15]
86 * + named GPIO outputs mscexp_ns[0..15]
87 */
88
89 #ifndef ARMSSE_H
90 #define ARMSSE_H
91
92 #include "hw/sysbus.h"
93 #include "hw/arm/armv7m.h"
94 #include "hw/misc/iotkit-secctl.h"
95 #include "hw/misc/tz-ppc.h"
96 #include "hw/misc/tz-mpc.h"
97 #include "hw/timer/cmsdk-apb-timer.h"
98 #include "hw/timer/cmsdk-apb-dualtimer.h"
99 #include "hw/watchdog/cmsdk-apb-watchdog.h"
100 #include "hw/misc/iotkit-sysctl.h"
101 #include "hw/misc/iotkit-sysinfo.h"
102 #include "hw/misc/armsse-cpuid.h"
103 #include "hw/misc/armsse-mhu.h"
104 #include "hw/misc/unimp.h"
105 #include "hw/or-irq.h"
106 #include "hw/core/split-irq.h"
107 #include "hw/cpu/cluster.h"
108 #include "qom/object.h"
109
110 #define TYPE_ARM_SSE "arm-sse"
111 OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
112 ARM_SSE)
113
114 /*
115 * These type names are for specific IoTKit subsystems; other than
116 * instantiating them, code using these devices should always handle
117 * them via the ARMSSE base class, so they have no IOTKIT() etc macros.
118 */
119 #define TYPE_IOTKIT "iotkit"
120 #define TYPE_SSE200 "sse-200"
121
122 /* We have an IRQ splitter and an OR gate input for each external PPC
123 * and the 2 internal PPCs
124 */
125 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
126 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
127
128 #define MAX_SRAM_BANKS 4
129 #if MAX_SRAM_BANKS > IOTS_NUM_MPC
130 #error Too many SRAM banks
131 #endif
132
133 #define SSE_MAX_CPUS 2
134
135 /* These define what each PPU in the ppu[] index is for */
136 #define CPU0CORE_PPU 0
137 #define CPU1CORE_PPU 1
138 #define DBG_PPU 2
139 #define RAM0_PPU 3
140 #define RAM1_PPU 4
141 #define RAM2_PPU 5
142 #define RAM3_PPU 6
143 #define NUM_PPUS 7
144
145 struct ARMSSE {
146 /*< private >*/
147 SysBusDevice parent_obj;
148
149 /*< public >*/
150 ARMv7MState armv7m[SSE_MAX_CPUS];
151 CPUClusterState cluster[SSE_MAX_CPUS];
152 IoTKitSecCtl secctl;
153 TZPPC apb_ppc0;
154 TZPPC apb_ppc1;
155 TZMPC mpc[IOTS_NUM_MPC];
156 CMSDKAPBTIMER timer0;
157 CMSDKAPBTIMER timer1;
158 CMSDKAPBTIMER s32ktimer;
159 qemu_or_irq ppc_irq_orgate;
160 SplitIRQ sec_resp_splitter;
161 SplitIRQ ppc_irq_splitter[NUM_PPCS];
162 SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
163 qemu_or_irq mpc_irq_orgate;
164 qemu_or_irq nmi_orgate;
165
166 SplitIRQ cpu_irq_splitter[32];
167
168 CMSDKAPBDualTimer dualtimer;
169
170 CMSDKAPBWatchdog s32kwatchdog;
171 CMSDKAPBWatchdog nswatchdog;
172 CMSDKAPBWatchdog swatchdog;
173
174 IoTKitSysCtl sysctl;
175 IoTKitSysCtl sysinfo;
176
177 ARMSSEMHU mhu[2];
178 UnimplementedDeviceState ppu[NUM_PPUS];
179 UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
180 UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
181
182 ARMSSECPUID cpuid[SSE_MAX_CPUS];
183
184 /*
185 * 'container' holds all devices seen by all CPUs.
186 * 'cpu_container[i]' is the view that CPU i has: this has the
187 * per-CPU devices of that CPU, plus as the background 'container'
188 * (or an alias of it, since we can only use it directly once).
189 * container_alias[i] is the alias of 'container' used by CPU i+1;
190 * CPU 0 can use 'container' directly.
191 */
192 MemoryRegion container;
193 MemoryRegion container_alias[SSE_MAX_CPUS - 1];
194 MemoryRegion cpu_container[SSE_MAX_CPUS];
195 MemoryRegion alias1;
196 MemoryRegion alias2;
197 MemoryRegion alias3[SSE_MAX_CPUS];
198 MemoryRegion sram[MAX_SRAM_BANKS];
199
200 qemu_irq *exp_irqs[SSE_MAX_CPUS];
201 qemu_irq ppc0_irq;
202 qemu_irq ppc1_irq;
203 qemu_irq sec_resp_cfg;
204 qemu_irq sec_resp_cfg_in;
205 qemu_irq nsc_cfg_in;
206
207 qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
208 qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
209
210 uint32_t nsccfg;
211
212 /* Properties */
213 MemoryRegion *board_memory;
214 uint32_t exp_numirq;
215 uint32_t mainclk_frq;
216 uint32_t sram_addr_width;
217 uint32_t init_svtor;
218 bool cpu_fpu[SSE_MAX_CPUS];
219 bool cpu_dsp[SSE_MAX_CPUS];
220 };
221
222 typedef struct ARMSSEInfo ARMSSEInfo;
223
224 struct ARMSSEClass {
225 SysBusDeviceClass parent_class;
226 const ARMSSEInfo *info;
227 };
228
229
230 #endif