Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request...
[qemu.git] / include / hw / arm / armv7m.h
1 /*
2 * ARMv7M CPU object
3 *
4 * Copyright (c) 2017 Linaro Ltd
5 * Written by Peter Maydell <peter.maydell@linaro.org>
6 *
7 * This code is licensed under the GPL version 2 or later.
8 */
9
10 #ifndef HW_ARM_ARMV7M_H
11 #define HW_ARM_ARMV7M_H
12
13 #include "hw/sysbus.h"
14 #include "hw/intc/armv7m_nvic.h"
15 #include "target/arm/idau.h"
16 #include "qom/object.h"
17
18 #define TYPE_BITBAND "ARM-bitband-memory"
19 OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
20
21 struct BitBandState {
22 /*< private >*/
23 SysBusDevice parent_obj;
24 /*< public >*/
25
26 AddressSpace source_as;
27 MemoryRegion iomem;
28 uint32_t base;
29 MemoryRegion *source_memory;
30 };
31
32 #define TYPE_ARMV7M "armv7m"
33 OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
34
35 #define ARMV7M_NUM_BITBANDS 2
36
37 /* ARMv7M container object.
38 * + Unnamed GPIO input lines: external IRQ lines for the NVIC
39 * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
40 * If this GPIO is not wired up then the NVIC will default to performing
41 * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
42 * + Property "cpu-type": CPU type to instantiate
43 * + Property "num-irq": number of external IRQ lines
44 * + Property "memory": MemoryRegion defining the physical address space
45 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
46 * devices will be automatically layered on top of this view.)
47 * + Property "idau": IDAU interface (forwarded to CPU object)
48 * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
49 * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object)
50 * + Property "vfp": enable VFP (forwarded to CPU object)
51 * + Property "dsp": enable DSP (forwarded to CPU object)
52 * + Property "enable-bitband": expose bitbanded IO
53 */
54 struct ARMv7MState {
55 /*< private >*/
56 SysBusDevice parent_obj;
57 /*< public >*/
58 NVICState nvic;
59 BitBandState bitband[ARMV7M_NUM_BITBANDS];
60 ARMCPU *cpu;
61
62 /* MemoryRegion we pass to the CPU, with our devices layered on
63 * top of the ones the board provides in board_memory.
64 */
65 MemoryRegion container;
66
67 /* Properties */
68 char *cpu_type;
69 /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
70 MemoryRegion *board_memory;
71 Object *idau;
72 uint32_t init_svtor;
73 uint32_t init_nsvtor;
74 bool enable_bitband;
75 bool start_powered_off;
76 bool vfp;
77 bool dsp;
78 };
79
80 #endif