hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriately
[qemu.git] / include / hw / arm / aspeed_soc.h
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/arm/arm.h"
16 #include "hw/intc/aspeed_vic.h"
17 #include "hw/misc/aspeed_scu.h"
18 #include "hw/misc/aspeed_sdmc.h"
19 #include "hw/timer/aspeed_timer.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "hw/ssi/aspeed_smc.h"
22
23 #define ASPEED_SPIS_NUM 2
24
25 typedef struct AspeedSoCState {
26 /*< private >*/
27 DeviceState parent;
28
29 /*< public >*/
30 ARMCPU cpu;
31 MemoryRegion iomem;
32 MemoryRegion sram;
33 AspeedVICState vic;
34 AspeedTimerCtrlState timerctrl;
35 AspeedI2CState i2c;
36 AspeedSCUState scu;
37 AspeedSMCState fmc;
38 AspeedSMCState spi[ASPEED_SPIS_NUM];
39 AspeedSDMCState sdmc;
40 } AspeedSoCState;
41
42 #define TYPE_ASPEED_SOC "aspeed-soc"
43 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
44
45 typedef struct AspeedSoCInfo {
46 const char *name;
47 const char *cpu_model;
48 uint32_t silicon_rev;
49 hwaddr sdram_base;
50 uint64_t sram_size;
51 int spis_num;
52 const hwaddr *spi_bases;
53 const char *fmc_typename;
54 const char **spi_typename;
55 } AspeedSoCInfo;
56
57 typedef struct AspeedSoCClass {
58 DeviceClass parent_class;
59 AspeedSoCInfo *info;
60 } AspeedSoCClass;
61
62 #define ASPEED_SOC_CLASS(klass) \
63 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
64 #define ASPEED_SOC_GET_CLASS(obj) \
65 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
66
67 #endif /* ASPEED_SOC_H */