aspeed: introduce a configurable number of CPU per machine
[qemu.git] / include / hw / arm / aspeed_soc.h
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/intc/aspeed_vic.h"
16 #include "hw/misc/aspeed_scu.h"
17 #include "hw/misc/aspeed_sdmc.h"
18 #include "hw/timer/aspeed_timer.h"
19 #include "hw/timer/aspeed_rtc.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "hw/ssi/aspeed_smc.h"
22 #include "hw/watchdog/wdt_aspeed.h"
23 #include "hw/net/ftgmac100.h"
24
25 #define ASPEED_SPIS_NUM 2
26 #define ASPEED_WDTS_NUM 3
27 #define ASPEED_CPUS_NUM 2
28
29 typedef struct AspeedSoCState {
30 /*< private >*/
31 DeviceState parent;
32
33 /*< public >*/
34 ARMCPU cpu[ASPEED_CPUS_NUM];
35 uint32_t num_cpus;
36 MemoryRegion sram;
37 AspeedVICState vic;
38 AspeedRtcState rtc;
39 AspeedTimerCtrlState timerctrl;
40 AspeedI2CState i2c;
41 AspeedSCUState scu;
42 AspeedSMCState fmc;
43 AspeedSMCState spi[ASPEED_SPIS_NUM];
44 AspeedSDMCState sdmc;
45 AspeedWDTState wdt[ASPEED_WDTS_NUM];
46 FTGMAC100State ftgmac100;
47 } AspeedSoCState;
48
49 #define TYPE_ASPEED_SOC "aspeed-soc"
50 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
51
52 typedef struct AspeedSoCInfo {
53 const char *name;
54 const char *cpu_type;
55 uint32_t silicon_rev;
56 uint64_t sram_size;
57 int spis_num;
58 const char *fmc_typename;
59 const char **spi_typename;
60 int wdts_num;
61 const int *irqmap;
62 const hwaddr *memmap;
63 uint32_t num_cpus;
64 } AspeedSoCInfo;
65
66 typedef struct AspeedSoCClass {
67 DeviceClass parent_class;
68 AspeedSoCInfo *info;
69 } AspeedSoCClass;
70
71 #define ASPEED_SOC_CLASS(klass) \
72 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
73 #define ASPEED_SOC_GET_CLASS(obj) \
74 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
75
76 enum {
77 ASPEED_IOMEM,
78 ASPEED_UART1,
79 ASPEED_UART2,
80 ASPEED_UART3,
81 ASPEED_UART4,
82 ASPEED_UART5,
83 ASPEED_VUART,
84 ASPEED_FMC,
85 ASPEED_SPI1,
86 ASPEED_SPI2,
87 ASPEED_VIC,
88 ASPEED_SDMC,
89 ASPEED_SCU,
90 ASPEED_ADC,
91 ASPEED_SRAM,
92 ASPEED_GPIO,
93 ASPEED_RTC,
94 ASPEED_TIMER1,
95 ASPEED_TIMER2,
96 ASPEED_TIMER3,
97 ASPEED_TIMER4,
98 ASPEED_TIMER5,
99 ASPEED_TIMER6,
100 ASPEED_TIMER7,
101 ASPEED_TIMER8,
102 ASPEED_WDT,
103 ASPEED_PWM,
104 ASPEED_LPC,
105 ASPEED_IBT,
106 ASPEED_I2C,
107 ASPEED_ETH1,
108 ASPEED_ETH2,
109 ASPEED_SDRAM,
110 };
111
112 #endif /* ASPEED_SOC_H */