Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging
[qemu.git] / include / hw / arm / aspeed_soc.h
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/intc/aspeed_vic.h"
17 #include "hw/misc/aspeed_scu.h"
18 #include "hw/misc/aspeed_sdmc.h"
19 #include "hw/misc/aspeed_xdma.h"
20 #include "hw/timer/aspeed_timer.h"
21 #include "hw/rtc/aspeed_rtc.h"
22 #include "hw/i2c/aspeed_i2c.h"
23 #include "hw/ssi/aspeed_smc.h"
24 #include "hw/misc/aspeed_hace.h"
25 #include "hw/watchdog/wdt_aspeed.h"
26 #include "hw/net/ftgmac100.h"
27 #include "target/arm/cpu.h"
28 #include "hw/gpio/aspeed_gpio.h"
29 #include "hw/sd/aspeed_sdhci.h"
30 #include "hw/usb/hcd-ehci.h"
31 #include "qom/object.h"
32 #include "hw/misc/aspeed_lpc.h"
33
34 #define ASPEED_SPIS_NUM 2
35 #define ASPEED_EHCIS_NUM 2
36 #define ASPEED_WDTS_NUM 4
37 #define ASPEED_CPUS_NUM 2
38 #define ASPEED_MACS_NUM 4
39
40 struct AspeedSoCState {
41 /*< private >*/
42 DeviceState parent;
43
44 /*< public >*/
45 ARMCPU cpu[ASPEED_CPUS_NUM];
46 A15MPPrivState a7mpcore;
47 MemoryRegion *dram_mr;
48 MemoryRegion sram;
49 AspeedVICState vic;
50 AspeedRtcState rtc;
51 AspeedTimerCtrlState timerctrl;
52 AspeedI2CState i2c;
53 AspeedSCUState scu;
54 AspeedHACEState hace;
55 AspeedXDMAState xdma;
56 AspeedSMCState fmc;
57 AspeedSMCState spi[ASPEED_SPIS_NUM];
58 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
59 AspeedSDMCState sdmc;
60 AspeedWDTState wdt[ASPEED_WDTS_NUM];
61 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
62 AspeedMiiState mii[ASPEED_MACS_NUM];
63 AspeedGPIOState gpio;
64 AspeedGPIOState gpio_1_8v;
65 AspeedSDHCIState sdhci;
66 AspeedSDHCIState emmc;
67 AspeedLPCState lpc;
68 };
69
70 #define TYPE_ASPEED_SOC "aspeed-soc"
71 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
72
73 struct AspeedSoCClass {
74 DeviceClass parent_class;
75
76 const char *name;
77 const char *cpu_type;
78 uint32_t silicon_rev;
79 uint64_t sram_size;
80 int spis_num;
81 int ehcis_num;
82 int wdts_num;
83 int macs_num;
84 const int *irqmap;
85 const hwaddr *memmap;
86 uint32_t num_cpus;
87 };
88
89
90 enum {
91 ASPEED_DEV_IOMEM,
92 ASPEED_DEV_UART1,
93 ASPEED_DEV_UART2,
94 ASPEED_DEV_UART3,
95 ASPEED_DEV_UART4,
96 ASPEED_DEV_UART5,
97 ASPEED_DEV_VUART,
98 ASPEED_DEV_FMC,
99 ASPEED_DEV_SPI1,
100 ASPEED_DEV_SPI2,
101 ASPEED_DEV_EHCI1,
102 ASPEED_DEV_EHCI2,
103 ASPEED_DEV_VIC,
104 ASPEED_DEV_SDMC,
105 ASPEED_DEV_SCU,
106 ASPEED_DEV_ADC,
107 ASPEED_DEV_VIDEO,
108 ASPEED_DEV_SRAM,
109 ASPEED_DEV_SDHCI,
110 ASPEED_DEV_GPIO,
111 ASPEED_DEV_GPIO_1_8V,
112 ASPEED_DEV_RTC,
113 ASPEED_DEV_TIMER1,
114 ASPEED_DEV_TIMER2,
115 ASPEED_DEV_TIMER3,
116 ASPEED_DEV_TIMER4,
117 ASPEED_DEV_TIMER5,
118 ASPEED_DEV_TIMER6,
119 ASPEED_DEV_TIMER7,
120 ASPEED_DEV_TIMER8,
121 ASPEED_DEV_WDT,
122 ASPEED_DEV_PWM,
123 ASPEED_DEV_LPC,
124 ASPEED_DEV_IBT,
125 ASPEED_DEV_I2C,
126 ASPEED_DEV_ETH1,
127 ASPEED_DEV_ETH2,
128 ASPEED_DEV_ETH3,
129 ASPEED_DEV_ETH4,
130 ASPEED_DEV_MII1,
131 ASPEED_DEV_MII2,
132 ASPEED_DEV_MII3,
133 ASPEED_DEV_MII4,
134 ASPEED_DEV_SDRAM,
135 ASPEED_DEV_XDMA,
136 ASPEED_DEV_EMMC,
137 ASPEED_DEV_KCS,
138 ASPEED_DEV_HACE,
139 };
140
141 #endif /* ASPEED_SOC_H */