ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / arm / fsl-imx25.h
1 /*
2 * Freescale i.MX25 SoC emulation
3 *
4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #ifndef FSL_IMX25_H
18 #define FSL_IMX25_H
19
20 #include "hw/arm/boot.h"
21 #include "hw/intc/imx_avic.h"
22 #include "hw/misc/imx25_ccm.h"
23 #include "hw/char/imx_serial.h"
24 #include "hw/timer/imx_gpt.h"
25 #include "hw/timer/imx_epit.h"
26 #include "hw/net/imx_fec.h"
27 #include "hw/misc/imx_rngc.h"
28 #include "hw/i2c/imx_i2c.h"
29 #include "hw/gpio/imx_gpio.h"
30 #include "hw/sd/sdhci.h"
31 #include "hw/usb/chipidea.h"
32 #include "hw/watchdog/wdt_imx2.h"
33 #include "exec/memory.h"
34 #include "target/arm/cpu.h"
35
36 #define TYPE_FSL_IMX25 "fsl,imx25"
37 #define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
38
39 #define FSL_IMX25_NUM_UARTS 5
40 #define FSL_IMX25_NUM_GPTS 4
41 #define FSL_IMX25_NUM_EPITS 2
42 #define FSL_IMX25_NUM_I2CS 3
43 #define FSL_IMX25_NUM_GPIOS 4
44 #define FSL_IMX25_NUM_ESDHCS 2
45 #define FSL_IMX25_NUM_USBS 2
46
47 typedef struct FslIMX25State {
48 /*< private >*/
49 DeviceState parent_obj;
50
51 /*< public >*/
52 ARMCPU cpu;
53 IMXAVICState avic;
54 IMX25CCMState ccm;
55 IMXSerialState uart[FSL_IMX25_NUM_UARTS];
56 IMXGPTState gpt[FSL_IMX25_NUM_GPTS];
57 IMXEPITState epit[FSL_IMX25_NUM_EPITS];
58 IMXFECState fec;
59 IMXRNGCState rngc;
60 IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
61 IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
62 SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
63 ChipideaState usb[FSL_IMX25_NUM_USBS];
64 IMX2WdtState wdt;
65 MemoryRegion rom[2];
66 MemoryRegion iram;
67 MemoryRegion iram_alias;
68 uint32_t phy_num;
69 } FslIMX25State;
70
71 /**
72 * i.MX25 memory map
73 ****************************************************************
74 * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
75 * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved
76 * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes)
77 * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved
78 * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved
79 * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved
80 * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved
81 * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved
82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
83 * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
84 * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL
85 * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers
86 * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory
87 * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers
88 * 0x43F1_8000 0x43F7_FFFF 416 Kbytes Reserved
89 * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
90 * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3
91 * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1
92 * 0x43F8_C000 0x43F8_FFFF 16 Kbytes CAN-2
93 * 0x43F9_0000 0x43F9_3FFF 16 Kbytes UART-1
94 * 0x43F9_4000 0x43F9_7FFF 16 Kbytes UART-2
95 * 0x43F9_8000 0x43F9_BFFF 16 Kbytes I2C-2
96 * 0x43F9_C000 0x43F9_FFFF 16 Kbytes 1-Wire
97 * 0x43FA_0000 0x43FA_3FFF 16 Kbytes ATA (CPU side)
98 * 0x43FA_4000 0x43FA_7FFF 16 Kbytes CSPI-1
99 * 0x43FA_8000 0x43FA_BFFF 16 Kbytes KPP
100 * 0x43FA_C000 0x43FA_FFFF 16 Kbytes IOMUXC
101 * 0x43FB_0000 0x43FB_3FFF 16 Kbytes AUDMUX
102 * 0x43FB_4000 0x43FB_7FFF 16 Kbytes Reserved
103 * 0x43FB_8000 0x43FB_BFFF 16 Kbytes ECT (IP BUS A)
104 * 0x43FB_C000 0x43FB_FFFF 16 Kbytes ECT (IP BUS B)
105 * 0x43FC_0000 0x43FF_FFFF 256 Kbytes Reserved AIPS A off-platform slots
106 * 0x4400_0000 0x4FFF_FFFF 192 Mbytes Reserved
107 * 0x5000_0000 0x5000_3FFF 16 Kbytes SPBA base address
108 * 0x5000_4000 0x5000_7FFF 16 Kbytes CSPI-3
109 * 0x5000_8000 0x5000_BFFF 16 Kbytes UART-4
110 * 0x5000_C000 0x5000_FFFF 16 Kbytes UART-3
111 * 0x5001_0000 0x5001_3FFF 16 Kbytes CSPI-2
112 * 0x5001_4000 0x5001_7FFF 16 Kbytes SSI-2
113 * 0x5001_C000 0x5001_FFFF 16 Kbytes Reserved
114 * 0x5002_0000 0x5002_3FFF 16 Kbytes ATA
115 * 0x5002_4000 0x5002_7FFF 16 Kbytes SIM-1
116 * 0x5002_8000 0x5002_BFFF 16 Kbytes SIM-2
117 * 0x5002_C000 0x5002_FFFF 16 Kbytes UART-5
118 * 0x5003_0000 0x5003_3FFF 16 Kbytes TSC
119 * 0x5003_4000 0x5003_7FFF 16 Kbytes SSI-1
120 * 0x5003_8000 0x5003_BFFF 16 Kbytes FEC
121 * 0x5003_C000 0x5003_FFFF 16 Kbytes SPBA registers
122 * 0x5004_0000 0x51FF_FFFF 32 Mbytes (minus 256 Kbytes)
123 * 0x5200_0000 0x53EF_FFFF 31 Mbytes Reserved
124 * 0x53F0_0000 0x53F0_3FFF 16 Kbytes AIPS B control registers
125 * 0x53F0_4000 0x53F7_FFFF 496 Kbytes Reserved
126 * 0x53F8_0000 0x53F8_3FFF 16 Kbytes CCM
127 * 0x53F8_4000 0x53F8_7FFF 16 Kbytes GPT-4
128 * 0x53F8_8000 0x53F8_BFFF 16 Kbytes GPT-3
129 * 0x53F8_C000 0x53F8_FFFF 16 Kbytes GPT-2
130 * 0x53F9_0000 0x53F9_3FFF 16 Kbytes GPT-1
131 * 0x53F9_4000 0x53F9_7FFF 16 Kbytes EPIT-1
132 * 0x53F9_8000 0x53F9_BFFF 16 Kbytes EPIT-2
133 * 0x53F9_C000 0x53F9_FFFF 16 Kbytes GPIO-4
134 * 0x53FA_0000 0x53FA_3FFF 16 Kbytes PWM-2
135 * 0x53FA_4000 0x53FA_7FFF 16 Kbytes GPIO-3
136 * 0x53FA_8000 0x53FA_BFFF 16 Kbytes PWM-3
137 * 0x53FA_C000 0x53FA_FFFF 16 Kbytes SCC
138 * 0x53FB_0000 0x53FB_3FFF 16 Kbytes RNGB
139 * 0x53FB_4000 0x53FB_7FFF 16 Kbytes eSDHC-1
140 * 0x53FB_8000 0x53FB_BFFF 16 Kbytes eSDHC-2
141 * 0x53FB_C000 0x53FB_FFFF 16 Kbytes LCDC
142 * 0x53FC_0000 0x53FC_3FFF 16 Kbytes SLCDC
143 * 0x53FC_4000 0x53FC_7FFF 16 Kbytes Reserved
144 * 0x53FC_8000 0x53FC_BFFF 16 Kbytes PWM-4
145 * 0x53FC_C000 0x53FC_FFFF 16 Kbytes GPIO-1
146 * 0x53FD_0000 0x53FD_3FFF 16 Kbytes GPIO-2
147 * 0x53FD_4000 0x53FD_7FFF 16 Kbytes SDMA
148 * 0x53FD_8000 0x53FD_BFFF 16 Kbytes Reserved
149 * 0x53FD_C000 0x53FD_FFFF 16 Kbytes WDOG
150 * 0x53FE_0000 0x53FE_3FFF 16 Kbytes PWM-1
151 * 0x53FE_4000 0x53FE_7FFF 16 Kbytes Reserved
152 * 0x53FE_8000 0x53FE_BFFF 16 Kbytes Reserved
153 * 0x53FE_C000 0x53FE_FFFF 16 Kbytes RTICv3
154 * 0x53FF_0000 0x53FF_3FFF 16 Kbytes IIM
155 * 0x53FF_4000 0x53FF_7FFF 16 Kbytes USB
156 * 0x53FF_8000 0x53FF_BFFF 16 Kbytes CSI
157 * 0x53FF_C000 0x53FF_FFFF 16 Kbytes DryIce
158 * 0x5400_0000 0x5FFF_FFFF 192 Mbytes Reserved (aliased AIPS B slots)
159 * 0x6000_0000 0x67FF_FFFF 128 Mbytes ARM926 platform ROMPATCH
160 * 0x6800_0000 0x6FFF_FFFF 128 Mbytes ARM926 platform ASIC
161 * 0x7000_0000 0x77FF_FFFF 128 Mbytes Reserved
162 * 0x7800_0000 0x7801_FFFF 128 Kbytes RAM
163 * 0x7802_0000 0x7FFF_FFFF 128 Mbytes (minus 128 Kbytes)
164 * 0x8000_0000 0x8FFF_FFFF 256 Mbytes SDRAM bank 0
165 * 0x9000_0000 0x9FFF_FFFF 256 Mbytes SDRAM bank 1
166 * 0xA000_0000 0xA7FF_FFFF 128 Mbytes WEIM CS0 (flash 128) 1
167 * 0xA800_0000 0xAFFF_FFFF 128 Mbytes WEIM CS1 (flash 64) 1
168 * 0xB000_0000 0xB1FF_FFFF 32 Mbytes WEIM CS2 (SRAM)
169 * 0xB200_0000 0xB3FF_FFFF 32 Mbytes WEIM CS3 (SRAM)
170 * 0xB400_0000 0xB5FF_FFFF 32 Mbytes WEIM CS4
171 * 0xB600_0000 0xB7FF_FFFF 32 Mbytes Reserved
172 * 0xB800_0000 0xB800_0FFF 4 Kbytes Reserved
173 * 0xB800_1000 0xB800_1FFF 4 Kbytes SDRAM control registers
174 * 0xB800_2000 0xB800_2FFF 4 Kbytes WEIM control registers
175 * 0xB800_3000 0xB800_3FFF 4 Kbytes M3IF control registers
176 * 0xB800_4000 0xB800_4FFF 4 Kbytes EMI control registers
177 * 0xB800_5000 0xBAFF_FFFF 32 Mbytes (minus 20 Kbytes)
178 * 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer
179 * 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer
180 * 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved
181 * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control regisers
182 * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
183 * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved
184 */
185
186 #define FSL_IMX25_ROM0_ADDR 0x00000000
187 #define FSL_IMX25_ROM0_SIZE 0x4000
188 #define FSL_IMX25_ROM1_ADDR 0x00404000
189 #define FSL_IMX25_ROM1_SIZE 0x4000
190 #define FSL_IMX25_I2C1_ADDR 0x43F80000
191 #define FSL_IMX25_I2C1_SIZE 0x4000
192 #define FSL_IMX25_I2C3_ADDR 0x43F84000
193 #define FSL_IMX25_I2C3_SIZE 0x4000
194 #define FSL_IMX25_UART1_ADDR 0x43F90000
195 #define FSL_IMX25_UART1_SIZE 0x4000
196 #define FSL_IMX25_UART2_ADDR 0x43F94000
197 #define FSL_IMX25_UART2_SIZE 0x4000
198 #define FSL_IMX25_I2C2_ADDR 0x43F98000
199 #define FSL_IMX25_I2C2_SIZE 0x4000
200 #define FSL_IMX25_UART4_ADDR 0x50008000
201 #define FSL_IMX25_UART4_SIZE 0x4000
202 #define FSL_IMX25_UART3_ADDR 0x5000C000
203 #define FSL_IMX25_UART3_SIZE 0x4000
204 #define FSL_IMX25_UART5_ADDR 0x5002C000
205 #define FSL_IMX25_UART5_SIZE 0x4000
206 #define FSL_IMX25_FEC_ADDR 0x50038000
207 #define FSL_IMX25_CCM_ADDR 0x53F80000
208 #define FSL_IMX25_CCM_SIZE 0x4000
209 #define FSL_IMX25_GPT4_ADDR 0x53F84000
210 #define FSL_IMX25_GPT4_SIZE 0x4000
211 #define FSL_IMX25_GPT3_ADDR 0x53F88000
212 #define FSL_IMX25_GPT3_SIZE 0x4000
213 #define FSL_IMX25_GPT2_ADDR 0x53F8C000
214 #define FSL_IMX25_GPT2_SIZE 0x4000
215 #define FSL_IMX25_GPT1_ADDR 0x53F90000
216 #define FSL_IMX25_GPT1_SIZE 0x4000
217 #define FSL_IMX25_EPIT1_ADDR 0x53F94000
218 #define FSL_IMX25_EPIT1_SIZE 0x4000
219 #define FSL_IMX25_EPIT2_ADDR 0x53F98000
220 #define FSL_IMX25_EPIT2_SIZE 0x4000
221 #define FSL_IMX25_GPIO4_ADDR 0x53F9C000
222 #define FSL_IMX25_GPIO4_SIZE 0x4000
223 #define FSL_IMX25_GPIO3_ADDR 0x53FA4000
224 #define FSL_IMX25_GPIO3_SIZE 0x4000
225 #define FSL_IMX25_RNGC_ADDR 0x53FB0000
226 #define FSL_IMX25_RNGC_SIZE 0x4000
227 #define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
228 #define FSL_IMX25_ESDHC1_SIZE 0x4000
229 #define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
230 #define FSL_IMX25_ESDHC2_SIZE 0x4000
231 #define FSL_IMX25_GPIO1_ADDR 0x53FCC000
232 #define FSL_IMX25_GPIO1_SIZE 0x4000
233 #define FSL_IMX25_GPIO2_ADDR 0x53FD0000
234 #define FSL_IMX25_GPIO2_SIZE 0x4000
235 #define FSL_IMX25_WDT_ADDR 0x53FDC000
236 #define FSL_IMX25_WDT_SIZE 0x4000
237 #define FSL_IMX25_USB1_ADDR 0x53FF4000
238 #define FSL_IMX25_USB1_SIZE 0x0200
239 #define FSL_IMX25_USB2_ADDR 0x53FF4400
240 #define FSL_IMX25_USB2_SIZE 0x0200
241 #define FSL_IMX25_AVIC_ADDR 0x68000000
242 #define FSL_IMX25_AVIC_SIZE 0x4000
243 #define FSL_IMX25_IRAM_ADDR 0x78000000
244 #define FSL_IMX25_IRAM_SIZE 0x20000
245 #define FSL_IMX25_IRAM_ALIAS_ADDR 0x78020000
246 #define FSL_IMX25_IRAM_ALIAS_SIZE 0x7FE0000
247 #define FSL_IMX25_SDRAM0_ADDR 0x80000000
248 #define FSL_IMX25_SDRAM0_SIZE 0x10000000
249 #define FSL_IMX25_SDRAM1_ADDR 0x90000000
250 #define FSL_IMX25_SDRAM1_SIZE 0x10000000
251
252 #define FSL_IMX25_UART1_IRQ 45
253 #define FSL_IMX25_UART2_IRQ 32
254 #define FSL_IMX25_UART3_IRQ 18
255 #define FSL_IMX25_UART4_IRQ 5
256 #define FSL_IMX25_UART5_IRQ 40
257 #define FSL_IMX25_GPT1_IRQ 54
258 #define FSL_IMX25_GPT2_IRQ 53
259 #define FSL_IMX25_GPT3_IRQ 29
260 #define FSL_IMX25_GPT4_IRQ 1
261 #define FSL_IMX25_EPIT1_IRQ 28
262 #define FSL_IMX25_EPIT2_IRQ 27
263 #define FSL_IMX25_FEC_IRQ 57
264 #define FSL_IMX25_RNGC_IRQ 22
265 #define FSL_IMX25_I2C1_IRQ 3
266 #define FSL_IMX25_I2C2_IRQ 4
267 #define FSL_IMX25_I2C3_IRQ 10
268 #define FSL_IMX25_GPIO1_IRQ 52
269 #define FSL_IMX25_GPIO2_IRQ 51
270 #define FSL_IMX25_GPIO3_IRQ 16
271 #define FSL_IMX25_GPIO4_IRQ 23
272 #define FSL_IMX25_ESDHC1_IRQ 9
273 #define FSL_IMX25_ESDHC2_IRQ 8
274 #define FSL_IMX25_USB1_IRQ 37
275 #define FSL_IMX25_USB2_IRQ 35
276 #define FSL_IMX25_WDT_IRQ 55
277
278 #endif /* FSL_IMX25_H */