hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriately
[qemu.git] / include / hw / arm / fsl-imx31.h
1 /*
2 * Freescale i.MX31 SoC emulation
3 *
4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #ifndef FSL_IMX31_H
18 #define FSL_IMX31_H
19
20 #include "hw/arm/arm.h"
21 #include "hw/intc/imx_avic.h"
22 #include "hw/misc/imx31_ccm.h"
23 #include "hw/char/imx_serial.h"
24 #include "hw/timer/imx_gpt.h"
25 #include "hw/timer/imx_epit.h"
26 #include "hw/i2c/imx_i2c.h"
27 #include "hw/gpio/imx_gpio.h"
28 #include "exec/memory.h"
29
30 #define TYPE_FSL_IMX31 "fsl,imx31"
31 #define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
32
33 #define FSL_IMX31_NUM_UARTS 2
34 #define FSL_IMX31_NUM_EPITS 2
35 #define FSL_IMX31_NUM_I2CS 3
36 #define FSL_IMX31_NUM_GPIOS 3
37
38 typedef struct FslIMX31State {
39 /*< private >*/
40 DeviceState parent_obj;
41
42 /*< public >*/
43 ARMCPU cpu;
44 IMXAVICState avic;
45 IMX31CCMState ccm;
46 IMXSerialState uart[FSL_IMX31_NUM_UARTS];
47 IMXGPTState gpt;
48 IMXEPITState epit[FSL_IMX31_NUM_EPITS];
49 IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
50 IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
51 MemoryRegion secure_rom;
52 MemoryRegion rom;
53 MemoryRegion iram;
54 MemoryRegion iram_alias;
55 } FslIMX31State;
56
57 #define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
58 #define FSL_IMX31_SECURE_ROM_SIZE 0x4000
59 #define FSL_IMX31_ROM_ADDR 0x00404000
60 #define FSL_IMX31_ROM_SIZE 0x4000
61 #define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
62 #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
63 #define FSL_IMX31_IRAM_ADDR 0x1FFFC000
64 #define FSL_IMX31_IRAM_SIZE 0x4000
65 #define FSL_IMX31_I2C1_ADDR 0x43F80000
66 #define FSL_IMX31_I2C1_SIZE 0x4000
67 #define FSL_IMX31_I2C3_ADDR 0x43F84000
68 #define FSL_IMX31_I2C3_SIZE 0x4000
69 #define FSL_IMX31_UART1_ADDR 0x43F90000
70 #define FSL_IMX31_UART1_SIZE 0x4000
71 #define FSL_IMX31_UART2_ADDR 0x43F94000
72 #define FSL_IMX31_UART2_SIZE 0x4000
73 #define FSL_IMX31_I2C2_ADDR 0x43F98000
74 #define FSL_IMX31_I2C2_SIZE 0x4000
75 #define FSL_IMX31_CCM_ADDR 0x53F80000
76 #define FSL_IMX31_CCM_SIZE 0x4000
77 #define FSL_IMX31_GPT_ADDR 0x53F90000
78 #define FSL_IMX31_GPT_SIZE 0x4000
79 #define FSL_IMX31_EPIT1_ADDR 0x53F94000
80 #define FSL_IMX31_EPIT1_SIZE 0x4000
81 #define FSL_IMX31_EPIT2_ADDR 0x53F98000
82 #define FSL_IMX31_EPIT2_SIZE 0x4000
83 #define FSL_IMX31_GPIO3_ADDR 0x53FA4000
84 #define FSL_IMX31_GPIO3_SIZE 0x4000
85 #define FSL_IMX31_GPIO1_ADDR 0x53FCC000
86 #define FSL_IMX31_GPIO1_SIZE 0x4000
87 #define FSL_IMX31_GPIO2_ADDR 0x53FD0000
88 #define FSL_IMX31_GPIO2_SIZE 0x4000
89 #define FSL_IMX31_AVIC_ADDR 0x68000000
90 #define FSL_IMX31_AVIC_SIZE 0x100
91 #define FSL_IMX31_SDRAM0_ADDR 0x80000000
92 #define FSL_IMX31_SDRAM0_SIZE 0x10000000
93 #define FSL_IMX31_SDRAM1_ADDR 0x90000000
94 #define FSL_IMX31_SDRAM1_SIZE 0x10000000
95 #define FSL_IMX31_FLASH0_ADDR 0xA0000000
96 #define FSL_IMX31_FLASH0_SIZE 0x8000000
97 #define FSL_IMX31_FLASH1_ADDR 0xA8000000
98 #define FSL_IMX31_FLASH1_SIZE 0x8000000
99 #define FSL_IMX31_CS2_ADDR 0xB0000000
100 #define FSL_IMX31_CS2_SIZE 0x2000000
101 #define FSL_IMX31_CS3_ADDR 0xB2000000
102 #define FSL_IMX31_CS3_SIZE 0x2000000
103 #define FSL_IMX31_CS4_ADDR 0xB4000000
104 #define FSL_IMX31_CS4_SIZE 0x2000000
105 #define FSL_IMX31_CS5_ADDR 0xB6000000
106 #define FSL_IMX31_CS5_SIZE 0x2000000
107 #define FSL_IMX31_NAND_ADDR 0xB8000000
108 #define FSL_IMX31_NAND_SIZE 0x1000
109
110 #define FSL_IMX31_EPIT2_IRQ 27
111 #define FSL_IMX31_EPIT1_IRQ 28
112 #define FSL_IMX31_GPT_IRQ 29
113 #define FSL_IMX31_UART2_IRQ 32
114 #define FSL_IMX31_UART1_IRQ 45
115 #define FSL_IMX31_I2C1_IRQ 10
116 #define FSL_IMX31_I2C2_IRQ 4
117 #define FSL_IMX31_I2C3_IRQ 3
118 #define FSL_IMX31_GPIO1_IRQ 52
119 #define FSL_IMX31_GPIO2_IRQ 51
120 #define FSL_IMX31_GPIO3_IRQ 56
121
122 #endif /* FSL_IMX31_H */