block/export: Add query-block-exports
[qemu.git] / include / hw / arm / fsl-imx7.h
1 /*
2 * Copyright (c) 2018, Impinj, Inc.
3 *
4 * i.MX7 SoC definitions
5 *
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #ifndef FSL_IMX7_H
20 #define FSL_IMX7_H
21
22 #include "hw/arm/boot.h"
23 #include "hw/cpu/a15mpcore.h"
24 #include "hw/intc/imx_gpcv2.h"
25 #include "hw/misc/imx7_ccm.h"
26 #include "hw/misc/imx7_snvs.h"
27 #include "hw/misc/imx7_gpr.h"
28 #include "hw/misc/imx6_src.h"
29 #include "hw/watchdog/wdt_imx2.h"
30 #include "hw/gpio/imx_gpio.h"
31 #include "hw/char/imx_serial.h"
32 #include "hw/timer/imx_gpt.h"
33 #include "hw/timer/imx_epit.h"
34 #include "hw/i2c/imx_i2c.h"
35 #include "hw/gpio/imx_gpio.h"
36 #include "hw/sd/sdhci.h"
37 #include "hw/ssi/imx_spi.h"
38 #include "hw/net/imx_fec.h"
39 #include "hw/pci-host/designware.h"
40 #include "hw/usb/chipidea.h"
41 #include "cpu.h"
42 #include "qom/object.h"
43
44 #define TYPE_FSL_IMX7 "fsl,imx7"
45 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
46
47 enum FslIMX7Configuration {
48 FSL_IMX7_NUM_CPUS = 2,
49 FSL_IMX7_NUM_UARTS = 7,
50 FSL_IMX7_NUM_ETHS = 2,
51 FSL_IMX7_ETH_NUM_TX_RINGS = 3,
52 FSL_IMX7_NUM_USDHCS = 3,
53 FSL_IMX7_NUM_WDTS = 4,
54 FSL_IMX7_NUM_GPTS = 4,
55 FSL_IMX7_NUM_IOMUXCS = 2,
56 FSL_IMX7_NUM_GPIOS = 7,
57 FSL_IMX7_NUM_I2CS = 4,
58 FSL_IMX7_NUM_ECSPIS = 4,
59 FSL_IMX7_NUM_USBS = 3,
60 FSL_IMX7_NUM_ADCS = 2,
61 };
62
63 struct FslIMX7State {
64 /*< private >*/
65 DeviceState parent_obj;
66
67 /*< public >*/
68 ARMCPU cpu[FSL_IMX7_NUM_CPUS];
69 A15MPPrivState a7mpcore;
70 IMXGPTState gpt[FSL_IMX7_NUM_GPTS];
71 IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS];
72 IMX7CCMState ccm;
73 IMX7AnalogState analog;
74 IMX7SNVSState snvs;
75 IMXGPCv2State gpcv2;
76 IMXSPIState spi[FSL_IMX7_NUM_ECSPIS];
77 IMXI2CState i2c[FSL_IMX7_NUM_I2CS];
78 IMXSerialState uart[FSL_IMX7_NUM_UARTS];
79 IMXFECState eth[FSL_IMX7_NUM_ETHS];
80 SDHCIState usdhc[FSL_IMX7_NUM_USDHCS];
81 IMX2WdtState wdt[FSL_IMX7_NUM_WDTS];
82 IMX7GPRState gpr;
83 ChipideaState usb[FSL_IMX7_NUM_USBS];
84 DesignwarePCIEHost pcie;
85 uint32_t phy_num[FSL_IMX7_NUM_ETHS];
86 };
87
88 enum FslIMX7MemoryMap {
89 FSL_IMX7_MMDC_ADDR = 0x80000000,
90 FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
91
92 FSL_IMX7_GPIO1_ADDR = 0x30200000,
93 FSL_IMX7_GPIO2_ADDR = 0x30210000,
94 FSL_IMX7_GPIO3_ADDR = 0x30220000,
95 FSL_IMX7_GPIO4_ADDR = 0x30230000,
96 FSL_IMX7_GPIO5_ADDR = 0x30240000,
97 FSL_IMX7_GPIO6_ADDR = 0x30250000,
98 FSL_IMX7_GPIO7_ADDR = 0x30260000,
99
100 FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
101
102 FSL_IMX7_WDOG1_ADDR = 0x30280000,
103 FSL_IMX7_WDOG2_ADDR = 0x30290000,
104 FSL_IMX7_WDOG3_ADDR = 0x302A0000,
105 FSL_IMX7_WDOG4_ADDR = 0x302B0000,
106
107 FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
108
109 FSL_IMX7_GPT1_ADDR = 0x302D0000,
110 FSL_IMX7_GPT2_ADDR = 0x302E0000,
111 FSL_IMX7_GPT3_ADDR = 0x302F0000,
112 FSL_IMX7_GPT4_ADDR = 0x30300000,
113
114 FSL_IMX7_IOMUXC_ADDR = 0x30330000,
115 FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
116 FSL_IMX7_IOMUXCn_SIZE = 0x1000,
117
118 FSL_IMX7_OCOTP_ADDR = 0x30350000,
119 FSL_IMX7_OCOTP_SIZE = 0x10000,
120
121 FSL_IMX7_ANALOG_ADDR = 0x30360000,
122 FSL_IMX7_SNVS_ADDR = 0x30370000,
123 FSL_IMX7_CCM_ADDR = 0x30380000,
124
125 FSL_IMX7_SRC_ADDR = 0x30390000,
126 FSL_IMX7_SRC_SIZE = 0x1000,
127
128 FSL_IMX7_ADC1_ADDR = 0x30610000,
129 FSL_IMX7_ADC2_ADDR = 0x30620000,
130 FSL_IMX7_ADCn_SIZE = 0x1000,
131
132 FSL_IMX7_PWM1_ADDR = 0x30660000,
133 FSL_IMX7_PWM2_ADDR = 0x30670000,
134 FSL_IMX7_PWM3_ADDR = 0x30680000,
135 FSL_IMX7_PWM4_ADDR = 0x30690000,
136 FSL_IMX7_PWMn_SIZE = 0x10000,
137
138 FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
139 FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
140
141 FSL_IMX7_GPC_ADDR = 0x303A0000,
142
143 FSL_IMX7_CAAM_ADDR = 0x30900000,
144 FSL_IMX7_CAAM_SIZE = 0x40000,
145
146 FSL_IMX7_CAN1_ADDR = 0x30A00000,
147 FSL_IMX7_CAN2_ADDR = 0x30A10000,
148 FSL_IMX7_CANn_SIZE = 0x10000,
149
150 FSL_IMX7_I2C1_ADDR = 0x30A20000,
151 FSL_IMX7_I2C2_ADDR = 0x30A30000,
152 FSL_IMX7_I2C3_ADDR = 0x30A40000,
153 FSL_IMX7_I2C4_ADDR = 0x30A50000,
154
155 FSL_IMX7_ECSPI1_ADDR = 0x30820000,
156 FSL_IMX7_ECSPI2_ADDR = 0x30830000,
157 FSL_IMX7_ECSPI3_ADDR = 0x30840000,
158 FSL_IMX7_ECSPI4_ADDR = 0x30630000,
159
160 FSL_IMX7_LCDIF_ADDR = 0x30730000,
161 FSL_IMX7_LCDIF_SIZE = 0x1000,
162
163 FSL_IMX7_UART1_ADDR = 0x30860000,
164 /*
165 * Some versions of the reference manual claim that UART2 is @
166 * 0x30870000, but experiments with HW + DT files in upstream
167 * Linux kernel show that not to be true and that block is
168 * acutally located @ 0x30890000
169 */
170 FSL_IMX7_UART2_ADDR = 0x30890000,
171 FSL_IMX7_UART3_ADDR = 0x30880000,
172 FSL_IMX7_UART4_ADDR = 0x30A60000,
173 FSL_IMX7_UART5_ADDR = 0x30A70000,
174 FSL_IMX7_UART6_ADDR = 0x30A80000,
175 FSL_IMX7_UART7_ADDR = 0x30A90000,
176
177 FSL_IMX7_ENET1_ADDR = 0x30BE0000,
178 FSL_IMX7_ENET2_ADDR = 0x30BF0000,
179
180 FSL_IMX7_USB1_ADDR = 0x30B10000,
181 FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
182 FSL_IMX7_USB2_ADDR = 0x30B20000,
183 FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
184 FSL_IMX7_USB3_ADDR = 0x30B30000,
185 FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
186 FSL_IMX7_USBMISCn_SIZE = 0x200,
187
188 FSL_IMX7_USDHC1_ADDR = 0x30B40000,
189 FSL_IMX7_USDHC2_ADDR = 0x30B50000,
190 FSL_IMX7_USDHC3_ADDR = 0x30B60000,
191
192 FSL_IMX7_SDMA_ADDR = 0x30BD0000,
193 FSL_IMX7_SDMA_SIZE = 0x1000,
194
195 FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
196 FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000,
197
198 FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
199 FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
200
201 FSL_IMX7_GPR_ADDR = 0x30340000,
202
203 FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
204 FSL_IMX7_DMA_APBH_SIZE = 0x2000,
205 };
206
207 enum FslIMX7IRQs {
208 FSL_IMX7_USDHC1_IRQ = 22,
209 FSL_IMX7_USDHC2_IRQ = 23,
210 FSL_IMX7_USDHC3_IRQ = 24,
211
212 FSL_IMX7_UART1_IRQ = 26,
213 FSL_IMX7_UART2_IRQ = 27,
214 FSL_IMX7_UART3_IRQ = 28,
215 FSL_IMX7_UART4_IRQ = 29,
216 FSL_IMX7_UART5_IRQ = 30,
217 FSL_IMX7_UART6_IRQ = 16,
218
219 FSL_IMX7_ECSPI1_IRQ = 31,
220 FSL_IMX7_ECSPI2_IRQ = 32,
221 FSL_IMX7_ECSPI3_IRQ = 33,
222 FSL_IMX7_ECSPI4_IRQ = 34,
223
224 FSL_IMX7_I2C1_IRQ = 35,
225 FSL_IMX7_I2C2_IRQ = 36,
226 FSL_IMX7_I2C3_IRQ = 37,
227 FSL_IMX7_I2C4_IRQ = 38,
228
229 FSL_IMX7_USB1_IRQ = 43,
230 FSL_IMX7_USB2_IRQ = 42,
231 FSL_IMX7_USB3_IRQ = 40,
232
233 FSL_IMX7_WDOG1_IRQ = 78,
234 FSL_IMX7_WDOG2_IRQ = 79,
235 FSL_IMX7_WDOG3_IRQ = 10,
236 FSL_IMX7_WDOG4_IRQ = 109,
237
238 FSL_IMX7_PCI_INTA_IRQ = 125,
239 FSL_IMX7_PCI_INTB_IRQ = 124,
240 FSL_IMX7_PCI_INTC_IRQ = 123,
241 FSL_IMX7_PCI_INTD_IRQ = 122,
242
243 FSL_IMX7_UART7_IRQ = 126,
244
245 #define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118))
246
247 FSL_IMX7_MAX_IRQ = 128,
248 };
249
250 #endif /* FSL_IMX7_H */