ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / arm / pxa.h
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
10 #ifndef PXA_H
11 #define PXA_H
12
13 #include "exec/memory.h"
14 #include "target/arm/cpu-qom.h"
15 #include "hw/pcmcia.h"
16
17 /* Interrupt numbers */
18 # define PXA2XX_PIC_SSP3 0
19 # define PXA2XX_PIC_USBH2 2
20 # define PXA2XX_PIC_USBH1 3
21 # define PXA2XX_PIC_KEYPAD 4
22 # define PXA2XX_PIC_PWRI2C 6
23 # define PXA25X_PIC_HWUART 7
24 # define PXA27X_PIC_OST_4_11 7
25 # define PXA2XX_PIC_GPIO_0 8
26 # define PXA2XX_PIC_GPIO_1 9
27 # define PXA2XX_PIC_GPIO_X 10
28 # define PXA2XX_PIC_I2S 13
29 # define PXA26X_PIC_ASSP 15
30 # define PXA25X_PIC_NSSP 16
31 # define PXA27X_PIC_SSP2 16
32 # define PXA2XX_PIC_LCD 17
33 # define PXA2XX_PIC_I2C 18
34 # define PXA2XX_PIC_ICP 19
35 # define PXA2XX_PIC_STUART 20
36 # define PXA2XX_PIC_BTUART 21
37 # define PXA2XX_PIC_FFUART 22
38 # define PXA2XX_PIC_MMC 23
39 # define PXA2XX_PIC_SSP 24
40 # define PXA2XX_PIC_DMA 25
41 # define PXA2XX_PIC_OST_0 26
42 # define PXA2XX_PIC_RTC1HZ 30
43 # define PXA2XX_PIC_RTCALARM 31
44
45 /* DMA requests */
46 # define PXA2XX_RX_RQ_I2S 2
47 # define PXA2XX_TX_RQ_I2S 3
48 # define PXA2XX_RX_RQ_BTUART 4
49 # define PXA2XX_TX_RQ_BTUART 5
50 # define PXA2XX_RX_RQ_FFUART 6
51 # define PXA2XX_TX_RQ_FFUART 7
52 # define PXA2XX_RX_RQ_SSP1 13
53 # define PXA2XX_TX_RQ_SSP1 14
54 # define PXA2XX_RX_RQ_SSP2 15
55 # define PXA2XX_TX_RQ_SSP2 16
56 # define PXA2XX_RX_RQ_ICP 17
57 # define PXA2XX_TX_RQ_ICP 18
58 # define PXA2XX_RX_RQ_STUART 19
59 # define PXA2XX_TX_RQ_STUART 20
60 # define PXA2XX_RX_RQ_MMCI 21
61 # define PXA2XX_TX_RQ_MMCI 22
62 # define PXA2XX_USB_RQ(x) ((x) + 24)
63 # define PXA2XX_RX_RQ_SSP3 66
64 # define PXA2XX_TX_RQ_SSP3 67
65
66 # define PXA2XX_SDRAM_BASE 0xa0000000
67 # define PXA2XX_INTERNAL_BASE 0x5c000000
68 # define PXA2XX_INTERNAL_SIZE 0x40000
69
70 /* pxa2xx_pic.c */
71 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
72
73 /* pxa2xx_gpio.c */
74 DeviceState *pxa2xx_gpio_init(hwaddr base,
75 ARMCPU *cpu, DeviceState *pic, int lines);
76 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
77
78 /* pxa2xx_dma.c */
79 DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
80 DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
81
82 /* pxa2xx_lcd.c */
83 typedef struct PXA2xxLCDState PXA2xxLCDState;
84 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
85 hwaddr base, qemu_irq irq);
86 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
87
88 /* pxa2xx_mmci.c */
89 #define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
90 typedef struct PXA2xxMMCIState PXA2xxMMCIState;
91 #define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
92
93 PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
94 hwaddr base,
95 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma);
96 void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
97 qemu_irq coverswitch);
98
99 /* pxa2xx_pcmcia.c */
100 #define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
101 typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
102 #define PXA2XX_PCMCIA(obj) \
103 OBJECT_CHECK(PXA2xxPCMCIAState, obj, TYPE_PXA2XX_PCMCIA)
104
105 PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
106 hwaddr base);
107 int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
108 int pxa2xx_pcmcia_detach(void *opaque);
109 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
110
111 /* pxa2xx_keypad.c */
112 struct keymap {
113 int8_t column;
114 int8_t row;
115 };
116 typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
117 PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
118 hwaddr base,
119 qemu_irq irq);
120 void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
121 const struct keymap *map, int size);
122
123 /* pxa2xx.c */
124 typedef struct PXA2xxI2CState PXA2xxI2CState;
125 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
126 qemu_irq irq, uint32_t page_size);
127 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
128
129 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
130 typedef struct PXA2xxI2SState PXA2xxI2SState;
131 #define PXA2XX_I2C(obj) \
132 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
133
134 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
135 typedef struct PXA2xxFIrState PXA2xxFIrState;
136 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
137
138 typedef struct {
139 ARMCPU *cpu;
140 DeviceState *pic;
141 qemu_irq reset;
142 MemoryRegion sdram;
143 MemoryRegion internal;
144 MemoryRegion cm_iomem;
145 MemoryRegion mm_iomem;
146 MemoryRegion pm_iomem;
147 DeviceState *dma;
148 DeviceState *gpio;
149 PXA2xxLCDState *lcd;
150 SSIBus **ssp;
151 PXA2xxI2CState *i2c[2];
152 PXA2xxMMCIState *mmc;
153 PXA2xxPCMCIAState *pcmcia[2];
154 PXA2xxI2SState *i2s;
155 PXA2xxFIrState *fir;
156 PXA2xxKeyPadState *kp;
157
158 /* Power management */
159 hwaddr pm_base;
160 uint32_t pm_regs[0x40];
161
162 /* Clock management */
163 hwaddr cm_base;
164 uint32_t cm_regs[4];
165 uint32_t clkcfg;
166
167 /* Memory management */
168 hwaddr mm_base;
169 uint32_t mm_regs[0x1a];
170
171 /* Performance monitoring */
172 uint32_t pmnc;
173 } PXA2xxState;
174
175 struct PXA2xxI2SState {
176 MemoryRegion iomem;
177 qemu_irq irq;
178 qemu_irq rx_dma;
179 qemu_irq tx_dma;
180 void (*data_req)(void *, int, int);
181
182 uint32_t control[2];
183 uint32_t status;
184 uint32_t mask;
185 uint32_t clk;
186
187 int enable;
188 int rx_len;
189 int tx_len;
190 void (*codec_out)(void *, uint32_t);
191 uint32_t (*codec_in)(void *);
192 void *opaque;
193
194 int fifo_len;
195 uint32_t fifo[16];
196 };
197
198 # define PA_FMT "0x%08lx"
199
200 PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
201 const char *revision);
202 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
203
204 #endif /* PXA_H */