hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriately
[qemu.git] / include / hw / arm / raspi_platform.h
1 /*
2 * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
3 *
4 * These definitions are derived from those in Raspbian Linux at
5 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
6 * where they carry the following notice:
7 *
8 * Copyright (C) 2010 Broadcom
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25 #define MCORE_OFFSET 0x0000 /* Fake frame buffer device
26 * (the multicore sync block) */
27 #define IC0_OFFSET 0x2000
28 #define ST_OFFSET 0x3000 /* System Timer */
29 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
30 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
31 #define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
32 #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
33 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
34 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
35 #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
36 * Doorbells & Mailboxes */
37 #define PM_OFFSET 0x100000 /* Power Management, Reset controller
38 * and Watchdog registers */
39 #define PCM_CLOCK_OFFSET 0x101098
40 #define RNG_OFFSET 0x104000
41 #define GPIO_OFFSET 0x200000
42 #define UART0_OFFSET 0x201000
43 #define MMCI0_OFFSET 0x202000
44 #define I2S_OFFSET 0x203000
45 #define SPI0_OFFSET 0x204000
46 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
47 #define UART1_OFFSET 0x215000
48 #define EMMC_OFFSET 0x300000
49 #define SMI_OFFSET 0x600000
50 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
51 #define USB_OFFSET 0x980000 /* DTC_OTG USB controller */
52 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
53
54 /* GPU interrupts */
55 #define INTERRUPT_TIMER0 0
56 #define INTERRUPT_TIMER1 1
57 #define INTERRUPT_TIMER2 2
58 #define INTERRUPT_TIMER3 3
59 #define INTERRUPT_CODEC0 4
60 #define INTERRUPT_CODEC1 5
61 #define INTERRUPT_CODEC2 6
62 #define INTERRUPT_JPEG 7
63 #define INTERRUPT_ISP 8
64 #define INTERRUPT_USB 9
65 #define INTERRUPT_3D 10
66 #define INTERRUPT_TRANSPOSER 11
67 #define INTERRUPT_MULTICORESYNC0 12
68 #define INTERRUPT_MULTICORESYNC1 13
69 #define INTERRUPT_MULTICORESYNC2 14
70 #define INTERRUPT_MULTICORESYNC3 15
71 #define INTERRUPT_DMA0 16
72 #define INTERRUPT_DMA1 17
73 #define INTERRUPT_DMA2 18
74 #define INTERRUPT_DMA3 19
75 #define INTERRUPT_DMA4 20
76 #define INTERRUPT_DMA5 21
77 #define INTERRUPT_DMA6 22
78 #define INTERRUPT_DMA7 23
79 #define INTERRUPT_DMA8 24
80 #define INTERRUPT_DMA9 25
81 #define INTERRUPT_DMA10 26
82 #define INTERRUPT_DMA11 27
83 #define INTERRUPT_DMA12 28
84 #define INTERRUPT_AUX 29
85 #define INTERRUPT_ARM 30
86 #define INTERRUPT_VPUDMA 31
87 #define INTERRUPT_HOSTPORT 32
88 #define INTERRUPT_VIDEOSCALER 33
89 #define INTERRUPT_CCP2TX 34
90 #define INTERRUPT_SDC 35
91 #define INTERRUPT_DSI0 36
92 #define INTERRUPT_AVE 37
93 #define INTERRUPT_CAM0 38
94 #define INTERRUPT_CAM1 39
95 #define INTERRUPT_HDMI0 40
96 #define INTERRUPT_HDMI1 41
97 #define INTERRUPT_PIXELVALVE1 42
98 #define INTERRUPT_I2CSPISLV 43
99 #define INTERRUPT_DSI1 44
100 #define INTERRUPT_PWA0 45
101 #define INTERRUPT_PWA1 46
102 #define INTERRUPT_CPR 47
103 #define INTERRUPT_SMI 48
104 #define INTERRUPT_GPIO0 49
105 #define INTERRUPT_GPIO1 50
106 #define INTERRUPT_GPIO2 51
107 #define INTERRUPT_GPIO3 52
108 #define INTERRUPT_I2C 53
109 #define INTERRUPT_SPI 54
110 #define INTERRUPT_I2SPCM 55
111 #define INTERRUPT_SDIO 56
112 #define INTERRUPT_UART 57
113 #define INTERRUPT_SLIMBUS 58
114 #define INTERRUPT_VEC 59
115 #define INTERRUPT_CPG 60
116 #define INTERRUPT_RNG 61
117 #define INTERRUPT_ARASANSDIO 62
118 #define INTERRUPT_AVSPMON 63
119
120 /* ARM CPU IRQs use a private number space */
121 #define INTERRUPT_ARM_TIMER 0
122 #define INTERRUPT_ARM_MAILBOX 1
123 #define INTERRUPT_ARM_DOORBELL_0 2
124 #define INTERRUPT_ARM_DOORBELL_1 3
125 #define INTERRUPT_VPU0_HALTED 4
126 #define INTERRUPT_VPU1_HALTED 5
127 #define INTERRUPT_ILLEGAL_TYPE0 6
128 #define INTERRUPT_ILLEGAL_TYPE1 7