hw/arm/raspi: Define various blocks base addresses
[qemu.git] / include / hw / arm / raspi_platform.h
1 /*
2 * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
3 *
4 * These definitions are derived from those in Raspbian Linux at
5 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
6 * where they carry the following notice:
7 *
8 * Copyright (C) 2010 Broadcom
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Various undocumented addresses and names come from Herman Hermitage's VC4
25 * documentation:
26 * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
27 */
28
29 #ifndef HW_ARM_RASPI_PLATFORM_H
30 #define HW_ARM_RASPI_PLATFORM_H
31
32 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
33 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
34 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
35 #define ST_OFFSET 0x3000 /* System Timer */
36 #define TXP_OFFSET 0x4000 /* Transposer */
37 #define JPEG_OFFSET 0x5000
38 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
39 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
40 #define ARBA_OFFSET 0x9000
41 #define BRDG_OFFSET 0xa000
42 #define ARM_OFFSET 0xB000 /* ARM control block */
43 #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
44 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
45 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
46 #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
47 * Doorbells & Mailboxes */
48 #define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
49 #define CM_OFFSET 0x101000 /* Clock Management */
50 #define A2W_OFFSET 0x102000 /* Reset controller */
51 #define AVS_OFFSET 0x103000 /* Audio Video Standard */
52 #define RNG_OFFSET 0x104000
53 #define GPIO_OFFSET 0x200000
54 #define UART0_OFFSET 0x201000 /* PL011 */
55 #define MMCI0_OFFSET 0x202000 /* Legacy MMC */
56 #define I2S_OFFSET 0x203000 /* PCM */
57 #define SPI0_OFFSET 0x204000 /* SPI master */
58 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
59 #define PIXV0_OFFSET 0x206000
60 #define PIXV1_OFFSET 0x207000
61 #define DPI_OFFSET 0x208000
62 #define DSI0_OFFSET 0x209000 /* Display Serial Interface */
63 #define PWM_OFFSET 0x20c000
64 #define PERM_OFFSET 0x20d000
65 #define TEC_OFFSET 0x20e000
66 #define OTP_OFFSET 0x20f000
67 #define SLIM_OFFSET 0x210000 /* SLIMbus */
68 #define CPG_OFFSET 0x211000
69 #define THERMAL_OFFSET 0x212000
70 #define AVSP_OFFSET 0x213000
71 #define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */
72 #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */
73 #define EMMC1_OFFSET 0x300000
74 #define EMMC2_OFFSET 0x340000
75 #define HVS_OFFSET 0x400000
76 #define SMI_OFFSET 0x600000
77 #define DSI1_OFFSET 0x700000
78 #define UCAM_OFFSET 0x800000
79 #define CMI_OFFSET 0x802000
80 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
81 #define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */
82 #define VECA_OFFSET 0x806000
83 #define PIXV2_OFFSET 0x807000
84 #define HDMI_OFFSET 0x808000
85 #define HDCP_OFFSET 0x809000
86 #define ARBR0_OFFSET 0x80a000
87 #define DBUS_OFFSET 0x900000
88 #define AVE0_OFFSET 0x910000
89 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
90 #define V3D_OFFSET 0xc00000
91 #define SDRAMC_OFFSET 0xe00000
92 #define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
93 #define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
94 #define ARBR1_OFFSET 0xe04000
95 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
96 #define DCRC_OFFSET 0xe07000
97 #define AXIP_OFFSET 0xe08000
98
99 /* GPU interrupts */
100 #define INTERRUPT_TIMER0 0
101 #define INTERRUPT_TIMER1 1
102 #define INTERRUPT_TIMER2 2
103 #define INTERRUPT_TIMER3 3
104 #define INTERRUPT_CODEC0 4
105 #define INTERRUPT_CODEC1 5
106 #define INTERRUPT_CODEC2 6
107 #define INTERRUPT_JPEG 7
108 #define INTERRUPT_ISP 8
109 #define INTERRUPT_USB 9
110 #define INTERRUPT_3D 10
111 #define INTERRUPT_TRANSPOSER 11
112 #define INTERRUPT_MULTICORESYNC0 12
113 #define INTERRUPT_MULTICORESYNC1 13
114 #define INTERRUPT_MULTICORESYNC2 14
115 #define INTERRUPT_MULTICORESYNC3 15
116 #define INTERRUPT_DMA0 16
117 #define INTERRUPT_DMA1 17
118 #define INTERRUPT_DMA2 18
119 #define INTERRUPT_DMA3 19
120 #define INTERRUPT_DMA4 20
121 #define INTERRUPT_DMA5 21
122 #define INTERRUPT_DMA6 22
123 #define INTERRUPT_DMA7 23
124 #define INTERRUPT_DMA8 24
125 #define INTERRUPT_DMA9 25
126 #define INTERRUPT_DMA10 26
127 #define INTERRUPT_DMA11 27
128 #define INTERRUPT_DMA12 28
129 #define INTERRUPT_AUX 29
130 #define INTERRUPT_ARM 30
131 #define INTERRUPT_VPUDMA 31
132 #define INTERRUPT_HOSTPORT 32
133 #define INTERRUPT_VIDEOSCALER 33
134 #define INTERRUPT_CCP2TX 34
135 #define INTERRUPT_SDC 35
136 #define INTERRUPT_DSI0 36
137 #define INTERRUPT_AVE 37
138 #define INTERRUPT_CAM0 38
139 #define INTERRUPT_CAM1 39
140 #define INTERRUPT_HDMI0 40
141 #define INTERRUPT_HDMI1 41
142 #define INTERRUPT_PIXELVALVE1 42
143 #define INTERRUPT_I2CSPISLV 43
144 #define INTERRUPT_DSI1 44
145 #define INTERRUPT_PWA0 45
146 #define INTERRUPT_PWA1 46
147 #define INTERRUPT_CPR 47
148 #define INTERRUPT_SMI 48
149 #define INTERRUPT_GPIO0 49
150 #define INTERRUPT_GPIO1 50
151 #define INTERRUPT_GPIO2 51
152 #define INTERRUPT_GPIO3 52
153 #define INTERRUPT_I2C 53
154 #define INTERRUPT_SPI 54
155 #define INTERRUPT_I2SPCM 55
156 #define INTERRUPT_SDIO 56
157 #define INTERRUPT_UART0 57
158 #define INTERRUPT_SLIMBUS 58
159 #define INTERRUPT_VEC 59
160 #define INTERRUPT_CPG 60
161 #define INTERRUPT_RNG 61
162 #define INTERRUPT_ARASANSDIO 62
163 #define INTERRUPT_AVSPMON 63
164
165 /* ARM CPU IRQs use a private number space */
166 #define INTERRUPT_ARM_TIMER 0
167 #define INTERRUPT_ARM_MAILBOX 1
168 #define INTERRUPT_ARM_DOORBELL_0 2
169 #define INTERRUPT_ARM_DOORBELL_1 3
170 #define INTERRUPT_VPU0_HALTED 4
171 #define INTERRUPT_VPU1_HALTED 5
172 #define INTERRUPT_ILLEGAL_TYPE0 6
173 #define INTERRUPT_ILLEGAL_TYPE1 7
174
175 #endif