ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / arm / smmu-common.h
1 /*
2 * ARM SMMU Support
3 *
4 * Copyright (C) 2015-2016 Broadcom Corporation
5 * Copyright (c) 2017 Red Hat, Inc.
6 * Written by Prem Mallappa, Eric Auger
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19 #ifndef HW_ARM_SMMU_COMMON_H
20 #define HW_ARM_SMMU_COMMON_H
21
22 #include "hw/sysbus.h"
23 #include "hw/pci/pci.h"
24
25 #define SMMU_PCI_BUS_MAX 256
26 #define SMMU_PCI_DEVFN_MAX 256
27 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
28
29 #define SMMU_MAX_VA_BITS 48
30
31 /*
32 * Page table walk error types
33 */
34 typedef enum {
35 SMMU_PTW_ERR_NONE,
36 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */
37 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
38 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */
39 SMMU_PTW_ERR_ACCESS, /* Access fault */
40 SMMU_PTW_ERR_PERMISSION, /* Permission fault */
41 } SMMUPTWEventType;
42
43 typedef struct SMMUPTWEventInfo {
44 SMMUPTWEventType type;
45 dma_addr_t addr; /* fetched address that induced an abort, if any */
46 } SMMUPTWEventInfo;
47
48 typedef struct SMMUTransTableInfo {
49 bool disabled; /* is the translation table disabled? */
50 uint64_t ttb; /* TT base address */
51 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/
52 uint8_t granule_sz; /* granule page shift */
53 bool had; /* hierarchical attribute disable */
54 } SMMUTransTableInfo;
55
56 typedef struct SMMUTLBEntry {
57 IOMMUTLBEntry entry;
58 uint8_t level;
59 uint8_t granule;
60 } SMMUTLBEntry;
61
62 /*
63 * Generic structure populated by derived SMMU devices
64 * after decoding the configuration information and used as
65 * input to the page table walk
66 */
67 typedef struct SMMUTransCfg {
68 int stage; /* translation stage */
69 bool aa64; /* arch64 or aarch32 translation table */
70 bool disabled; /* smmu is disabled */
71 bool bypassed; /* translation is bypassed */
72 bool aborted; /* translation is aborted */
73 uint64_t ttb; /* TT base address */
74 uint8_t oas; /* output address width */
75 uint8_t tbi; /* Top Byte Ignore */
76 uint16_t asid;
77 SMMUTransTableInfo tt[2];
78 uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
79 uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
80 } SMMUTransCfg;
81
82 typedef struct SMMUDevice {
83 void *smmu;
84 PCIBus *bus;
85 int devfn;
86 IOMMUMemoryRegion iommu;
87 AddressSpace as;
88 uint32_t cfg_cache_hits;
89 uint32_t cfg_cache_misses;
90 QLIST_ENTRY(SMMUDevice) next;
91 } SMMUDevice;
92
93 typedef struct SMMUPciBus {
94 PCIBus *bus;
95 SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */
96 } SMMUPciBus;
97
98 typedef struct SMMUIOTLBKey {
99 uint64_t iova;
100 uint16_t asid;
101 uint8_t tg;
102 uint8_t level;
103 } SMMUIOTLBKey;
104
105 typedef struct SMMUState {
106 /* <private> */
107 SysBusDevice dev;
108 const char *mrtypename;
109 MemoryRegion iomem;
110
111 GHashTable *smmu_pcibus_by_busptr;
112 GHashTable *configs; /* cache for configuration data */
113 GHashTable *iotlb;
114 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX];
115 PCIBus *pci_bus;
116 QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
117 uint8_t bus_num;
118 PCIBus *primary_bus;
119 } SMMUState;
120
121 typedef struct {
122 /* <private> */
123 SysBusDeviceClass parent_class;
124
125 /*< public >*/
126
127 DeviceRealize parent_realize;
128
129 } SMMUBaseClass;
130
131 #define TYPE_ARM_SMMU "arm-smmu"
132 #define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU)
133 #define ARM_SMMU_CLASS(klass) \
134 OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_ARM_SMMU)
135 #define ARM_SMMU_GET_CLASS(obj) \
136 OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARM_SMMU)
137
138 /* Return the SMMUPciBus handle associated to a PCI bus number */
139 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
140
141 /* Return the stream ID of an SMMU device */
142 static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
143 {
144 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
145 }
146
147 /**
148 * smmu_ptw - Perform the page table walk for a given iova / access flags
149 * pair, according to @cfg translation config
150 */
151 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
152 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
153
154 /**
155 * select_tt - compute which translation table shall be used according to
156 * the input iova and translation config and return the TT specific info
157 */
158 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
159
160 /* Return the iommu mr associated to @sid, or NULL if none */
161 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
162
163 #define SMMU_IOTLB_MAX_SIZE 256
164
165 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
166 SMMUTransTableInfo *tt, hwaddr iova);
167 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
168 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
169 uint8_t tg, uint8_t level);
170 void smmu_iotlb_inv_all(SMMUState *s);
171 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
172 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
173 uint8_t tg, uint64_t num_pages, uint8_t ttl);
174
175 /* Unmap the range of all the notifiers registered to any IOMMU mr */
176 void smmu_inv_notifiers_all(SMMUState *s);
177
178 /* Unmap the range of all the notifiers registered to @mr */
179 void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
180
181 #endif /* HW_ARM_SMMU_COMMON_H */