ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / arm / smmuv3.h
1 /*
2 * Copyright (C) 2014-2016 Broadcom Corporation
3 * Copyright (c) 2017 Red Hat, Inc.
4 * Written by Prem Mallappa, Eric Auger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #ifndef HW_ARM_SMMUV3_H
20 #define HW_ARM_SMMUV3_H
21
22 #include "hw/arm/smmu-common.h"
23 #include "hw/registerfields.h"
24
25 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
26
27 typedef struct SMMUQueue {
28 uint64_t base; /* base register */
29 uint32_t prod;
30 uint32_t cons;
31 uint8_t entry_size;
32 uint8_t log2size;
33 } SMMUQueue;
34
35 typedef struct SMMUv3State {
36 SMMUState smmu_state;
37
38 uint32_t features;
39 uint8_t sid_size;
40 uint8_t sid_split;
41
42 uint32_t idr[6];
43 uint32_t iidr;
44 uint32_t aidr;
45 uint32_t cr[3];
46 uint32_t cr0ack;
47 uint32_t statusr;
48 uint32_t irq_ctrl;
49 uint32_t gerror;
50 uint32_t gerrorn;
51 uint64_t gerror_irq_cfg0;
52 uint32_t gerror_irq_cfg1;
53 uint32_t gerror_irq_cfg2;
54 uint64_t strtab_base;
55 uint32_t strtab_base_cfg;
56 uint64_t eventq_irq_cfg0;
57 uint32_t eventq_irq_cfg1;
58 uint32_t eventq_irq_cfg2;
59
60 SMMUQueue eventq, cmdq;
61
62 qemu_irq irq[4];
63 QemuMutex mutex;
64 } SMMUv3State;
65
66 typedef enum {
67 SMMU_IRQ_EVTQ,
68 SMMU_IRQ_PRIQ,
69 SMMU_IRQ_CMD_SYNC,
70 SMMU_IRQ_GERROR,
71 } SMMUIrq;
72
73 typedef struct {
74 /*< private >*/
75 SMMUBaseClass smmu_base_class;
76 /*< public >*/
77
78 DeviceRealize parent_realize;
79 DeviceReset parent_reset;
80 } SMMUv3Class;
81
82 #define TYPE_ARM_SMMUV3 "arm-smmuv3"
83 #define ARM_SMMUV3(obj) OBJECT_CHECK(SMMUv3State, (obj), TYPE_ARM_SMMUV3)
84 #define ARM_SMMUV3_CLASS(klass) \
85 OBJECT_CLASS_CHECK(SMMUv3Class, (klass), TYPE_ARM_SMMUV3)
86 #define ARM_SMMUV3_GET_CLASS(obj) \
87 OBJECT_GET_CLASS(SMMUv3Class, (obj), TYPE_ARM_SMMUV3)
88
89 #endif